Retired PciIncompatibleDeviceSupportLib from IntelFrameworkModulePkg.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@8773 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
vanjeff
@ -91,8 +91,8 @@ SkipIsaAliasAperture (
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**/
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VOID
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InsertResourceNode (
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IN PCI_RESOURCE_NODE *Bridge,
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IN PCI_RESOURCE_NODE *ResNode
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IN OUT PCI_RESOURCE_NODE *Bridge,
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IN PCI_RESOURCE_NODE *ResNode
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)
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{
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LIST_ENTRY *CurrentLink;
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@ -352,7 +352,6 @@ CalculateResourceAperture (
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//
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// Apply padding resource if available
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//
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Offset = Aperture & (Node->Alignment);
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if (Offset != 0) {
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@ -375,7 +374,6 @@ CalculateResourceAperture (
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//
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// Consider the aperture alignment
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//
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CurrentLink = CurrentLink->ForwardLink;
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}
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@ -423,12 +421,12 @@ CalculateResourceAperture (
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**/
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VOID
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GetResourceFromDevice (
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IN PCI_IO_DEVICE *PciDev,
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IN PCI_RESOURCE_NODE *IoNode,
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IN PCI_RESOURCE_NODE *Mem32Node,
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IN PCI_RESOURCE_NODE *PMem32Node,
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IN PCI_RESOURCE_NODE *Mem64Node,
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IN PCI_RESOURCE_NODE *PMem64Node
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IN PCI_IO_DEVICE *PciDev,
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IN OUT PCI_RESOURCE_NODE *IoNode,
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IN OUT PCI_RESOURCE_NODE *Mem32Node,
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IN OUT PCI_RESOURCE_NODE *PMem32Node,
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IN OUT PCI_RESOURCE_NODE *Mem64Node,
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IN OUT PCI_RESOURCE_NODE *PMem64Node
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)
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{
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@ -582,14 +580,12 @@ CreateResourceNode (
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Node = NULL;
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Node = AllocatePool (sizeof (PCI_RESOURCE_NODE));
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Node = AllocateZeroPool (sizeof (PCI_RESOURCE_NODE));
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ASSERT (Node != NULL);
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if (Node == NULL) {
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return NULL;
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}
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ZeroMem (Node, sizeof (PCI_RESOURCE_NODE));
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Node->Signature = PCI_RESOURCE_SIGNATURE;
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Node->PciDev = PciDev;
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Node->Length = Length;
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@ -617,12 +613,12 @@ CreateResourceNode (
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**/
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VOID
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CreateResourceMap (
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IN PCI_IO_DEVICE *Bridge,
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IN PCI_RESOURCE_NODE *IoNode,
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IN PCI_RESOURCE_NODE *Mem32Node,
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IN PCI_RESOURCE_NODE *PMem32Node,
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IN PCI_RESOURCE_NODE *Mem64Node,
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IN PCI_RESOURCE_NODE *PMem64Node
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IN PCI_IO_DEVICE *Bridge,
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IN OUT PCI_RESOURCE_NODE *IoNode,
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IN OUT PCI_RESOURCE_NODE *Mem32Node,
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IN OUT PCI_RESOURCE_NODE *PMem32Node,
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IN OUT PCI_RESOURCE_NODE *Mem64Node,
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IN OUT PCI_RESOURCE_NODE *PMem64Node
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)
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{
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PCI_IO_DEVICE *Temp;
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@ -726,7 +722,7 @@ CreateResourceMap (
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IoBridge
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);
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} else {
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gBS->FreePool (IoBridge);
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FreePool (IoBridge);
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IoBridge = NULL;
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}
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@ -742,7 +738,7 @@ CreateResourceMap (
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Mem32Bridge
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);
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} else {
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gBS->FreePool (Mem32Bridge);
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FreePool (Mem32Bridge);
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Mem32Bridge = NULL;
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}
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@ -758,7 +754,7 @@ CreateResourceMap (
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PMem32Bridge
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);
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} else {
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gBS->FreePool (PMem32Bridge);
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FreePool (PMem32Bridge);
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PMem32Bridge = NULL;
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}
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@ -774,7 +770,7 @@ CreateResourceMap (
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Mem64Bridge
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);
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} else {
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gBS->FreePool (Mem64Bridge);
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FreePool (Mem64Bridge);
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Mem64Bridge = NULL;
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}
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@ -790,7 +786,7 @@ CreateResourceMap (
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PMem64Bridge
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);
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} else {
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gBS->FreePool (PMem64Bridge);
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FreePool (PMem64Bridge);
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PMem64Bridge = NULL;
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}
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@ -799,7 +795,6 @@ CreateResourceMap (
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//
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// If it is P2C, apply hard coded resource padding
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//
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//
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if (IS_CARDBUS_BRIDGE (&Temp->Pci)) {
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ResourcePaddingForCardBusBridge (
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Temp,
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@ -813,7 +808,7 @@ CreateResourceMap (
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CurrentLink = CurrentLink->ForwardLink;
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}
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//
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//
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// To do some platform specific resource padding ...
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//
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@ -1120,13 +1115,13 @@ ProgramBar (
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case PciBarTypeMem32:
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case PciBarTypePMem32:
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PciIoWrite (
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PciIo,
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EfiPciIoWidthUint32,
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(Node->PciDev->PciBar[Node->Bar]).Offset,
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1,
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&Address
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);
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PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint32,
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(Node->PciDev->PciBar[Node->Bar]).Offset,
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1,
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&Address
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);
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Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
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@ -1137,23 +1132,23 @@ ProgramBar (
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Address32 = (UINT32) (Address & 0x00000000FFFFFFFF);
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PciIoWrite (
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PciIo,
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EfiPciIoWidthUint32,
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(Node->PciDev->PciBar[Node->Bar]).Offset,
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1,
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&Address32
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);
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PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint32,
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(Node->PciDev->PciBar[Node->Bar]).Offset,
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1,
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&Address32
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);
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Address32 = (UINT32) RShiftU64 (Address, 32);
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PciIoWrite (
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PciIo,
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EfiPciIoWidthUint32,
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(UINT8) ((Node->PciDev->PciBar[Node->Bar]).Offset + 4),
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1,
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&Address32
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);
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PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint32,
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(UINT8) ((Node->PciDev->PciBar[Node->Bar]).Offset + 4),
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1,
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&Address32
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);
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Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
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@ -1205,13 +1200,13 @@ ProgramPpbApperture (
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case PPB_BAR_0:
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case PPB_BAR_1:
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PciIoWrite (
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PciIo,
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EfiPciIoWidthUint32,
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(Node->PciDev->PciBar[Node->Bar]).Offset,
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1,
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&Address
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);
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PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint32,
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(Node->PciDev->PciBar[Node->Bar]).Offset,
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1,
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&Address
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);
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Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
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Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
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@ -1221,41 +1216,41 @@ ProgramPpbApperture (
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case PPB_IO_RANGE:
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Address32 = ((UINT32) (Address)) >> 8;
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PciIoWrite (
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PciIo,
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EfiPciIoWidthUint8,
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0x1C,
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1,
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&Address32
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);
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PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint8,
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0x1C,
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1,
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&Address32
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);
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Address32 >>= 8;
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PciIoWrite (
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PciIo,
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EfiPciIoWidthUint16,
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0x30,
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1,
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&Address32
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);
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PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint16,
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0x30,
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1,
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&Address32
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);
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Address32 = (UINT32) (Address + Node->Length - 1);
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Address32 = ((UINT32) (Address32)) >> 8;
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PciIoWrite (
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PciIo,
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EfiPciIoWidthUint8,
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0x1D,
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1,
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&Address32
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);
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PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint8,
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0x1D,
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1,
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&Address32
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);
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Address32 >>= 8;
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PciIoWrite (
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PciIo,
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EfiPciIoWidthUint16,
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0x32,
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1,
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&Address32
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);
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PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint16,
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0x32,
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1,
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&Address32
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);
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Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
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Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
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@ -1264,23 +1259,23 @@ ProgramPpbApperture (
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case PPB_MEM32_RANGE:
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Address32 = ((UINT32) (Address)) >> 16;
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PciIoWrite (
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PciIo,
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EfiPciIoWidthUint16,
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0x20,
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1,
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&Address32
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);
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PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint16,
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0x20,
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1,
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&Address32
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);
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Address32 = (UINT32) (Address + Node->Length - 1);
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Address32 = ((UINT32) (Address32)) >> 16;
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PciIoWrite (
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PciIo,
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EfiPciIoWidthUint16,
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0x22,
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1,
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&Address32
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);
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PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint16,
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0x22,
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1,
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&Address32
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);
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Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
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Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
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@ -1290,41 +1285,41 @@ ProgramPpbApperture (
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case PPB_PMEM64_RANGE:
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Address32 = ((UINT32) (Address)) >> 16;
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PciIoWrite (
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PciIo,
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EfiPciIoWidthUint16,
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0x24,
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1,
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&Address32
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);
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PciIo->Pci.Write (
|
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PciIo,
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EfiPciIoWidthUint16,
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0x24,
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1,
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&Address32
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);
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Address32 = (UINT32) (Address + Node->Length - 1);
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Address32 = ((UINT32) (Address32)) >> 16;
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PciIoWrite (
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PciIo,
|
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EfiPciIoWidthUint16,
|
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0x26,
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1,
|
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&Address32
|
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);
|
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PciIo->Pci.Write (
|
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PciIo,
|
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EfiPciIoWidthUint16,
|
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0x26,
|
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1,
|
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&Address32
|
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);
|
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|
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Address32 = (UINT32) RShiftU64 (Address, 32);
|
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PciIoWrite (
|
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PciIo,
|
||||
EfiPciIoWidthUint32,
|
||||
0x28,
|
||||
1,
|
||||
&Address32
|
||||
);
|
||||
PciIo->Pci.Write (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint32,
|
||||
0x28,
|
||||
1,
|
||||
&Address32
|
||||
);
|
||||
|
||||
Address32 = (UINT32) RShiftU64 ((Address + Node->Length - 1), 32);
|
||||
PciIoWrite (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint32,
|
||||
0x2C,
|
||||
1,
|
||||
&Address32
|
||||
);
|
||||
PciIo->Pci.Write (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint32,
|
||||
0x2C,
|
||||
1,
|
||||
&Address32
|
||||
);
|
||||
|
||||
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
|
||||
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
|
||||
@ -1707,77 +1702,77 @@ ProgramP2C (
|
||||
switch (Node->Bar) {
|
||||
|
||||
case P2C_BAR_0:
|
||||
PciIoWrite (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint32,
|
||||
(Node->PciDev->PciBar[Node->Bar]).Offset,
|
||||
1,
|
||||
&Address
|
||||
);
|
||||
PciIo->Pci.Write (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint32,
|
||||
(Node->PciDev->PciBar[Node->Bar]).Offset,
|
||||
1,
|
||||
&Address
|
||||
);
|
||||
|
||||
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
|
||||
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
|
||||
break;
|
||||
|
||||
case P2C_MEM_1:
|
||||
PciIoWrite (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint32,
|
||||
PCI_CARD_MEMORY_BASE_0,
|
||||
1,
|
||||
&Address
|
||||
);
|
||||
PciIo->Pci.Write (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint32,
|
||||
PCI_CARD_MEMORY_BASE_0,
|
||||
1,
|
||||
&Address
|
||||
);
|
||||
|
||||
TempAddress = Address + Node->Length - 1;
|
||||
PciIoWrite (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint32,
|
||||
PCI_CARD_MEMORY_LIMIT_0,
|
||||
1,
|
||||
&TempAddress
|
||||
);
|
||||
PciIo->Pci.Write (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint32,
|
||||
PCI_CARD_MEMORY_LIMIT_0,
|
||||
1,
|
||||
&TempAddress
|
||||
);
|
||||
|
||||
if (Node->ResType == PciBarTypeMem32) {
|
||||
//
|
||||
// Set non-prefetchable bit
|
||||
//
|
||||
PciIoRead (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint16,
|
||||
PCI_CARD_BRIDGE_CONTROL,
|
||||
1,
|
||||
&BridgeControl
|
||||
);
|
||||
PciIo->Pci.Read (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint16,
|
||||
PCI_CARD_BRIDGE_CONTROL,
|
||||
1,
|
||||
&BridgeControl
|
||||
);
|
||||
|
||||
BridgeControl &= (UINT16) ~PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE;
|
||||
PciIoWrite (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint16,
|
||||
PCI_CARD_BRIDGE_CONTROL,
|
||||
1,
|
||||
&BridgeControl
|
||||
);
|
||||
PciIo->Pci.Write (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint16,
|
||||
PCI_CARD_BRIDGE_CONTROL,
|
||||
1,
|
||||
&BridgeControl
|
||||
);
|
||||
|
||||
} else {
|
||||
//
|
||||
// Set pre-fetchable bit
|
||||
//
|
||||
PciIoRead (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint16,
|
||||
PCI_CARD_BRIDGE_CONTROL,
|
||||
1,
|
||||
&BridgeControl
|
||||
);
|
||||
PciIo->Pci.Read (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint16,
|
||||
PCI_CARD_BRIDGE_CONTROL,
|
||||
1,
|
||||
&BridgeControl
|
||||
);
|
||||
|
||||
BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE;
|
||||
PciIoWrite (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint16,
|
||||
PCI_CARD_BRIDGE_CONTROL,
|
||||
1,
|
||||
&BridgeControl
|
||||
);
|
||||
PciIo->Pci.Write (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint16,
|
||||
PCI_CARD_BRIDGE_CONTROL,
|
||||
1,
|
||||
&BridgeControl
|
||||
);
|
||||
}
|
||||
|
||||
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
|
||||
@ -1787,67 +1782,67 @@ ProgramP2C (
|
||||
break;
|
||||
|
||||
case P2C_MEM_2:
|
||||
PciIoWrite (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint32,
|
||||
PCI_CARD_MEMORY_BASE_1,
|
||||
1,
|
||||
&Address
|
||||
);
|
||||
PciIo->Pci.Write (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint32,
|
||||
PCI_CARD_MEMORY_BASE_1,
|
||||
1,
|
||||
&Address
|
||||
);
|
||||
|
||||
TempAddress = Address + Node->Length - 1;
|
||||
|
||||
PciIoWrite (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint32,
|
||||
PCI_CARD_MEMORY_LIMIT_1,
|
||||
1,
|
||||
&TempAddress
|
||||
);
|
||||
PciIo->Pci.Write (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint32,
|
||||
PCI_CARD_MEMORY_LIMIT_1,
|
||||
1,
|
||||
&TempAddress
|
||||
);
|
||||
|
||||
if (Node->ResType == PciBarTypeMem32) {
|
||||
|
||||
//
|
||||
// Set non-prefetchable bit
|
||||
//
|
||||
PciIoRead (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint16,
|
||||
PCI_CARD_BRIDGE_CONTROL,
|
||||
1,
|
||||
&BridgeControl
|
||||
);
|
||||
PciIo->Pci.Read (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint16,
|
||||
PCI_CARD_BRIDGE_CONTROL,
|
||||
1,
|
||||
&BridgeControl
|
||||
);
|
||||
|
||||
BridgeControl &= (UINT16) ~(PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE);
|
||||
PciIoWrite (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint16,
|
||||
PCI_CARD_BRIDGE_CONTROL,
|
||||
1,
|
||||
&BridgeControl
|
||||
);
|
||||
PciIo->Pci.Write (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint16,
|
||||
PCI_CARD_BRIDGE_CONTROL,
|
||||
1,
|
||||
&BridgeControl
|
||||
);
|
||||
|
||||
} else {
|
||||
|
||||
//
|
||||
// Set pre-fetchable bit
|
||||
//
|
||||
PciIoRead (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint16,
|
||||
PCI_CARD_BRIDGE_CONTROL,
|
||||
1,
|
||||
&BridgeControl
|
||||
);
|
||||
PciIo->Pci.Read (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint16,
|
||||
PCI_CARD_BRIDGE_CONTROL,
|
||||
1,
|
||||
&BridgeControl
|
||||
);
|
||||
|
||||
BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE;
|
||||
PciIoWrite (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint16,
|
||||
PCI_CARD_BRIDGE_CONTROL,
|
||||
1,
|
||||
&BridgeControl
|
||||
);
|
||||
PciIo->Pci.Write (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint16,
|
||||
PCI_CARD_BRIDGE_CONTROL,
|
||||
1,
|
||||
&BridgeControl
|
||||
);
|
||||
}
|
||||
|
||||
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
|
||||
@ -1856,22 +1851,22 @@ ProgramP2C (
|
||||
break;
|
||||
|
||||
case P2C_IO_1:
|
||||
PciIoWrite (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint32,
|
||||
PCI_CARD_IO_BASE_0_LOWER,
|
||||
1,
|
||||
&Address
|
||||
);
|
||||
PciIo->Pci.Write (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint32,
|
||||
PCI_CARD_IO_BASE_0_LOWER,
|
||||
1,
|
||||
&Address
|
||||
);
|
||||
|
||||
TempAddress = Address + Node->Length - 1;
|
||||
PciIoWrite (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint32,
|
||||
PCI_CARD_IO_LIMIT_0_LOWER,
|
||||
1,
|
||||
&TempAddress
|
||||
);
|
||||
PciIo->Pci.Write (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint32,
|
||||
PCI_CARD_IO_LIMIT_0_LOWER,
|
||||
1,
|
||||
&TempAddress
|
||||
);
|
||||
|
||||
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
|
||||
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
|
||||
@ -1880,22 +1875,22 @@ ProgramP2C (
|
||||
break;
|
||||
|
||||
case P2C_IO_2:
|
||||
PciIoWrite (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint32,
|
||||
PCI_CARD_IO_BASE_1_LOWER,
|
||||
1,
|
||||
&Address
|
||||
);
|
||||
PciIo->Pci.Write (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint32,
|
||||
PCI_CARD_IO_BASE_1_LOWER,
|
||||
1,
|
||||
&Address
|
||||
);
|
||||
|
||||
TempAddress = Address + Node->Length - 1;
|
||||
PciIoWrite (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint32,
|
||||
PCI_CARD_IO_LIMIT_1_LOWER,
|
||||
1,
|
||||
&TempAddress
|
||||
);
|
||||
PciIo->Pci.Write (
|
||||
PciIo,
|
||||
EfiPciIoWidthUint32,
|
||||
PCI_CARD_IO_LIMIT_1_LOWER,
|
||||
1,
|
||||
&TempAddress
|
||||
);
|
||||
|
||||
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
|
||||
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
|
||||
|
||||
Reference in New Issue
Block a user