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Retired PciIncompatibleDeviceSupportLib from IntelFrameworkModulePkg.

Browse Source 
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@8773 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
vanjeff
2009-07-07 04:00:44 +00:00
parent 7bfed576b0
commit 9eb130ff8c
21 changed files with 456 additions and 2289 deletions
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1
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBus.h
View File

@ -41,7 +41,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#include <Library/UefiBootServicesTableLib.h> #include <Library/UefiBootServicesTableLib.h>
#include <Library/DevicePathLib.h> #include <Library/DevicePathLib.h>
#include <Library/PcdLib.h> #include <Library/PcdLib.h>
#include <Library/PciIncompatibleDeviceSupportLib.h>
#include <Library/PeCoffLib.h> #include <Library/PeCoffLib.h>
#include <IndustryStandard/Pci.h> #include <IndustryStandard/Pci.h>

4
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
View File

@ -73,7 +73,6 @@
IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
[LibraryClasses] [LibraryClasses]
PciIncompatibleDeviceSupportLib
PcdLib PcdLib
DevicePathLib DevicePathLib
UefiBootServicesTableLib UefiBootServicesTableLib
@ -103,9 +102,6 @@
[FeaturePcd.common] [FeaturePcd.common]
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport
[Pcd.common]
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPciIncompatibleDeviceSupportMask
# [Event] # [Event]
# ## # ##
# # Notify event set by CreateEventForHpc () for PCI Hot Plug controller. # # Notify event set by CreateEventForHpc () for PCI Hot Plug controller.

10
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.c
View File

@ -43,7 +43,7 @@ PciOperateRegister (
PciIo = &PciIoDevice->PciIo; PciIo = &PciIoDevice->PciIo;
if (Operation != EFI_SET_REGISTER) { if (Operation != EFI_SET_REGISTER) {
Status = PciIoRead ( Status = PciIo->Pci.Read (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
Offset, Offset,
@ -65,7 +65,7 @@ PciOperateRegister (
OldCommand = Command; OldCommand = Command;
} }
return PciIoWrite ( return PciIo->Pci.Write (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
Offset, Offset,
@ -134,7 +134,7 @@ LocateCapabilityRegBlock (
CapabilityPtr = 0; CapabilityPtr = 0;
if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) { if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
PciIoRead ( PciIoDevice->PciIo.Pci.Read (
&PciIoDevice->PciIo, &PciIoDevice->PciIo,
EfiPciIoWidthUint8, EfiPciIoWidthUint8,
EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR, EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR,
@ -143,7 +143,7 @@ LocateCapabilityRegBlock (
); );
} else { } else {
PciIoRead ( PciIoDevice->PciIo.Pci.Read (
&PciIoDevice->PciIo, &PciIoDevice->PciIo,
EfiPciIoWidthUint8, EfiPciIoWidthUint8,
PCI_CAPBILITY_POINTER_OFFSET, PCI_CAPBILITY_POINTER_OFFSET,
@ -154,7 +154,7 @@ LocateCapabilityRegBlock (
} }
while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) { while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {
PciIoRead ( PciIoDevice->PciIo.Pci.Read (
&PciIoDevice->PciIo, &PciIoDevice->PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
CapabilityPtr, CapabilityPtr,

2
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
View File

@ -250,7 +250,7 @@ RegisterPciDevice (
// //
PciIo = &(PciIoDevice->PciIo); PciIo = &(PciIoDevice->PciIo);
Data8 = PCI_INT_LINE_UNKNOWN; Data8 = PCI_INT_LINE_UNKNOWN;
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &Data8); PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &Data8);
// //
// Process OpRom // Process OpRom

25
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c
View File

@ -341,9 +341,8 @@ PciAssignBusNumber (
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18); Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);
Status = PciRootBridgeIoWrite ( Status = PciRootBridgeIo->Pci.Write (
PciRootBridgeIo, PciRootBridgeIo,
&Pci,
EfiPciWidthUint16, EfiPciWidthUint16,
Address, Address,
1, 1,
@ -354,9 +353,8 @@ PciAssignBusNumber (
// Initialize SubBusNumber to SecondBus // Initialize SubBusNumber to SecondBus
// //
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A); Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);
Status = PciRootBridgeIoWrite ( Status = PciRootBridgeIo->Pci.Write (
PciRootBridgeIo, PciRootBridgeIo,
&Pci,
EfiPciWidthUint8, EfiPciWidthUint8,
Address, Address,
1, 1,
@ -368,9 +366,8 @@ PciAssignBusNumber (
if (IS_PCI_BRIDGE (&Pci)) { if (IS_PCI_BRIDGE (&Pci)) {
Register8 = 0xFF; Register8 = 0xFF;
Status = PciRootBridgeIoWrite ( Status = PciRootBridgeIo->Pci.Write (
PciRootBridgeIo, PciRootBridgeIo,
&Pci,
EfiPciWidthUint8, EfiPciWidthUint8,
Address, Address,
1, 1,
@ -393,9 +390,8 @@ PciAssignBusNumber (
// //
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A); Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);
Status = PciRootBridgeIoWrite ( Status = PciRootBridgeIo->Pci.Write (
PciRootBridgeIo, PciRootBridgeIo,
&Pci,
EfiPciWidthUint8, EfiPciWidthUint8,
Address, Address,
1, 1,
@ -1083,16 +1079,11 @@ ConstructAcpiResourceRequestor (
// If there is at least one type of resource request, // If there is at least one type of resource request,
// allocate a acpi resource node // allocate a acpi resource node
// //
Configuration = AllocatePool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)); Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
if (Configuration == NULL) { if (Configuration == NULL) {
return EFI_OUT_OF_RESOURCES; return EFI_OUT_OF_RESOURCES;
} }
ZeroMem (
Configuration,
sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)
);
Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
// //
@ -1221,13 +1212,11 @@ ConstructAcpiResourceRequestor (
// //
// If there is no resource request // If there is no resource request
// //
Configuration = AllocatePool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)); Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
if (Configuration == NULL) { if (Configuration == NULL) {
return EFI_OUT_OF_RESOURCES; return EFI_OUT_OF_RESOURCES;
} }
ZeroMem (Configuration, sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) (Configuration); Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) (Configuration);
Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR; Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
@ -1356,7 +1345,7 @@ PciBridgeEnumerator (
SubBusNumber = 0; SubBusNumber = 0;
StartBusNumber = 0; StartBusNumber = 0;
PciIo = &(BridgeDev->PciIo); PciIo = &(BridgeDev->PciIo);
Status = PciIoRead (PciIo, EfiPciIoWidthUint8, 0x19, 1, &StartBusNumber); Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x19, 1, &StartBusNumber);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;

105
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
View File

@ -47,9 +47,8 @@ PciDevicePresent (
// //
// Read the Vendor ID register // Read the Vendor ID register
// //
Status = PciRootBridgeIoRead ( Status = PciRootBridgeIo->Pci.Read (
PciRootBridgeIo, PciRootBridgeIo,
NULL,
EfiPciWidthUint32, EfiPciWidthUint32,
Address, Address,
1, 1,
@ -60,9 +59,8 @@ PciDevicePresent (
// //
// Read the entire config header for the device // Read the entire config header for the device
// //
Status = PciRootBridgeIoRead ( Status = PciRootBridgeIo->Pci.Read (
PciRootBridgeIo, PciRootBridgeIo,
NULL,
EfiPciWidthUint32, EfiPciWidthUint32,
Address, Address,
sizeof (PCI_TYPE00) / sizeof (UINT32), sizeof (PCI_TYPE00) / sizeof (UINT32),
@ -149,7 +147,7 @@ PciPciDeviceInfoCollector (
// //
PciIo = &(PciIoDevice->PciIo); PciIo = &(PciIoDevice->PciIo);
Status = PciIoRead (PciIo, EfiPciIoWidthUint8, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, 1, &SecBus); Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, 1, &SecBus);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
@ -446,10 +444,10 @@ GatherPpbInfo (
// //
// Test whether it support 32 decode or not // Test whether it support 32 decode or not
// //
PciIoRead (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp); PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne); PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);
PciIoRead (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value); PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value);
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp); PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);
if (Value != 0) { if (Value != 0) {
if ((Value & 0x01) != 0) { if ((Value & 0x01) != 0) {
@ -629,20 +627,20 @@ BarExisted (
// //
// Preserve the original value // Preserve the original value
// //
PciIoRead (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue); PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);
// //
// Raise TPL to high level to disable timer interrupt while the BAR is probed // Raise TPL to high level to disable timer interrupt while the BAR is probed
// //
OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL); OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
PciIoWrite (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &gAllOne); PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &gAllOne);
PciIoRead (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &Value); PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &Value);
// //
// Write back the original value // Write back the original value
// //
PciIoWrite (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue); PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);
// //
// Restore TPL to its original level // Restore TPL to its original level
@ -860,7 +858,7 @@ GetFastBackToBackSupport (
// Read the status register // Read the status register
// //
PciIo = &PciIoDevice->PciIo; PciIo = &PciIoDevice->PciIo;
Status = PciIoRead (PciIo, EfiPciIoWidthUint16, StatusIndex, 1, &StatusRegister); Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, StatusIndex, 1, &StatusRegister);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
@ -1049,23 +1047,22 @@ DetermineDeviceAttribute (
/** /**
This routine is used to update the bar information for those incompatible PCI device. This routine is used to update the bar information for those incompatible PCI device.
@param PciIoDevice Pci device instance. @param PciIoDevice Input Pci device instance. Output Pci device instance with updated
Bar information.
@retval EFI_SUCCESS Successfully updated bar information. @retval EFI_SUCCESS Successfully updated bar information.
@retval EFI_UNSUPPORTED Given PCI device doesn't belong to incompatible PCI device list. @retval EFI_UNSUPPORTED Given PCI device doesn't belong to incompatible PCI device list.
@retval other Failed to check incompatibility device.
**/ **/
EFI_STATUS EFI_STATUS
UpdatePciInfo ( UpdatePciInfo (
IN PCI_IO_DEVICE *PciIoDevice IN OUT PCI_IO_DEVICE *PciIoDevice
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINTN BarIndex; UINTN BarIndex;
UINTN BarEndIndex; UINTN BarEndIndex;
BOOLEAN SetFlag; BOOLEAN SetFlag;
EFI_PCI_DEVICE_INFO PciDeviceInfo;
VOID *Configuration; VOID *Configuration;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr; EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
@ -1100,22 +1097,6 @@ UpdatePciInfo (
} }
if (EFI_ERROR (Status)) {
//
// Check whether the device belongs to incompatible devices from library or not
// If it is , then get its special requirement in the ACPI table
//
if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_ACPI_RESOURCE_SUPPORT) {
PciDeviceInfo.VendorID = PciIoDevice->Pci.Hdr.VendorId;
PciDeviceInfo.DeviceID = PciIoDevice->Pci.Hdr.DeviceId;
PciDeviceInfo.RevisionID = PciIoDevice->Pci.Hdr.RevisionID;
PciDeviceInfo.SubsystemVendorID = PciIoDevice->Pci.Device.SubsystemVendorID;
PciDeviceInfo.SubsystemID = PciIoDevice->Pci.Device.SubsystemID;
Status = PciResourceUpdateCheck (&PciDeviceInfo, &Configuration);
}
}
if (EFI_ERROR (Status) || Configuration == NULL ) { if (EFI_ERROR (Status) || Configuration == NULL ) {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
@ -1193,9 +1174,7 @@ UpdatePciInfo (
Ptr++; Ptr++;
} }
if (Configuration != NULL) {
FreePool (Configuration); FreePool (Configuration);
}
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@ -1203,13 +1182,13 @@ UpdatePciInfo (
/** /**
This routine will update the alignment with the new alignment. This routine will update the alignment with the new alignment.
@param Alignment Old alignment. @param Alignment Input Old alignment. Output updated alignment.
@param NewAlignment New alignment. @param NewAlignment New alignment.
**/ **/
VOID VOID
SetNewAlign ( SetNewAlign (
IN UINT64 *Alignment, IN OUT UINT64 *Alignment,
IN UINT64 NewAlignment IN UINT64 NewAlignment
) )
{ {
@ -1482,7 +1461,7 @@ InitializePciDevice (
// has not been alloacted // has not been alloacted
// //
for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) { for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) {
PciIoWrite (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllOne); PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllOne);
} }
} }
@ -1506,28 +1485,28 @@ InitializePpb (
// Io32, pMem32, pMem64 to quiescent state // Io32, pMem32, pMem64 to quiescent state
// Resource base all ones, Resource limit all zeros // Resource base all ones, Resource limit all zeros
// //
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne); PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1D, 1, &gAllZero); PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1D, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x20, 1, &gAllOne); PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x20, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x22, 1, &gAllZero); PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x22, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x24, 1, &gAllOne); PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x24, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x26, 1, &gAllZero); PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x26, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllOne); PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x2C, 1, &gAllZero); PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x2C, 1, &gAllZero);
// //
// don't support use io32 as for now // Don't support use io32 as for now
// //
PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x30, 1, &gAllOne); PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x30, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x32, 1, &gAllZero); PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x32, 1, &gAllZero);
// //
// Force Interrupt line to zero for cards that come up randomly // Force Interrupt line to zero for cards that come up randomly
// //
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero); PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);
} }
/** /**
@ -1550,22 +1529,22 @@ InitializeP2C (
// Io32, pMem32, pMem64 to quiescent state( // Io32, pMem32, pMem64 to quiescent state(
// Resource base all ones, Resource limit all zeros // Resource base all ones, Resource limit all zeros
// //
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x1c, 1, &gAllOne); PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x1c, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x20, 1, &gAllZero); PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x20, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x24, 1, &gAllOne); PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x24, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllZero); PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x2c, 1, &gAllOne); PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x2c, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x30, 1, &gAllZero); PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x30, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x34, 1, &gAllOne); PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x34, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x38, 1, &gAllZero); PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x38, 1, &gAllZero);
// //
// Force Interrupt line to zero for cards that come up randomly // Force Interrupt line to zero for cards that come up randomly
// //
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero); PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);
} }
/** /**
@ -2006,9 +1985,8 @@ ResetAllPpbBusNumber (
Register = 0; Register = 0;
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18); Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);
Status = PciRootBridgeIoRead ( Status = PciRootBridgeIo->Pci.Read (
PciRootBridgeIo, PciRootBridgeIo,
&Pci,
EfiPciWidthUint32, EfiPciWidthUint32,
Address, Address,
1, 1,
@ -2024,9 +2002,8 @@ ResetAllPpbBusNumber (
// Reset register 18h, 19h, 1Ah on PCI Bridge // Reset register 18h, 19h, 1Ah on PCI Bridge
// //
Register &= 0xFF000000; Register &= 0xFF000000;
Status = PciRootBridgeIoWrite ( Status = PciRootBridgeIo->Pci.Write (
PciRootBridgeIo, PciRootBridgeIo,
&Pci,
EfiPciWidthUint32, EfiPciWidthUint32,
Address, Address,
1, 1,

10
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h
View File

@ -246,28 +246,28 @@ DetermineDeviceAttribute (
/** /**
This routine is used to update the bar information for those incompatible PCI device. This routine is used to update the bar information for those incompatible PCI device.
@param PciIoDevice Pci device instance. @param PciIoDevice Input Pci device instance. Output Pci device instance with updated
Bar information.
@retval EFI_SUCCESS Successfully updated bar information. @retval EFI_SUCCESS Successfully updated bar information.
@retval EFI_UNSUPPORTED Given PCI device doesn't belong to incompatible PCI device list. @retval EFI_UNSUPPORTED Given PCI device doesn't belong to incompatible PCI device list.
@retval other Failed to check incompatibility device.
**/ **/
EFI_STATUS EFI_STATUS
UpdatePciInfo ( UpdatePciInfo (
IN PCI_IO_DEVICE *PciIoDevice IN OUT PCI_IO_DEVICE *PciIoDevice
); );
/** /**
This routine will update the alignment with the new alignment. This routine will update the alignment with the new alignment.
@param Alignment Old alignment. @param Alignment Input Old alignment. Output updated alignment.
@param NewAlignment New alignment. @param NewAlignment New alignment.
**/ **/
VOID VOID
SetNewAlign ( SetNewAlign (
IN UINT64 *Alignment, IN OUT UINT64 *Alignment,
IN UINT64 NewAlignment IN UINT64 NewAlignment
); );

7
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciIo.c
View File

@ -1628,16 +1628,11 @@ PciIoGetBarAttributes (
NumConfig = 1; NumConfig = 1;
} }
Configuration = AllocatePool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)); Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
if (Configuration == NULL) { if (Configuration == NULL) {
return EFI_OUT_OF_RESOURCES; return EFI_OUT_OF_RESOURCES;
} }
ZeroMem (
Configuration,
sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)
);
Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
if (NumConfig == 1) { if (NumConfig == 1) {

908
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.c
View File

@ -37,7 +37,7 @@ GetBackPcCardBar (
// //
if (!gFullEnumeration) { if (!gFullEnumeration) {
Address = 0; Address = 0;
PciIoRead ( PciIoDevice->PciIo.Pci.Read (
&(PciIoDevice->PciIo), &(PciIoDevice->PciIo),
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
PCI_CARD_MEMORY_BASE_0, PCI_CARD_MEMORY_BASE_0,
@ -50,7 +50,7 @@ GetBackPcCardBar (
(PciIoDevice->PciBar)[P2C_MEM_1].BarType = PciBarTypeMem32; (PciIoDevice->PciBar)[P2C_MEM_1].BarType = PciBarTypeMem32;
Address = 0; Address = 0;
PciIoRead ( PciIoDevice->PciIo.Pci.Read (
&(PciIoDevice->PciIo), &(PciIoDevice->PciIo),
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
PCI_CARD_MEMORY_BASE_1, PCI_CARD_MEMORY_BASE_1,
@ -62,7 +62,7 @@ GetBackPcCardBar (
(PciIoDevice->PciBar)[P2C_MEM_2].BarType = PciBarTypePMem32; (PciIoDevice->PciBar)[P2C_MEM_2].BarType = PciBarTypePMem32;
Address = 0; Address = 0;
PciIoRead ( PciIoDevice->PciIo.Pci.Read (
&(PciIoDevice->PciIo), &(PciIoDevice->PciIo),
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
PCI_CARD_IO_BASE_0_LOWER, PCI_CARD_IO_BASE_0_LOWER,
@ -74,7 +74,7 @@ GetBackPcCardBar (
(PciIoDevice->PciBar)[P2C_IO_1].BarType = PciBarTypeIo16; (PciIoDevice->PciBar)[P2C_IO_1].BarType = PciBarTypeIo16;
Address = 0; Address = 0;
PciIoRead ( PciIoDevice->PciIo.Pci.Read (
&(PciIoDevice->PciIo), &(PciIoDevice->PciIo),
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
PCI_CARD_IO_BASE_1_LOWER, PCI_CARD_IO_BASE_1_LOWER,
@ -891,9 +891,8 @@ PciScanBus (
Register = (UINT16) ((SecondBus << 8) | (UINT16) StartBusNumber); Register = (UINT16) ((SecondBus << 8) | (UINT16) StartBusNumber);
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET); Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET);
Status = PciRootBridgeIoWrite ( Status = PciRootBridgeIo->Pci.Write (
PciRootBridgeIo, PciRootBridgeIo,
&Pci,
EfiPciWidthUint16, EfiPciWidthUint16,
Address, Address,
1, 1,
@ -912,9 +911,8 @@ PciScanBus (
// //
Register = 0xFF; Register = 0xFF;
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET); Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);
Status = PciRootBridgeIoWrite ( Status = PciRootBridgeIo->Pci.Write (
PciRootBridgeIo, PciRootBridgeIo,
&Pci,
EfiPciWidthUint8, EfiPciWidthUint8,
Address, Address,
1, 1,
@ -962,9 +960,8 @@ PciScanBus (
// //
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET); Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);
Status = PciRootBridgeIoWrite ( Status = PciRootBridgeIo->Pci.Write (
PciRootBridgeIo, PciRootBridgeIo,
&Pci,
EfiPciWidthUint8, EfiPciWidthUint8,
Address, Address,
1, 1,
@ -1117,7 +1114,7 @@ PciHostBridgeP2CProcess (
**/ **/
EFI_STATUS EFI_STATUS
PciHostBridgeEnumerator ( PciHostBridgeEnumerator (
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
) )
{ {
EFI_HANDLE RootBridgeHandle; EFI_HANDLE RootBridgeHandle;
@ -1331,892 +1328,3 @@ PciHostBridgeEnumerator (
return EFI_SUCCESS; return EFI_SUCCESS;
} }
/**
Read PCI device configuration register by specified address.
This function check the incompatiblilites on PCI device. Return the register
value.
@param PciRootBridgeIo PCI root bridge io protocol instance.
@param PciIo PCI IO protocol instance.
@param PciDeviceInfo PCI device information.
@param Width Signifies the width of the memory operations.
@param Offset The offset within the PCI configuration space for the PCI controller.
@param Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_UNSUPPORTED Width is invalid for this PCI root bridge.
@retval other Some error occurred when reading PCI device configuration space
or checking incompatibility.
**/
EFI_STATUS
ReadConfigData (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL
IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,
IN UINT64 Width,
IN UINT64 Offset,
IN OUT VOID *Buffer
)
{
EFI_STATUS Status;
UINT64 AccessWidth;
EFI_PCI_REGISTER_ACCESS_DATA *PciRegisterAccessData;
UINT64 AccessAddress;
UINTN Stride;
UINT64 TempBuffer;
UINT8 *Pointer;
ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));
ASSERT (Buffer != NULL);
if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT) != 0) {
//
// Check access compatibility at first time
//
Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_READ, Offset & 0xff, Width, &PciRegisterAccessData);
if (Status == EFI_SUCCESS) {
//
// There exists incompatibility on this operation
//
AccessWidth = Width;
if (PciRegisterAccessData->Width != VALUE_NOCARE) {
AccessWidth = PciRegisterAccessData->Width;
}
AccessAddress = Offset & ~((1 << AccessWidth) - 1);
TempBuffer = 0;
Stride = 0;
Pointer = (UINT8 *) &TempBuffer;
while (TRUE) {
if (PciRootBridgeIo != NULL) {
Status = PciRootBridgeIo->Pci.Read (
PciRootBridgeIo,
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) AccessWidth,
AccessAddress,
1,
Pointer
);
} else if (PciIo != NULL) {
Status = PciIo->Pci.Read (
PciIo,
(EFI_PCI_IO_PROTOCOL_WIDTH) AccessWidth,
(UINT32) AccessAddress,
1,
Pointer
);
}
if (Status != EFI_SUCCESS) {
return Status;
}
Stride = (UINTN)1 << AccessWidth;
AccessAddress += Stride;
if (AccessAddress >= (Offset + LShiftU64 (1ULL, (UINTN)Width))) {
//
// If all datas have been read, exit
//
break;
}
Pointer += Stride;
if ((AccessAddress & 0xff) < PciRegisterAccessData->EndOffset) {
//
// If current offset doesn't reach the end
//
continue;
}
//
// Continue checking access incompatibility
//
Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_READ, AccessAddress & 0xff, AccessWidth, &PciRegisterAccessData);
if (Status == EFI_SUCCESS) {
if (PciRegisterAccessData->Width != VALUE_NOCARE) {
AccessWidth = PciRegisterAccessData->Width;
}
}
}
switch (Width) {
case EfiPciWidthUint8:
* (UINT8 *) Buffer = (UINT8) TempBuffer;
break;
case EfiPciWidthUint16:
* (UINT16 *) Buffer = (UINT16) TempBuffer;
break;
case EfiPciWidthUint32:
* (UINT32 *) Buffer = (UINT32) TempBuffer;
break;
default:
return EFI_UNSUPPORTED;
}
return Status;
}
}
//
// AccessWidth incompatible check not supportted
// or, there doesn't exist incompatibility on this operation
//
if (PciRootBridgeIo != NULL) {
Status = PciRootBridgeIo->Pci.Read (
PciRootBridgeIo,
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
Offset,
1,
Buffer
);
} else {
Status = PciIo->Pci.Read (
PciIo,
(EFI_PCI_IO_PROTOCOL_WIDTH) Width,
(UINT32) Offset,
1,
Buffer
);
}
return Status;
}
/**
Update register value by checking PCI device incompatibility.
This function check register value incompatibilites on PCI device. Return the register
value.
@param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.
@param AccessType Access type, READ or WRITE.
@param Width Signifies the width of the memory operations.
@param Offset The offset within the PCI configuration space.
@param Buffer Store the register data.
@retval EFI_SUCCESS The data has been updated.
@retval EFI_UNSUPPORTED Width is invalid for this PCI root bridge.
@retval other Some error occurred when checking incompatibility.
**/
EFI_STATUS
UpdateConfigData (
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,
IN UINT64 AccessType,
IN UINT64 Width,
IN UINT64 Offset,
IN OUT VOID *Buffer
)
{
EFI_STATUS Status;
EFI_PCI_REGISTER_VALUE_DATA *PciRegisterData;
UINT32 AndValue;
UINT32 OrValue;
UINT32 TempValue;
ASSERT (Buffer != NULL);
//
// Check register value incompatibility
//
Status = PciRegisterUpdateCheck (PciDeviceInfo, AccessType, Offset & 0xff, &PciRegisterData);
if (Status == EFI_SUCCESS) {
AndValue = ((UINT32) PciRegisterData->AndValue) >> (((UINT8) Offset & 0x3) * 8);
OrValue = ((UINT32) PciRegisterData->OrValue) >> (((UINT8) Offset & 0x3) * 8);
TempValue = * (UINT32 *) Buffer;
if (PciRegisterData->AndValue != VALUE_NOCARE) {
TempValue &= AndValue;
}
if (PciRegisterData->OrValue != VALUE_NOCARE) {
TempValue |= OrValue;
}
switch (Width) {
case EfiPciWidthUint8:
*(UINT8 *)Buffer = (UINT8) TempValue;
break;
case EfiPciWidthUint16:
*(UINT16 *)Buffer = (UINT16) TempValue;
break;
case EfiPciWidthUint32:
*(UINT32 *)Buffer = TempValue;
break;
default:
return EFI_UNSUPPORTED;
}
}
return Status;
}
/**
Write PCI device configuration register by specified address.
This function check the incompatiblilites on PCI device, and write date
into register.
@param PciRootBridgeIo PCI root bridge io instance.
@param PciIo PCI IO protocol instance.
@param PciDeviceInfo PCI device information.
@param Width Signifies the width of the memory operations.
@param Offset The offset within the PCI configuration space for the PCI controller.
@param Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval other Some error occurred when writing PCI device information
or checking incompatibility.
**/
EFI_STATUS
WriteConfigData (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL
IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,
IN UINT64 Width,
IN UINT64 Offset,
IN VOID *Buffer
)
{
EFI_STATUS Status;
UINT64 AccessWidth;
EFI_PCI_REGISTER_ACCESS_DATA *PciRegisterAccessData;
UINT64 AccessAddress;
UINTN Stride;
UINT8 *Pointer;
UINT64 Data;
UINTN Shift;
ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));
ASSERT (Buffer != NULL);
if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT) != 0) {
//
// Check access compatibility at first time
//
Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_WRITE, Offset & 0xff, Width, &PciRegisterAccessData);
if (Status == EFI_SUCCESS) {
//
// There exists incompatibility on this operation
//
AccessWidth = Width;
if (PciRegisterAccessData->Width != VALUE_NOCARE) {
AccessWidth = PciRegisterAccessData->Width;
}
AccessAddress = Offset & ~((1 << AccessWidth) - 1);
Stride = 0;
Pointer = (UINT8 *) &Buffer;
Data = * (UINT64 *) Buffer;
while (TRUE) {
if (AccessWidth > Width) {
//
// If actual access width is larger than orignal one, additional data need to be read back firstly
//
Status = ReadConfigData (PciRootBridgeIo, PciIo, PciDeviceInfo, AccessWidth, AccessAddress, &Data);
if (Status != EFI_SUCCESS) {
return Status;
}
//
// Check data read incompatibility
//
UpdateConfigData (PciDeviceInfo, PCI_REGISTER_READ, AccessWidth, AccessAddress & 0xff, &Data);
Shift = (UINTN)(Offset - AccessAddress) * 8;
switch (Width) {
case EfiPciWidthUint8:
Data = (* (UINT8 *) Buffer) << Shift | (Data & ~(0xff << Shift));
break;
case EfiPciWidthUint16:
Data = (* (UINT16 *) Buffer) << Shift | (Data & ~(0xffff << Shift));
break;
}
//
// Check data write incompatibility
//
UpdateConfigData (PciDeviceInfo, PCI_REGISTER_WRITE, AccessWidth, MultU64x32 (AccessAddress, 0xff), &Data);
}
if (PciRootBridgeIo != NULL) {
Status = PciRootBridgeIo->Pci.Write (
PciRootBridgeIo,
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) AccessWidth,
AccessAddress,
1,
&Data
);
} else {
Status = PciIo->Pci.Write (
PciIo,
(EFI_PCI_IO_PROTOCOL_WIDTH) AccessWidth,
(UINT32) AccessAddress,
1,
&Data
);
}
if (Status != EFI_SUCCESS) {
return Status;
}
Data = RShiftU64 (Data, ((1 << AccessWidth) * 8));
Stride = (UINTN)1 << AccessWidth;
AccessAddress += Stride;
if (AccessAddress >= (Offset + LShiftU64 (1ULL, (UINTN)Width))) {
//
// If all datas have been written, exit
//
break;
}
Pointer += Stride;
if ((AccessAddress & 0xff) < PciRegisterAccessData->EndOffset) {
//
// If current offset doesn't reach the end
//
continue;
}
//
// Continue checking access incompatibility
//
Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_WRITE, AccessAddress & 0xff, AccessWidth, &PciRegisterAccessData);
if (Status == EFI_SUCCESS) {
if (PciRegisterAccessData->Width != VALUE_NOCARE) {
AccessWidth = PciRegisterAccessData->Width;
}
}
};
return Status;
}
}
//
// AccessWidth incompatible check not supportted
// or, there doesn't exist incompatibility on this operation
//
if (PciRootBridgeIo != NULL) {
Status = PciRootBridgeIo->Pci.Write (
PciRootBridgeIo,
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
Offset,
1,
Buffer
);
} else {
Status = PciIo->Pci.Write (
PciIo,
(EFI_PCI_IO_PROTOCOL_WIDTH) Width,
(UINT32) Offset,
1,
Buffer
);
}
return Status;
}
/**
Abstract PCI device device information.
@param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param PciIo A pointer to EFI_PCI_PROTOCOL.
@param Pci PCI device configuration space.
@param Offset The offset within the PCI configuration space for the PCI controller.
@param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.
@retval EFI_SUCCESS Pci device device information has been abstracted.
@retval EFI_NOT_FOUND Cannot found the specified PCI device.
@retval other Some error occurred when reading PCI device information.
**/
EFI_STATUS
GetPciDeviceDeviceInfo (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL
IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL
IN PCI_TYPE00 *Pci, OPTIONAL
IN UINT64 Offset, OPTIONAL
OUT EFI_PCI_DEVICE_INFO *PciDeviceInfo
)
{
EFI_STATUS Status;
UINT64 PciAddress;
UINT32 PciConfigData;
PCI_IO_DEVICE *PciIoDevice;
ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));
ASSERT (PciDeviceInfo != NULL);
if (PciIo != NULL) {
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo);
//
// Get pointer to PCI_TYPE00 from PciIoDevice
//
Pci = &PciIoDevice->Pci;
}
if (Pci == NULL) {
//
// While PCI_TYPE00 hasn't been gotten, read PCI device device information directly
//
PciAddress = Offset & 0xffffffffffffff00ULL;
Status = PciRootBridgeIo->Pci.Read (
PciRootBridgeIo,
EfiPciWidthUint32,
PciAddress,
1,
&PciConfigData
);
if (EFI_ERROR (Status)) {
return Status;
}
if ((PciConfigData & 0xffff) == 0xffff) {
return EFI_NOT_FOUND;
}
PciDeviceInfo->VendorID = PciConfigData & 0xffff;
PciDeviceInfo->DeviceID = PciConfigData >> 16;
Status = PciRootBridgeIo->Pci.Read (
PciRootBridgeIo,
EfiPciWidthUint32,
PciAddress + 8,
1,
&PciConfigData
);
if (EFI_ERROR (Status)) {
return Status;
}
PciDeviceInfo->RevisionID = PciConfigData & 0xf;
Status = PciRootBridgeIo->Pci.Read (
PciRootBridgeIo,
EfiPciWidthUint32,
PciAddress + 0x2c,
1,
&PciConfigData
);
if (EFI_ERROR (Status)) {
return Status;
}
PciDeviceInfo->SubsystemVendorID = PciConfigData & 0xffff;
PciDeviceInfo->SubsystemID = PciConfigData >> 16;
} else {
PciDeviceInfo->VendorID = Pci->Hdr.VendorId;
PciDeviceInfo->DeviceID = Pci->Hdr.DeviceId;
PciDeviceInfo->RevisionID = Pci->Hdr.RevisionID;
PciDeviceInfo->SubsystemVendorID = Pci->Device.SubsystemVendorID;
PciDeviceInfo->SubsystemID = Pci->Device.SubsystemID;
}
return EFI_SUCCESS;
}
/**
Read PCI configuration space with incompatibility check.
@param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param PciIo A pointer to the EFI_PCI_IO_PROTOCOL.
@param Pci A pointer to PCI_TYPE00.
@param Width Signifies the width of the memory operations.
@param Offset The offset within the PCI configuration space for the PCI controller.
@param Count The number of unit to be read.
@param Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_UNSUPPORTED Buffer is NULL.
@retval other Some error occurred when reading PCI configuration space.
**/
EFI_STATUS
PciIncompatibilityCheckRead (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL
IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL
IN PCI_TYPE00 *Pci, OPTIONAL
IN UINTN Width,
IN UINT64 Offset,
IN UINTN Count,
IN OUT VOID *Buffer
)
{
EFI_STATUS Status;
EFI_PCI_DEVICE_INFO PciDeviceInfo;
UINT32 Stride;
ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));
if (Buffer == NULL) {
return EFI_UNSUPPORTED;
}
//
// get PCI device device information
//
Status = GetPciDeviceDeviceInfo (PciRootBridgeIo, PciIo, Pci, Offset, &PciDeviceInfo);
if (Status != EFI_SUCCESS) {
return Status;
}
Stride = 1 << Width;
for (; Count > 0; Count--, Offset += Stride, Buffer = (UINT8 *)Buffer + Stride) {
//
// read configuration register
//
Status = ReadConfigData (PciRootBridgeIo, PciIo, &PciDeviceInfo, (UINT64) Width, Offset, Buffer);
if (Status != EFI_SUCCESS) {
return Status;
}
//
// update the data read from configuration register
//
if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT) != 0) {
UpdateConfigData (&PciDeviceInfo, PCI_REGISTER_READ, Width, Offset & 0xff, Buffer);
}
}
return EFI_SUCCESS;
}
/**
Write PCI configuration space with incompatibility check.
@param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param PciIo A pointer to the EFI_PCI_IO_PROTOCOL.
@param Pci A pointer to PCI_TYPE00.
@param Width Signifies the width of the memory operations.
@param Offset The offset within the PCI configuration space for the PCI controller.
@param Count The number of unit to be write.
@param Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
valid for the PCI configuration header of the PCI controller.
Buffer is NULL.
@retval other Some error occurred when writing PCI configuration space.
**/
EFI_STATUS
PciIncompatibilityCheckWrite (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL
IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL
IN PCI_TYPE00 *Pci, OPTIONAL
IN UINTN Width,
IN UINT64 Offset,
IN UINTN Count,
IN OUT VOID *Buffer
)
{
EFI_STATUS Status;
EFI_PCI_DEVICE_INFO PciDeviceInfo;
UINT32 Stride;
UINT64 Data;
ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));
if (Buffer == NULL) {
return EFI_UNSUPPORTED;
}
//
// Get PCI device device information
//
Status = GetPciDeviceDeviceInfo (PciRootBridgeIo, PciIo, Pci, Offset, &PciDeviceInfo);
if (Status != EFI_SUCCESS) {
return Status;
}
Stride = 1 << Width;
for (; Count > 0; Count--, Offset += Stride, Buffer = (UINT8 *) Buffer + Stride) {
Data = 0;
switch (Width) {
case EfiPciWidthUint8:
Data = * (UINT8 *) Buffer;
break;
case EfiPciWidthUint16:
Data = * (UINT16 *) Buffer;
break;
case EfiPciWidthUint32:
Data = * (UINT32 *) Buffer;
break;
default:
return EFI_UNSUPPORTED;
}
//
// Update the data writen into configuration register
//
if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT) != 0) {
UpdateConfigData (&PciDeviceInfo, PCI_REGISTER_WRITE, Width, Offset & 0xff, &Data);
}
//
// Write configuration register
//
Status = WriteConfigData (PciRootBridgeIo, PciIo, &PciDeviceInfo, Width, Offset, &Data);
if (Status != EFI_SUCCESS) {
return Status;
}
}
return EFI_SUCCESS;
}
/**
Read PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param Pci A pointer to PCI_TYPE00.
@param Width Signifies the width of the memory operations.
@param Offset The offset within the PCI configuration space for the PCI controller.
@param Count The number of unit to be read.
@param Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
**/
EFI_STATUS
PciRootBridgeIoRead (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
IN PCI_TYPE00 *Pci, OPTIONAL
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Offset,
IN UINTN Count,
IN OUT VOID *Buffer
)
{
EFI_STATUS Status;
if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_READ_SUPPORT) != 0) {
//
// If PCI incompatibility check enabled
//
Status = PciIncompatibilityCheckRead (
PciRootBridgeIo,
NULL,
Pci,
(UINTN) Width,
Offset,
Count,
Buffer
);
if (Status == EFI_UNSUPPORTED) {
return EFI_INVALID_PARAMETER;
} else {
return Status;
}
} else {
return PciRootBridgeIo->Pci.Read (
PciRootBridgeIo,
Width,
Offset,
Count,
Buffer
);
}
}
/**
Write PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param Pci A pointer to PCI_TYPE00.
@param Width Signifies the width of the memory operations.
@param Offset The offset within the PCI configuration space for the PCI controller.
@param Count The number of unit to be read.
@param Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
**/
EFI_STATUS
PciRootBridgeIoWrite (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
IN PCI_TYPE00 *Pci,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Offset,
IN UINTN Count,
IN OUT VOID *Buffer
)
{
EFI_STATUS Status;
if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_WRITE_SUPPORT) != 0) {
//
// If PCI incompatibility check enabled
//
Status = PciIncompatibilityCheckWrite (
PciRootBridgeIo,
NULL,
Pci,
Width,
Offset,
Count,
Buffer
);
if (Status == EFI_UNSUPPORTED) {
return EFI_INVALID_PARAMETER;
} else {
return Status;
}
} else {
return PciRootBridgeIo->Pci.Write (
PciRootBridgeIo,
Width,
Offset,
Count,
Buffer
);
}
}
/**
Read PCI configuration space through EFI_PCI_IO_PROTOCOL.
@param PciIo A pointer to the EFI_PCI_O_PROTOCOL.
@param Width Signifies the width of the memory operations.
@param Offset The offset within the PCI configuration space for the PCI controller.
@param Count The number of unit to be read.
@param Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI controller.
@retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
valid for the PCI configuration header of the PCI controller.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
**/
EFI_STATUS
PciIoRead (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT32 Offset,
IN UINTN Count,
IN OUT VOID *Buffer
)
{
if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_READ_SUPPORT) != 0) {
//
// If PCI incompatibility check enabled
//
return PciIncompatibilityCheckRead (
NULL,
PciIo,
NULL,
(UINTN) Width,
Offset,
Count,
Buffer
);
} else {
return PciIo->Pci.Read (
PciIo,
Width,
Offset,
Count,
Buffer
);
}
}
/**
Write PCI configuration space through EFI_PCI_IO_PROTOCOL.
If PCI incompatibility check is enabled, do incompatibility check.
@param PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.
@param Width Signifies the width of the memory operations.
@param Offset The offset within the PCI configuration space for the PCI controller.
@param Count The number of PCI configuration operations to perform.
@param Buffer For read operations, the destination buffer to store the results. For write
operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI controller.
@retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
valid for the PCI configuration header of the PCI controller.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
**/
EFI_STATUS
PciIoWrite (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT32 Offset,
IN UINTN Count,
IN OUT VOID *Buffer
)
{
if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_WRITE_SUPPORT) != 0) {
//
// If PCI incompatibility check enabled
//
return PciIncompatibilityCheckWrite (
NULL,
PciIo,
NULL,
Width,
Offset,
Count,
Buffer
);
} else {
return PciIo->Pci.Write (
PciIo,
Width,
Offset,
Count,
Buffer
);
}
}

116
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.h
View File

@ -15,14 +15,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#ifndef _EFI_PCI_LIB_H_ #ifndef _EFI_PCI_LIB_H_
#define _EFI_PCI_LIB_H_ #define _EFI_PCI_LIB_H_
//
// Mask definistions for PCD PcdPciIncompatibleDeviceSupportMask
//
#define PCI_INCOMPATIBLE_ACPI_RESOURCE_SUPPORT 0x01
#define PCI_INCOMPATIBLE_READ_SUPPORT 0x02
#define PCI_INCOMPATIBLE_WRITE_SUPPORT 0x04
#define PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT 0x08
#define PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT 0x10
typedef struct { typedef struct {
EFI_HANDLE Handle; EFI_HANDLE Handle;
@ -146,113 +138,7 @@ PciHostBridgeP2CProcess (
**/ **/
EFI_STATUS EFI_STATUS
PciHostBridgeEnumerator ( PciHostBridgeEnumerator (
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
);
/**
Read PCI configuration space through EFI_PCI_IO_PROTOCOL.
@param PciIo A pointer to the EFI_PCI_O_PROTOCOL.
@param Width Signifies the width of the memory operations.
@param Offset The offset within the PCI configuration space for the PCI controller.
@param Count The number of unit to be read.
@param Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI controller.
@retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
valid for the PCI configuration header of the PCI controller.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
**/
EFI_STATUS
PciIoRead (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT32 Offset,
IN UINTN Count,
IN OUT VOID *Buffer
);
/**
Write PCI configuration space through EFI_PCI_IO_PROTOCOL.
If PCI incompatibility check is enabled, do incompatibility check.
@param PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.
@param Width Signifies the width of the memory operations.
@param Offset The offset within the PCI configuration space for the PCI controller.
@param Count The number of PCI configuration operations to perform.
@param Buffer For read operations, the destination buffer to store the results. For write
operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI controller.
@retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
valid for the PCI configuration header of the PCI controller.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
**/
EFI_STATUS
PciIoWrite (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT32 Offset,
IN UINTN Count,
IN OUT VOID *Buffer
);
/**
Write PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param Pci A pointer to PCI_TYPE00.
@param Width Signifies the width of the memory operations.
@param Offset The offset within the PCI configuration space for the PCI controller.
@param Count The number of unit to be read.
@param Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
**/
EFI_STATUS
PciRootBridgeIoWrite (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
IN PCI_TYPE00 *Pci,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Offset,
IN UINTN Count,
IN OUT VOID *Buffer
);
/**
Read PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param Pci A pointer to PCI_TYPE00.
@param Width Signifies the width of the memory operations.
@param Offset The offset within the PCI configuration space for the PCI controller.
@param Count The number of unit to be read.
@param Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
**/
EFI_STATUS
PciRootBridgeIoRead (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
IN PCI_TYPE00 *Pci, OPTIONAL
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Offset,
IN UINTN Count,
IN OUT VOID *Buffer
); );
#endif #endif

26
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c
View File

@ -216,9 +216,10 @@ LoadFile2 (
} }
/** /**
Get Pci device's oprom infor bits. Get Pci device's oprom information.
@param PciIoDevice Pci device instance. @param PciIoDevice Input Pci device instance.
Output Pci device instance with updated OptionRom size.
@retval EFI_NOT_FOUND Pci device has not Option Rom. @retval EFI_NOT_FOUND Pci device has not Option Rom.
@retval EFI_SUCCESS Pci device has Option Rom. @retval EFI_SUCCESS Pci device has Option Rom.
@ -226,7 +227,7 @@ LoadFile2 (
**/ **/
EFI_STATUS EFI_STATUS
GetOpRomInfo ( GetOpRomInfo (
IN PCI_IO_DEVICE *PciIoDevice IN OUT PCI_IO_DEVICE *PciIoDevice
) )
{ {
UINT8 RomBarIndex; UINT8 RomBarIndex;
@ -255,11 +256,7 @@ GetOpRomInfo (
if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) { if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {
// //
// If is ppb // If is ppb, 0x38
//
//
// 0x38
// //
RomBarIndex = PCI_BRIDGE_ROMBAR; RomBarIndex = PCI_BRIDGE_ROMBAR;
} }
@ -269,9 +266,8 @@ GetOpRomInfo (
AllOnes = 0xfffffffe; AllOnes = 0xfffffffe;
Address = EFI_PCI_ADDRESS (Bus, Device, Function, RomBarIndex); Address = EFI_PCI_ADDRESS (Bus, Device, Function, RomBarIndex);
Status = PciRootBridgeIoWrite ( Status = PciRootBridgeIo->Pci.Write (
PciRootBridgeIo, PciRootBridgeIo,
&PciIoDevice->Pci,
EfiPciWidthUint32, EfiPciWidthUint32,
Address, Address,
1, 1,
@ -284,9 +280,8 @@ GetOpRomInfo (
// //
// Read back // Read back
// //
Status = PciRootBridgeIoRead ( Status = PciRootBridgeIo->Pci.Read(
PciRootBridgeIo, PciRootBridgeIo,
&PciIoDevice->Pci,
EfiPciWidthUint32, EfiPciWidthUint32,
Address, Address,
1, 1,
@ -295,6 +290,7 @@ GetOpRomInfo (
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return EFI_NOT_FOUND; return EFI_NOT_FOUND;
} }
// //
// Bits [1, 10] are reserved // Bits [1, 10] are reserved
// //
@ -558,7 +554,7 @@ RomDecode (
// Clear all bars // Clear all bars
// //
for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) { for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) {
PciIoWrite (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllZero); PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllZero);
} }
// //
@ -566,7 +562,7 @@ RomDecode (
// enable its decoder // enable its decoder
// //
Value32 = RomBar | 0x1; Value32 = RomBar | 0x1;
PciIoWrite ( PciIo->Pci.Write (
PciIo, PciIo,
(EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32, (EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32,
RomBarIndex, RomBarIndex,
@ -600,7 +596,7 @@ RomDecode (
// disable rom decode // disable rom decode
// //
Value32 = 0xFFFFFFFE; Value32 = 0xFFFFFFFE;
PciIoWrite ( PciIo->Pci.Write (
PciIo, PciIo,
(EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32, (EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32,
RomBarIndex, RomBarIndex,

7
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.h
View File

@ -78,9 +78,10 @@ ContainEfiImage (
/** /**
Get Pci device's oprom infor bits. Get Pci device's oprom information.
@param PciIoDevice Pci device instance. @param PciIoDevice Input Pci device instance.
Output Pci device instance with updated OptionRom size.
@retval EFI_NOT_FOUND Pci device has not Option Rom. @retval EFI_NOT_FOUND Pci device has not Option Rom.
@retval EFI_SUCCESS Pci device has Option Rom. @retval EFI_SUCCESS Pci device has Option Rom.
@ -88,7 +89,7 @@ ContainEfiImage (
**/ **/
EFI_STATUS EFI_STATUS
GetOpRomInfo ( GetOpRomInfo (
IN PCI_IO_DEVICE *PciIoDevice IN OUT PCI_IO_DEVICE *PciIoDevice
); );
/** /**

2
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciPowerManagement.c
View File

@ -55,7 +55,7 @@ ResetPowerManagementFeature (
// //
// Write PMCSR // Write PMCSR
// //
PciIoWrite ( PciIoDevice->PciIo.Pci.Write (
&PciIoDevice->PciIo, &PciIoDevice->PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
PowerManagementRegBlock + 4, PowerManagementRegBlock + 4,

103
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
View File

@ -91,7 +91,7 @@ SkipIsaAliasAperture (
**/ **/
VOID VOID
InsertResourceNode ( InsertResourceNode (
IN PCI_RESOURCE_NODE *Bridge, IN OUT PCI_RESOURCE_NODE *Bridge,
IN PCI_RESOURCE_NODE *ResNode IN PCI_RESOURCE_NODE *ResNode
) )
{ {
@ -352,7 +352,6 @@ CalculateResourceAperture (
// //
// Apply padding resource if available // Apply padding resource if available
// //
Offset = Aperture & (Node->Alignment); Offset = Aperture & (Node->Alignment);
if (Offset != 0) { if (Offset != 0) {
@ -375,7 +374,6 @@ CalculateResourceAperture (
// //
// Consider the aperture alignment // Consider the aperture alignment
// //
CurrentLink = CurrentLink->ForwardLink; CurrentLink = CurrentLink->ForwardLink;
} }
@ -424,11 +422,11 @@ CalculateResourceAperture (
VOID VOID
GetResourceFromDevice ( GetResourceFromDevice (
IN PCI_IO_DEVICE *PciDev, IN PCI_IO_DEVICE *PciDev,
IN PCI_RESOURCE_NODE *IoNode, IN OUT PCI_RESOURCE_NODE *IoNode,
IN PCI_RESOURCE_NODE *Mem32Node, IN OUT PCI_RESOURCE_NODE *Mem32Node,
IN PCI_RESOURCE_NODE *PMem32Node, IN OUT PCI_RESOURCE_NODE *PMem32Node,
IN PCI_RESOURCE_NODE *Mem64Node, IN OUT PCI_RESOURCE_NODE *Mem64Node,
IN PCI_RESOURCE_NODE *PMem64Node IN OUT PCI_RESOURCE_NODE *PMem64Node
) )
{ {
@ -582,14 +580,12 @@ CreateResourceNode (
Node = NULL; Node = NULL;
Node = AllocatePool (sizeof (PCI_RESOURCE_NODE)); Node = AllocateZeroPool (sizeof (PCI_RESOURCE_NODE));
ASSERT (Node != NULL); ASSERT (Node != NULL);
if (Node == NULL) { if (Node == NULL) {
return NULL; return NULL;
} }
ZeroMem (Node, sizeof (PCI_RESOURCE_NODE));
Node->Signature = PCI_RESOURCE_SIGNATURE; Node->Signature = PCI_RESOURCE_SIGNATURE;
Node->PciDev = PciDev; Node->PciDev = PciDev;
Node->Length = Length; Node->Length = Length;
@ -618,11 +614,11 @@ CreateResourceNode (
VOID VOID
CreateResourceMap ( CreateResourceMap (
IN PCI_IO_DEVICE *Bridge, IN PCI_IO_DEVICE *Bridge,
IN PCI_RESOURCE_NODE *IoNode, IN OUT PCI_RESOURCE_NODE *IoNode,
IN PCI_RESOURCE_NODE *Mem32Node, IN OUT PCI_RESOURCE_NODE *Mem32Node,
IN PCI_RESOURCE_NODE *PMem32Node, IN OUT PCI_RESOURCE_NODE *PMem32Node,
IN PCI_RESOURCE_NODE *Mem64Node, IN OUT PCI_RESOURCE_NODE *Mem64Node,
IN PCI_RESOURCE_NODE *PMem64Node IN OUT PCI_RESOURCE_NODE *PMem64Node
) )
{ {
PCI_IO_DEVICE *Temp; PCI_IO_DEVICE *Temp;
@ -726,7 +722,7 @@ CreateResourceMap (
IoBridge IoBridge
); );
} else { } else {
gBS->FreePool (IoBridge); FreePool (IoBridge);
IoBridge = NULL; IoBridge = NULL;
} }
@ -742,7 +738,7 @@ CreateResourceMap (
Mem32Bridge Mem32Bridge
); );
} else { } else {
gBS->FreePool (Mem32Bridge); FreePool (Mem32Bridge);
Mem32Bridge = NULL; Mem32Bridge = NULL;
} }
@ -758,7 +754,7 @@ CreateResourceMap (
PMem32Bridge PMem32Bridge
); );
} else { } else {
gBS->FreePool (PMem32Bridge); FreePool (PMem32Bridge);
PMem32Bridge = NULL; PMem32Bridge = NULL;
} }
@ -774,7 +770,7 @@ CreateResourceMap (
Mem64Bridge Mem64Bridge
); );
} else { } else {
gBS->FreePool (Mem64Bridge); FreePool (Mem64Bridge);
Mem64Bridge = NULL; Mem64Bridge = NULL;
} }
@ -790,7 +786,7 @@ CreateResourceMap (
PMem64Bridge PMem64Bridge
); );
} else { } else {
gBS->FreePool (PMem64Bridge); FreePool (PMem64Bridge);
PMem64Bridge = NULL; PMem64Bridge = NULL;
} }
@ -799,7 +795,6 @@ CreateResourceMap (
// //
// If it is P2C, apply hard coded resource padding // If it is P2C, apply hard coded resource padding
// //
//
if (IS_CARDBUS_BRIDGE (&Temp->Pci)) { if (IS_CARDBUS_BRIDGE (&Temp->Pci)) {
ResourcePaddingForCardBusBridge ( ResourcePaddingForCardBusBridge (
Temp, Temp,
@ -813,7 +808,7 @@ CreateResourceMap (
CurrentLink = CurrentLink->ForwardLink; CurrentLink = CurrentLink->ForwardLink;
} }
//
// //
// To do some platform specific resource padding ... // To do some platform specific resource padding ...
// //
@ -1120,7 +1115,7 @@ ProgramBar (
case PciBarTypeMem32: case PciBarTypeMem32:
case PciBarTypePMem32: case PciBarTypePMem32:
PciIoWrite ( PciIo->Pci.Write (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
(Node->PciDev->PciBar[Node->Bar]).Offset, (Node->PciDev->PciBar[Node->Bar]).Offset,
@ -1137,7 +1132,7 @@ ProgramBar (
Address32 = (UINT32) (Address & 0x00000000FFFFFFFF); Address32 = (UINT32) (Address & 0x00000000FFFFFFFF);
PciIoWrite ( PciIo->Pci.Write (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
(Node->PciDev->PciBar[Node->Bar]).Offset, (Node->PciDev->PciBar[Node->Bar]).Offset,
@ -1147,7 +1142,7 @@ ProgramBar (
Address32 = (UINT32) RShiftU64 (Address, 32); Address32 = (UINT32) RShiftU64 (Address, 32);
PciIoWrite ( PciIo->Pci.Write (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
(UINT8) ((Node->PciDev->PciBar[Node->Bar]).Offset + 4), (UINT8) ((Node->PciDev->PciBar[Node->Bar]).Offset + 4),
@ -1205,7 +1200,7 @@ ProgramPpbApperture (
case PPB_BAR_0: case PPB_BAR_0:
case PPB_BAR_1: case PPB_BAR_1:
PciIoWrite ( PciIo->Pci.Write (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
(Node->PciDev->PciBar[Node->Bar]).Offset, (Node->PciDev->PciBar[Node->Bar]).Offset,
@ -1221,7 +1216,7 @@ ProgramPpbApperture (
case PPB_IO_RANGE: case PPB_IO_RANGE:
Address32 = ((UINT32) (Address)) >> 8; Address32 = ((UINT32) (Address)) >> 8;
PciIoWrite ( PciIo->Pci.Write (
PciIo, PciIo,
EfiPciIoWidthUint8, EfiPciIoWidthUint8,
0x1C, 0x1C,
@ -1230,7 +1225,7 @@ ProgramPpbApperture (
); );
Address32 >>= 8; Address32 >>= 8;
PciIoWrite ( PciIo->Pci.Write (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
0x30, 0x30,
@ -1240,7 +1235,7 @@ ProgramPpbApperture (
Address32 = (UINT32) (Address + Node->Length - 1); Address32 = (UINT32) (Address + Node->Length - 1);
Address32 = ((UINT32) (Address32)) >> 8; Address32 = ((UINT32) (Address32)) >> 8;
PciIoWrite ( PciIo->Pci.Write (
PciIo, PciIo,
EfiPciIoWidthUint8, EfiPciIoWidthUint8,
0x1D, 0x1D,
@ -1249,7 +1244,7 @@ ProgramPpbApperture (
); );
Address32 >>= 8; Address32 >>= 8;
PciIoWrite ( PciIo->Pci.Write (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
0x32, 0x32,
@ -1264,7 +1259,7 @@ ProgramPpbApperture (
case PPB_MEM32_RANGE: case PPB_MEM32_RANGE:
Address32 = ((UINT32) (Address)) >> 16; Address32 = ((UINT32) (Address)) >> 16;
PciIoWrite ( PciIo->Pci.Write (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
0x20, 0x20,
@ -1274,7 +1269,7 @@ ProgramPpbApperture (
Address32 = (UINT32) (Address + Node->Length - 1); Address32 = (UINT32) (Address + Node->Length - 1);
Address32 = ((UINT32) (Address32)) >> 16; Address32 = ((UINT32) (Address32)) >> 16;
PciIoWrite ( PciIo->Pci.Write (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
0x22, 0x22,
@ -1290,7 +1285,7 @@ ProgramPpbApperture (
case PPB_PMEM64_RANGE: case PPB_PMEM64_RANGE:
Address32 = ((UINT32) (Address)) >> 16; Address32 = ((UINT32) (Address)) >> 16;
PciIoWrite ( PciIo->Pci.Write (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
0x24, 0x24,
@ -1300,7 +1295,7 @@ ProgramPpbApperture (
Address32 = (UINT32) (Address + Node->Length - 1); Address32 = (UINT32) (Address + Node->Length - 1);
Address32 = ((UINT32) (Address32)) >> 16; Address32 = ((UINT32) (Address32)) >> 16;
PciIoWrite ( PciIo->Pci.Write (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
0x26, 0x26,
@ -1309,7 +1304,7 @@ ProgramPpbApperture (
); );
Address32 = (UINT32) RShiftU64 (Address, 32); Address32 = (UINT32) RShiftU64 (Address, 32);
PciIoWrite ( PciIo->Pci.Write (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
0x28, 0x28,
@ -1318,7 +1313,7 @@ ProgramPpbApperture (
); );
Address32 = (UINT32) RShiftU64 ((Address + Node->Length - 1), 32); Address32 = (UINT32) RShiftU64 ((Address + Node->Length - 1), 32);
PciIoWrite ( PciIo->Pci.Write (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
0x2C, 0x2C,
@ -1707,7 +1702,7 @@ ProgramP2C (
switch (Node->Bar) { switch (Node->Bar) {
case P2C_BAR_0: case P2C_BAR_0:
PciIoWrite ( PciIo->Pci.Write (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
(Node->PciDev->PciBar[Node->Bar]).Offset, (Node->PciDev->PciBar[Node->Bar]).Offset,
@ -1720,7 +1715,7 @@ ProgramP2C (
break; break;
case P2C_MEM_1: case P2C_MEM_1:
PciIoWrite ( PciIo->Pci.Write (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
PCI_CARD_MEMORY_BASE_0, PCI_CARD_MEMORY_BASE_0,
@ -1729,7 +1724,7 @@ ProgramP2C (
); );
TempAddress = Address + Node->Length - 1; TempAddress = Address + Node->Length - 1;
PciIoWrite ( PciIo->Pci.Write (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
PCI_CARD_MEMORY_LIMIT_0, PCI_CARD_MEMORY_LIMIT_0,
@ -1741,7 +1736,7 @@ ProgramP2C (
// //
// Set non-prefetchable bit // Set non-prefetchable bit
// //
PciIoRead ( PciIo->Pci.Read (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
PCI_CARD_BRIDGE_CONTROL, PCI_CARD_BRIDGE_CONTROL,
@ -1750,7 +1745,7 @@ ProgramP2C (
); );
BridgeControl &= (UINT16) ~PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE; BridgeControl &= (UINT16) ~PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE;
PciIoWrite ( PciIo->Pci.Write (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
PCI_CARD_BRIDGE_CONTROL, PCI_CARD_BRIDGE_CONTROL,
@ -1762,7 +1757,7 @@ ProgramP2C (
// //
// Set pre-fetchable bit // Set pre-fetchable bit
// //
PciIoRead ( PciIo->Pci.Read (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
PCI_CARD_BRIDGE_CONTROL, PCI_CARD_BRIDGE_CONTROL,
@ -1771,7 +1766,7 @@ ProgramP2C (
); );
BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE; BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE;
PciIoWrite ( PciIo->Pci.Write (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
PCI_CARD_BRIDGE_CONTROL, PCI_CARD_BRIDGE_CONTROL,
@ -1787,7 +1782,7 @@ ProgramP2C (
break; break;
case P2C_MEM_2: case P2C_MEM_2:
PciIoWrite ( PciIo->Pci.Write (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
PCI_CARD_MEMORY_BASE_1, PCI_CARD_MEMORY_BASE_1,
@ -1797,7 +1792,7 @@ ProgramP2C (
TempAddress = Address + Node->Length - 1; TempAddress = Address + Node->Length - 1;
PciIoWrite ( PciIo->Pci.Write (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
PCI_CARD_MEMORY_LIMIT_1, PCI_CARD_MEMORY_LIMIT_1,
@ -1810,7 +1805,7 @@ ProgramP2C (
// //
// Set non-prefetchable bit // Set non-prefetchable bit
// //
PciIoRead ( PciIo->Pci.Read (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
PCI_CARD_BRIDGE_CONTROL, PCI_CARD_BRIDGE_CONTROL,
@ -1819,7 +1814,7 @@ ProgramP2C (
); );
BridgeControl &= (UINT16) ~(PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE); BridgeControl &= (UINT16) ~(PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE);
PciIoWrite ( PciIo->Pci.Write (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
PCI_CARD_BRIDGE_CONTROL, PCI_CARD_BRIDGE_CONTROL,
@ -1832,7 +1827,7 @@ ProgramP2C (
// //
// Set pre-fetchable bit // Set pre-fetchable bit
// //
PciIoRead ( PciIo->Pci.Read (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
PCI_CARD_BRIDGE_CONTROL, PCI_CARD_BRIDGE_CONTROL,
@ -1841,7 +1836,7 @@ ProgramP2C (
); );
BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE; BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE;
PciIoWrite ( PciIo->Pci.Write (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
PCI_CARD_BRIDGE_CONTROL, PCI_CARD_BRIDGE_CONTROL,
@ -1856,7 +1851,7 @@ ProgramP2C (
break; break;
case P2C_IO_1: case P2C_IO_1:
PciIoWrite ( PciIo->Pci.Write (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
PCI_CARD_IO_BASE_0_LOWER, PCI_CARD_IO_BASE_0_LOWER,
@ -1865,7 +1860,7 @@ ProgramP2C (
); );
TempAddress = Address + Node->Length - 1; TempAddress = Address + Node->Length - 1;
PciIoWrite ( PciIo->Pci.Write (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
PCI_CARD_IO_LIMIT_0_LOWER, PCI_CARD_IO_LIMIT_0_LOWER,
@ -1880,7 +1875,7 @@ ProgramP2C (
break; break;
case P2C_IO_2: case P2C_IO_2:
PciIoWrite ( PciIo->Pci.Write (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
PCI_CARD_IO_BASE_1_LOWER, PCI_CARD_IO_BASE_1_LOWER,
@ -1889,7 +1884,7 @@ ProgramP2C (
); );
TempAddress = Address + Node->Length - 1; TempAddress = Address + Node->Length - 1;
PciIoWrite ( PciIo->Pci.Write (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
PCI_CARD_IO_LIMIT_1_LOWER, PCI_CARD_IO_LIMIT_1_LOWER,

22
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.h
View File

@ -76,7 +76,7 @@ SkipIsaAliasAperture (
**/ **/
VOID VOID
InsertResourceNode ( InsertResourceNode (
IN PCI_RESOURCE_NODE *Bridge, IN OUT PCI_RESOURCE_NODE *Bridge,
IN PCI_RESOURCE_NODE *ResNode IN PCI_RESOURCE_NODE *ResNode
); );
@ -143,11 +143,11 @@ CalculateResourceAperture (
VOID VOID
GetResourceFromDevice ( GetResourceFromDevice (
IN PCI_IO_DEVICE *PciDev, IN PCI_IO_DEVICE *PciDev,
IN PCI_RESOURCE_NODE *IoNode, IN OUT PCI_RESOURCE_NODE *IoNode,
IN PCI_RESOURCE_NODE *Mem32Node, IN OUT PCI_RESOURCE_NODE *Mem32Node,
IN PCI_RESOURCE_NODE *PMem32Node, IN OUT PCI_RESOURCE_NODE *PMem32Node,
IN PCI_RESOURCE_NODE *Mem64Node, IN OUT PCI_RESOURCE_NODE *Mem64Node,
IN PCI_RESOURCE_NODE *PMem64Node IN OUT PCI_RESOURCE_NODE *PMem64Node
); );
/** /**
@ -189,11 +189,11 @@ CreateResourceNode (
VOID VOID
CreateResourceMap ( CreateResourceMap (
IN PCI_IO_DEVICE *Bridge, IN PCI_IO_DEVICE *Bridge,
IN PCI_RESOURCE_NODE *IoNode, IN OUT PCI_RESOURCE_NODE *IoNode,
IN PCI_RESOURCE_NODE *Mem32Node, IN OUT PCI_RESOURCE_NODE *Mem32Node,
IN PCI_RESOURCE_NODE *PMem32Node, IN OUT PCI_RESOURCE_NODE *PMem32Node,
IN PCI_RESOURCE_NODE *Mem64Node, IN OUT PCI_RESOURCE_NODE *Mem64Node,
IN PCI_RESOURCE_NODE *PMem64Node IN OUT PCI_RESOURCE_NODE *PMem64Node
); );
/** /**

146
IntelFrameworkModulePkg/Include/Library/PciIncompatibleDeviceSupportLib.h
View File

@ -1,146 +0,0 @@
/** @file
PCI Incompatible device support Libary. Platform can implement an
instance to support the incompatible PCI devices.
Copyright (c) 2006 - 2009, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __PCI_INCOMPATIBLE_DEVICE_SUPPORT_LIB_H__
#define __PCI_INCOMPATIBLE_DEVICE_SUPPORT_LIB_H__
#define PCI_REGISTER_READ 0xfffffffffffffff1ULL
#define PCI_REGISTER_WRITE 0xfffffffffffffff2ULL
#define VALUE_NOCARE 0xffffffffffffffffULL
//
// PCI device device information
//
typedef struct {
UINT64 VendorID;
UINT64 DeviceID;
UINT64 RevisionID;
UINT64 SubsystemVendorID;
UINT64 SubsystemID;
} EFI_PCI_DEVICE_INFO;
//
// store hardcode value of resgister
//
typedef struct {
UINT64 AndValue;
UINT64 OrValue;
} EFI_PCI_REGISTER_VALUE_DATA;
//
// store access width information
//
typedef struct {
UINT64 StartOffset;
UINT64 EndOffset;
UINT64 Width;
} EFI_PCI_REGISTER_ACCESS_DATA;
//
// ACPI resource descriptor
//
typedef struct {
UINT64 ResType;
UINT64 GenFlag;
UINT64 SpecificFlag;
UINT64 AddrSpaceGranularity;
UINT64 AddrRangeMin;
UINT64 AddrRangeMax;
UINT64 AddrTranslationOffset;
UINT64 AddrLen;
} EFI_PCI_RESOUCE_DESCRIPTOR;
/**
Check the incompatible device list for ACPI resource update and return
the configuration.
This function searches the incompatible device list according to request
information. If the PCI device belongs to the devices list, corresponding
configuration informtion will be returned, in the meantime return EFI_SUCCESS.
@param PciDeviceInfo A pointer to PCI device information.
@param Configuration Returned information.
@retval EFI_SUCCESS If check incompatible device successfully.
@retval EFI_ABORTED No any resource type.
@retval EFI_OUT_OF_RESOURCES No memory available.
@retval EFI_UNSUPPORTED Invalid Tag encounted.
**/
EFI_STATUS
EFIAPI
PciResourceUpdateCheck (
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,
OUT VOID *Configuration
);
/**
Check the incompatible device list and return configuraton register mask values.
This function searches the incompatible device list according to request
information. If the PCI device belongs to the devices list, corresponding
configuration informtion will be returned, in the meantime return EFI_SUCCESS.
@param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.
@param AccessType Access Type, READ or WRITE.
@param Offset The address within the PCI configuration space.
@param Configuration Returned information.
@retval EFI_SUCCESS If check incompatible device successfully.
@retval EFI_UNSUPPORTED Failed to check incompatibility device.
**/
EFI_STATUS
EFIAPI
PciRegisterUpdateCheck (
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,
IN UINT64 AccessType,
IN UINT64 Offset,
OUT VOID *Configuration
);
/**
Check the incompatible device list for access width incompatibility and
return the configuration.
This function searches the incompatible device list for access width
incompatibility according to request information. If the PCI device
belongs to the devices list, corresponding configuration informtion
will be returned, in the meantime return EFI_SUCCESS.
@param PciDeviceInfo A pointer to PCI device information.
@param AccessType Access type, READ or WRITE.
@param Offset The address within the PCI configuration space.
@param AccessWidth Access width needs to check incompatibility.
@param Configuration Returned information.
@retval EFI_SUCCESS If check incompatible device successfully.
@retval EFI_UNSUPPORTED Failed to check incompatibility device.
**/
EFI_STATUS
EFIAPI
PciRegisterAccessCheck (
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,
IN UINT64 AccessType,
IN UINT64 Offset,
IN UINT64 AccessWidth,
OUT VOID *Configuration
);
#endif

8
IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
View File

@ -24,9 +24,6 @@
Include # Root include for the package Include # Root include for the package
[LibraryClasses.common] [LibraryClasses.common]
## @libraryclass This libary is used to support the incompatible PCI devices.
PciIncompatibleDeviceSupportLib|Include/Library/PciIncompatibleDeviceSupportLib.h
## @libraryclass OEM status code libary is used to report status code to OEM device. ## @libraryclass OEM status code libary is used to report status code to OEM device.
OemHookStatusCodeLib|Include/Library/OemHookStatusCodeLib.h OemHookStatusCodeLib|Include/Library/OemHookStatusCodeLib.h
@ -139,11 +136,6 @@
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdIsaBusOnlySupportSlaveDma|FALSE|BOOLEAN|0x00010041 gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdIsaBusOnlySupportSlaveDma|FALSE|BOOLEAN|0x00010041
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdIsaBusSupportIsaMemory|TRUE|BOOLEAN|0x00010042 gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdIsaBusSupportIsaMemory|TRUE|BOOLEAN|0x00010042
[PcdsFixedAtBuild]
## PCD marks PCI support incompatible operations: AcpiResource, Read, Write, RegisterUpdate, AccessWidth.
# BIT0:AcpiResource, BIT1:Read, BIT2:Write, BIT3:RegisterUpdate, BIT4:AccessWidth
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPciIncompatibleDeviceSupportMask|0|UINT8|0x0001003f
[PcdsFixedAtBuild,PcdsPatchableInModule,PcdsDynamic] [PcdsFixedAtBuild,PcdsPatchableInModule,PcdsDynamic]
## PcdStatusCodeMemorySize is used when PcdStatusCodeUseMemory is set to true ## PcdStatusCodeMemorySize is used when PcdStatusCodeUseMemory is set to true
# (PcdStatusCodeMemorySize * KBytes) is the total taken memory size. # (PcdStatusCodeMemorySize * KBytes) is the total taken memory size.

6
IntelFrameworkModulePkg/IntelFrameworkModulePkg.dsc
View File

@ -3,7 +3,7 @@
# #
# This file is used to build all modules in IntelFrameworkModulePkg. # This file is used to build all modules in IntelFrameworkModulePkg.
# #
# Copyright (c) 2007, Intel Corporation # Copyright (c) 2007 - 2009, Intel Corporation
# #
# All rights reserved. This program and the accompanying materials # All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License # are licensed and made available under the terms and conditions of the BSD License
@ -90,7 +90,6 @@
UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
PciIncompatibleDeviceSupportLib|IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/PciIncompatibleDeviceSupportLib.inf
IoLib|IntelFrameworkPkg/Library/DxeIoLibCpuIo/DxeIoLibCpuIo.inf IoLib|IntelFrameworkPkg/Library/DxeIoLibCpuIo/DxeIoLibCpuIo.inf
[LibraryClasses.common.DXE_RUNTIME_DRIVER] [LibraryClasses.common.DXE_RUNTIME_DRIVER]
@ -118,7 +117,6 @@
UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
PciIncompatibleDeviceSupportLib|IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/PciIncompatibleDeviceSupportLib.inf
IoLib|IntelFrameworkPkg/Library/DxeIoLibCpuIo/DxeIoLibCpuIo.inf IoLib|IntelFrameworkPkg/Library/DxeIoLibCpuIo/DxeIoLibCpuIo.inf
################################################################################ ################################################################################
@ -149,7 +147,6 @@
gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0 gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPciIncompatibleDeviceSupportMask|0
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0xFFFB0000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0xFFFB0000
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
@ -189,7 +186,6 @@
IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
IntelFrameworkModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf IntelFrameworkModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/PciIncompatibleDeviceSupportLib.inf
IntelFrameworkModulePkg/Library/PeiS3Lib/PeiS3Lib.inf IntelFrameworkModulePkg/Library/PeiS3Lib/PeiS3Lib.inf
IntelFrameworkModulePkg/Library/PeiRecoveryLib/PeiRecoveryLib.inf IntelFrameworkModulePkg/Library/PeiRecoveryLib/PeiRecoveryLib.inf
IntelFrameworkModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf IntelFrameworkModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf

54
IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/IncompatiblePciDeviceList.h
View File

@ -1,54 +0,0 @@
/** @file
The incompatible PCI device list template.
Copyright (c) 2006 - 2009, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _EFI_INCOMPATIBLE_PCI_DEVICE_LIST_H_
#define _EFI_INCOMPATIBLE_PCI_DEVICE_LIST_H_
#include <Library/PciIncompatibleDeviceSupportLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
#include <IndustryStandard/Pci.h>
#include <IndustryStandard/Acpi.h>
#define PCI_DEVICE_ID(VendorId, DeviceId, Revision, SubVendorId, SubDeviceId) \
VendorId, DeviceId, Revision, SubVendorId, SubDeviceId
#define PCI_BAR_TYPE_IO ACPI_ADDRESS_SPACE_TYPE_IO
#define PCI_BAR_TYPE_MEM ACPI_ADDRESS_SPACE_TYPE_MEM
#define DEVICE_INF_TAG 0xFFF2
#define DEVICE_RES_TAG 0xFFF1
#define LIST_END_TAG 0x0000
//
// descriptor for access width of incompatible PCI device
//
typedef struct {
UINT64 AccessType;
UINT64 AccessWidth;
EFI_PCI_REGISTER_ACCESS_DATA PciRegisterAccessData;
} EFI_PCI_REGISTER_ACCESS_DESCRIPTOR;
//
// descriptor for register value of incompatible PCI device
//
typedef struct {
UINT64 AccessType;
UINT64 Offset;
EFI_PCI_REGISTER_VALUE_DATA PciRegisterValueData;
} EFI_PCI_REGISTER_VALUE_DESCRIPTOR;
#endif

521
IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/PciIncompatibleDeviceSupportLib.c
View File

@ -1,521 +0,0 @@
/** @file
The template of PCI incompatible device support libary.
Copyright (c) 2006 - 2009, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "IncompatiblePciDeviceList.h"
//
// the incompatible PCI devices list template for ACPI resource
//
GLOBAL_REMOVE_IF_UNREFERENCED UINT64 gIncompatiblePciDeviceListForResource[] = {
//
// DEVICE_INF_TAG,
// PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),
// DEVICE_RES_TAG,
// ResType, GFlag , SFlag, Granularity, RangeMin,
// RangeMax, Offset, AddrLen
//
//
// Sample Device 1
//
//DEVICE_INF_TAG,
//PCI_DEVICE_ID(0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),
//DEVICE_RES_TAG,
//PCI_BAR_TYPE_IO,
//PCI_ACPI_UNUSED,
//PCI_ACPI_UNUSED,
//PCI_ACPI_UNUSED,
//PCI_ACPI_UNUSED,
//PCI_BAR_EVEN_ALIGN,
//PCI_BAR_ALL,
//PCI_BAR_NOCHANGE,
//
// Sample Device 2
//
//DEVICE_INF_TAG,
//PCI_DEVICE_ID(0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),
//DEVICE_RES_TAG,
//PCI_BAR_TYPE_IO,
//PCI_ACPI_UNUSED,
//PCI_ACPI_UNUSED,
//PCI_ACPI_UNUSED,
//PCI_ACPI_UNUSED,
//PCI_BAR_EVEN_ALIGN,
//PCI_BAR_ALL,
//PCI_BAR_NOCHANGE,
//
// The end of the list
//
LIST_END_TAG
};
//
// the incompatible PCI devices list template for the values of configuration registers
//
GLOBAL_REMOVE_IF_UNREFERENCED UINT64 gIncompatiblePciDeviceListForRegister[] = {
//
// DEVICE_INF_TAG,
// PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),
// PCI_RES_TAG,
// PCI_ACCESS_TYPE, PCI_CONFIG_ADDRESS,
// AND_VALUE, OR_VALUE
//
// Sample Device 1
//
//DEVICE_INF_TAG,
//PCI_DEVICE_ID(0xXXXX, 0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),
//DEVICE_RES_TAG,
//PCI_REGISTER_READ,
//PCI_CAPBILITY_POINTER_OFFSET,
//0xffffff00,
//VALUE_NOCARE,
//
// Sample Device 2
//
//DEVICE_INF_TAG,
//PCI_DEVICE_ID(0xXXXX, 0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),
//DEVICE_RES_TAG,
//PCI_REGISTER_READ,
//PCI_CAPBILITY_POINTER_OFFSET,
//0xffffff00,
//VALUE_NOCARE,
//
// The end of the list
//
LIST_END_TAG
};
//
// the incompatible PCI devices list template for the access width of configuration registers
//
GLOBAL_REMOVE_IF_UNREFERENCED UINT64 gDeviceListForAccessWidth[] = {
//
// DEVICE_INF_TAG,
// PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),
// DEVICE_RES_TAG,
// PCI_ACCESS_TYPE, PCI_ACCESS_WIDTH,
// START_ADDRESS, END_ADDRESS,
// ACTUAL_PCI_ACCESS_WIDTH,
//
//
// Sample Device
//
//DEVICE_INF_TAG,
//PCI_DEVICE_ID(0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),
//DEVICE_RES_TAG,
//PCI_REGISTER_READ,
//EfiPciWidthUint8,
//0,
//0xFF,
//EfiPciWidthUint32,
//
//
// The end of the list
//
LIST_END_TAG
};
GLOBAL_REMOVE_IF_UNREFERENCED EFI_PCI_REGISTER_ACCESS_DATA mPciRegisterAccessData = {0, 0, 0};
GLOBAL_REMOVE_IF_UNREFERENCED EFI_PCI_REGISTER_VALUE_DATA mPciRegisterValueData = {0, 0};
/**
Check whether two PCI devices matched.
@param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.
@param Header A pointer to EFI_PCI_DEVICE_INFO.
@retval EFI_SUCCESS Two PCI devices matched.
@retval EFI_UNSUPPORTED Two PCI devices don't match.
**/
EFI_STATUS
DeviceCheck (
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,
IN EFI_PCI_DEVICE_INFO *Header
)
{
//
// See if the Header matches the parameters passed in
//
if (Header->VendorID != DEVICE_ID_NOCARE) {
if (PciDeviceInfo->VendorID != Header->VendorID) {
return EFI_UNSUPPORTED;
}
}
if (Header->DeviceID != DEVICE_ID_NOCARE) {
if (PciDeviceInfo->DeviceID != Header->DeviceID) {
return EFI_UNSUPPORTED;
}
}
if (Header->RevisionID != DEVICE_ID_NOCARE) {
if (PciDeviceInfo->RevisionID != Header->RevisionID) {
return EFI_UNSUPPORTED;
}
}
if (Header->SubsystemVendorID != DEVICE_ID_NOCARE) {
if (PciDeviceInfo->SubsystemVendorID != Header->SubsystemVendorID) {
return EFI_UNSUPPORTED;
}
}
if (Header->SubsystemID != DEVICE_ID_NOCARE) {
if (PciDeviceInfo->SubsystemID != Header->SubsystemID) {
return EFI_UNSUPPORTED;
}
}
return EFI_SUCCESS;
}
/**
Check the incompatible device list for ACPI resource update and return
the configuration.
This function searches the incompatible device list according to request
information. If the PCI device belongs to the devices list, corresponding
configuration informtion will be returned, in the meantime return EFI_SUCCESS.
@param PciDeviceInfo A pointer to PCI device information.
@param Configuration Returned information.
@retval EFI_SUCCESS If check incompatible device successfully.
@retval EFI_ABORTED No any resource type.
@retval EFI_OUT_OF_RESOURCES No memory available.
@retval EFI_UNSUPPORTED Invalid Tag encounted.
**/
EFI_STATUS
EFIAPI
PciResourceUpdateCheck (
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,
OUT VOID *Configuration
)
{
UINT64 Tag;
UINT64 *ListPtr;
UINT64 *TempListPtr;
EFI_PCI_DEVICE_INFO *Header;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *AcpiPtr;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *OldAcpiPtr;
EFI_PCI_RESOUCE_DESCRIPTOR *Dsc;
EFI_ACPI_END_TAG_DESCRIPTOR *PtrEnd;
UINTN Index;
ASSERT (PciDeviceInfo != NULL);
//
// Initialize the return value to NULL
//
* (VOID **) Configuration = NULL;
ListPtr = gIncompatiblePciDeviceListForResource;
while (*ListPtr != LIST_END_TAG) {
Tag = *ListPtr;
switch (Tag) {
case DEVICE_INF_TAG:
Header = (EFI_PCI_DEVICE_INFO *) (ListPtr + 1);
ListPtr = ListPtr + 1 + sizeof (EFI_PCI_DEVICE_INFO) / sizeof (UINT64);
if (DeviceCheck (PciDeviceInfo, Header) != EFI_SUCCESS) {
continue;
}
//
// Matched an item, so construct the ACPI descriptor for the resource.
//
//
// Count the resource items so that to allocate space
//
for (Index = 0, TempListPtr = ListPtr; *TempListPtr == DEVICE_RES_TAG; Index++) {
TempListPtr = TempListPtr + 1 + ((sizeof (EFI_PCI_RESOUCE_DESCRIPTOR)) / sizeof (UINT64));
}
//
// If there is at least one type of resource request,
// allocate a acpi resource node
//
if (Index == 0) {
return EFI_ABORTED;
}
AcpiPtr = AllocateZeroPool (
sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * Index + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)
);
if (AcpiPtr == NULL) {
return EFI_OUT_OF_RESOURCES;
}
OldAcpiPtr = AcpiPtr;
//
// Fill the EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR structure
// according to the EFI_PCI_RESOUCE_DESCRIPTOR structure
//
for (; *ListPtr == DEVICE_RES_TAG;) {
Dsc = (EFI_PCI_RESOUCE_DESCRIPTOR *) (ListPtr + 1);
AcpiPtr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
AcpiPtr->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
AcpiPtr->ResType = (UINT8) Dsc->ResType;
AcpiPtr->GenFlag = (UINT8) Dsc->GenFlag;
AcpiPtr->SpecificFlag = (UINT8) Dsc->SpecificFlag;
AcpiPtr->AddrSpaceGranularity = Dsc->AddrSpaceGranularity;;
AcpiPtr->AddrRangeMin = Dsc->AddrRangeMin;
AcpiPtr->AddrRangeMax = Dsc->AddrRangeMax;
AcpiPtr->AddrTranslationOffset = Dsc->AddrTranslationOffset;
AcpiPtr->AddrLen = Dsc->AddrLen;
ListPtr = ListPtr + 1 + ((sizeof (EFI_PCI_RESOUCE_DESCRIPTOR)) / sizeof (UINT64));
AcpiPtr++;
}
//
// put the checksum
//
PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) (AcpiPtr);
PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;
PtrEnd->Checksum = 0;
*(VOID **) Configuration = OldAcpiPtr;
return EFI_SUCCESS;
case DEVICE_RES_TAG:
//
// Adjust the pointer to the next PCI resource descriptor item
//
ListPtr = ListPtr + 1 + ((sizeof (EFI_PCI_RESOUCE_DESCRIPTOR)) / sizeof (UINT64));
break;
default:
return EFI_UNSUPPORTED;
}
}
return EFI_UNSUPPORTED;
}
/**
Check the incompatible device list and return configuraton register mask values.
This function searches the incompatible device list according to request
information. If the PCI device belongs to the devices list, corresponding
configuration informtion will be returned, in the meantime return EFI_SUCCESS.
@param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.
@param AccessType Access Type, READ or WRITE.
@param Offset The address within the PCI configuration space.
@param Configuration Returned information.
@retval EFI_SUCCESS If check incompatible device successfully.
@retval EFI_UNSUPPORTED Failed to check incompatibility device.
**/
EFI_STATUS
EFIAPI
PciRegisterUpdateCheck (
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,
IN UINT64 AccessType,
IN UINT64 Offset,
OUT VOID *Configuration
)
{
EFI_PCI_DEVICE_INFO *Header;
UINT64 Tag;
UINT64 *ListPtr;
EFI_PCI_REGISTER_VALUE_DATA *RegisterPtr;
EFI_PCI_REGISTER_VALUE_DATA *Dsc;
ASSERT (PciDeviceInfo != NULL);
ListPtr = gIncompatiblePciDeviceListForRegister;
//
// Initialize the return value to NULL
//
* (VOID **) Configuration = NULL;
while (*ListPtr != LIST_END_TAG) {
Tag = *ListPtr;
switch (Tag) {
case DEVICE_INF_TAG:
Header = (EFI_PCI_DEVICE_INFO *) (ListPtr + 1);
ListPtr = ListPtr + 1 + sizeof (EFI_PCI_DEVICE_INFO) / sizeof (UINT64);
//
// Check whether the PCI device matches the device in the incompatible devices list?
// If not, ship next
//
if (DeviceCheck (PciDeviceInfo, Header) != EFI_SUCCESS) {
continue;
}
//
// Matched an item, check whether access matches?
//
for (; *ListPtr == DEVICE_RES_TAG;) {
ListPtr ++;
if (((EFI_PCI_REGISTER_VALUE_DESCRIPTOR *)ListPtr)->Offset == (Offset & 0xfc)) {
if (((EFI_PCI_REGISTER_VALUE_DESCRIPTOR *)ListPtr)->AccessType == AccessType) {
Dsc = (EFI_PCI_REGISTER_VALUE_DATA *) (ListPtr + 2);
RegisterPtr = &mPciRegisterValueData;
RegisterPtr->AndValue = Dsc->AndValue;
RegisterPtr->OrValue = Dsc->OrValue;
*(VOID **) Configuration = RegisterPtr;
return EFI_SUCCESS;
}
}
ListPtr += sizeof (EFI_PCI_REGISTER_VALUE_DESCRIPTOR) / (sizeof (UINT64));
}
return EFI_UNSUPPORTED;
case DEVICE_RES_TAG:
//
// Adjust the pointer to the next item
//
ListPtr = ListPtr + 1 + ((sizeof (EFI_PCI_REGISTER_VALUE_DESCRIPTOR)) / sizeof (UINT64));
break;
default:
return EFI_UNSUPPORTED;
}
}
return EFI_UNSUPPORTED;
}
/**
Check the incompatible device list for access width incompatibility and
return the configuration.
This function searches the incompatible device list for access width
incompatibility according to request information. If the PCI device
belongs to the devices list, corresponding configuration informtion
will be returned, in the meantime return EFI_SUCCESS.
@param PciDeviceInfo A pointer to PCI device information.
@param AccessType Access type, READ or WRITE.
@param Offset The address within the PCI configuration space.
@param AccessWidth Access width needs to check incompatibility.
@param Configuration Returned information.
@retval EFI_SUCCESS If check incompatible device successfully.
@retval EFI_UNSUPPORTED Failed to check incompatibility device.
**/
EFI_STATUS
EFIAPI
PciRegisterAccessCheck (
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,
IN UINT64 AccessType,
IN UINT64 Offset,
IN UINT64 AccessWidth,
OUT VOID *Configuration
)
{
EFI_PCI_DEVICE_INFO *Header;
UINT64 Tag;
UINT64 *ListPtr;
EFI_PCI_REGISTER_ACCESS_DATA *RegisterPtr;
EFI_PCI_REGISTER_ACCESS_DATA *Dsc;
ASSERT (PciDeviceInfo != NULL);
ListPtr = gDeviceListForAccessWidth;
//
// Initialize the return value to NULL
//
* (VOID **) Configuration = NULL;
while (*ListPtr != LIST_END_TAG) {
Tag = *ListPtr;
switch (Tag) {
case DEVICE_INF_TAG:
Header = (EFI_PCI_DEVICE_INFO *) (ListPtr + 1);
ListPtr = ListPtr + 1 + sizeof (EFI_PCI_DEVICE_INFO) / sizeof (UINT64);
//
// Check whether the PCI device matches the device in the incompatible devices list?
// If not, ship next
//
if (DeviceCheck (PciDeviceInfo, Header) != EFI_SUCCESS) {
continue;
}
//
// Matched an item, check whether access matches?
//
for (; *ListPtr == DEVICE_RES_TAG;) {
ListPtr ++;
if (((EFI_PCI_REGISTER_ACCESS_DESCRIPTOR *) ListPtr)->AccessType == AccessType &&
((EFI_PCI_REGISTER_ACCESS_DESCRIPTOR *) ListPtr)->AccessWidth == AccessWidth ) {
Dsc = (EFI_PCI_REGISTER_ACCESS_DATA *) (ListPtr + 2);
if((Dsc->StartOffset <= Offset) && (Dsc->EndOffset > Offset)) {
RegisterPtr = &mPciRegisterAccessData;
RegisterPtr->StartOffset = Dsc->StartOffset;
RegisterPtr->EndOffset = Dsc->EndOffset;
RegisterPtr->Width = Dsc->Width;
*(VOID **) Configuration = RegisterPtr;
return EFI_SUCCESS;
}
}
ListPtr += sizeof (EFI_PCI_REGISTER_ACCESS_DESCRIPTOR) / (sizeof (UINT64));
}
return EFI_UNSUPPORTED;
case DEVICE_RES_TAG:
//
// Adjust the pointer to the next item
//
ListPtr = ListPtr + 1 + ((sizeof (EFI_PCI_REGISTER_ACCESS_DESCRIPTOR)) / sizeof (UINT64));
break;
default:
return EFI_UNSUPPORTED;
}
}
return EFI_UNSUPPORTED;
}

42
IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/PciIncompatibleDeviceSupportLib.inf
View File

@ -1,42 +0,0 @@
#/** @file
# PCI Incompatible device support Library template.
#
# Check PCI incompatible devices and set necessary configuration.
# Copyright (c) 2007 - 2009, Intel Corporation.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = PciIncompatibleDeviceSupportLib
FILE_GUID = 1ca1c1f9-5baf-4204-b6e5-5e24109a4e4e
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = PciIncompatibleDeviceSupportLib|DXE_DRIVER UEFI_DRIVER
EFI_SPECIFICATION_VERSION = 0x00020000
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
#
[Sources.common]
IncompatiblePciDeviceList.h
PciIncompatibleDeviceSupportLib.c
[Packages]
MdePkg/MdePkg.dec
IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
[LibraryClasses]
MemoryAllocationLib
DebugLib