Add EnableCache() and DisableCache() implementations for IA32 and X64 to the BaseLib

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@6705 6f19259b-4bc3-4df7-8a09-765794883524

MdePkg/Library/BaseLib/BaseLib.inf

@@ -157,6 +157,8 @@
   Ia32/ARShiftU64.c | MSFT 
   Ia32/Thunk16.asm | MSFT
   Ia32/EnablePaging64.asm | MSFT
+  Ia32/EnableCache.c | MSFT
+  Ia32/DisableCache.c | MSFT
   SynchronizationMsc.c  | MSFT
 
   Ia32/Wbinvd.asm | INTEL 
@@ -253,6 +255,8 @@
   Ia32/ARShiftU64.asm | INTEL 
   Ia32/Thunk16.asm | INTEL
   Ia32/EnablePaging64.asm | INTEL
+  Ia32/EnableCache.asm | INTEL
+  Ia32/DisableCache.asm | INTEL
   Synchronization.c | INTEL
 
   Ia32/Thunk16.S | GCC 
@@ -349,6 +353,8 @@
   Ia32/ARShiftU64.S | GCC 
   Ia32/RShiftU64.S | GCC 
   Ia32/LShiftU64.S | GCC 
+  Ia32/EnableCache.S | GCC
+  Ia32/DisableCache.S | GCC
   SynchronizationGcc.c  | GCC
 
   Ia32/DivS64x64Remainder.c
@@ -448,6 +454,8 @@
   X64/SwitchStack.asm
   X64/InterlockedCompareExchange64.asm 
   X64/InterlockedCompareExchange32.asm 
+  X64/EnableCache.asm
+  X64/DisableCache.asm
 
   X64/InterlockedDecrement.c | MSFT 
   X64/InterlockedIncrement.c | MSFT 
@@ -563,6 +571,8 @@
   X64/CpuIdEx.S | GCC 
   X64/CpuBreakpoint.S | GCC 
   SynchronizationGcc.c  | GCC 
+  X64/EnableCache.S | GCC
+  X64/DisableCache.S | GCC
   ChkStkGcc.c  | GCC 
 
 [Sources.IPF]

MdePkg/Library/BaseLib/Ia32/DisableCache.S

@@ -0,0 +1,39 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2006 - 2008, Intel Corporation
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+# Module Name:
+#
+#   DisableCache.S
+#
+# Abstract:
+#
+#   Set the CD bit of CR0 to 1, clear the NW bit of CR0 to 0, and flush all caches with a
+#   WBINVD instruction.
+#
+# Notes:
+#
+#------------------------------------------------------------------------------
+
+#------------------------------------------------------------------------------
+# VOID
+# EFIAPI
+# AsmDisableCache (
+#   VOID
+#   );
+#------------------------------------------------------------------------------
+.globl ASM_PFX(AsmDisableCache)
+ASM_PFX(AsmDisableCache):
+    movl    %cr0, %eax
+    btsl    $30, %eax
+    btrl    $29, %eax
+    movl    %eax, %cr0
+    wbinvd
+    ret

MdePkg/Library/BaseLib/Ia32/DisableCache.asm

@@ -0,0 +1,45 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation
+; All rights reserved. This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+;   DisableCache.Asm
+;
+; Abstract:
+;
+;   Set the CD bit of CR0 to 1, clear the NW bit of CR0 to 0, and flush all caches with a
+;   WBINVD instruction.
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+    .386p
+    .model  flat,C
+    .code
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmDisableCache (
+;   VOID
+;   );
+;------------------------------------------------------------------------------
+AsmDisableCache PROC
+    mov     eax, cr0
+    bts     eax, 30
+    btr     eax, 29
+    mov     cr0, eax
+    wbinvd
+    ret
+AsmDisableCache ENDP
+
+    END

MdePkg/Library/BaseLib/Ia32/DisableCache.c

@@ -0,0 +1,36 @@
+/** @file
+  AsmDisableCache function
+
+  Copyright (c) 2006 - 2008, Intel Corporation<BR>
+  All rights reserved. This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+/**
+  Disables caches.
+
+  Set the CD bit of CR0 to 1, clear the NW bit of CR0 to 0, and flush all caches with a
+  WBINVD instruction.
+
+**/
+VOID
+EFIAPI
+AsmDisableCache (
+  VOID
+  )
+{
+  _asm {
+    mov     eax, cr0
+    bts     eax, 30
+    btr     eax, 29
+    mov     cr0, eax
+    wbinvd
+  }
+}
+

MdePkg/Library/BaseLib/Ia32/EnableCache.S

@@ -0,0 +1,39 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2006 - 2008, Intel Corporation
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+# Module Name:
+#
+#   EnableCache.S
+#
+# Abstract:
+#
+#   Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear 
+#   the NW bit of CR0 to 0
+#
+# Notes:
+#
+#------------------------------------------------------------------------------
+
+#------------------------------------------------------------------------------
+# VOID
+# EFIAPI
+# AsmEnableCache (
+#   VOID
+#   );
+#------------------------------------------------------------------------------
+.globl ASM_PFX(AsmEnableCache)
+ASM_PFX(AsmEnableCache):
+    wbinvd
+    movl    %cr0, %eax
+    btrl    $30, %eax
+    btrl    $29, %eax
+    movl    %eax, %cr0
+    ret

MdePkg/Library/BaseLib/Ia32/EnableCache.asm

@@ -0,0 +1,45 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation
+; All rights reserved. This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+;   EnableCache.Asm
+;
+; Abstract:
+;
+;  Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear 
+;  the NW bit of CR0 to 0
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+    .386p
+    .model  flat,C
+    .code
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmEnableCache (
+;   VOID
+;   );
+;------------------------------------------------------------------------------
+AsmEnableCache PROC
+    wbinvd
+    mov     eax, cr0
+    btr     eax, 29
+    btr     eax, 30
+    mov     cr0, eax
+    ret
+AsmEnableCache ENDP
+
+    END

MdePkg/Library/BaseLib/Ia32/EnableCache.c

@@ -0,0 +1,36 @@
+/** @file
+  AsmEnableCache function
+
+  Copyright (c) 2006 - 2008, Intel Corporation<BR>
+  All rights reserved. This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+/**
+  Enabled caches.
+
+  Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear 
+  the NW bit of CR0 to 0
+
+**/
+VOID
+EFIAPI
+AsmEnableCache (
+  VOID
+  )
+{
+  _asm {
+    wbinvd
+    mov     eax, cr0
+    btr     eax, 30
+    btr     eax, 29
+    mov     cr0, eax
+  }
+}
+

MdePkg/Library/BaseLib/X64/DisableCache.S

@@ -0,0 +1,39 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2006 - 2008, Intel Corporation
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+# Module Name:
+#
+#   DisableCache.S
+#
+# Abstract:
+#
+#   Set the CD bit of CR0 to 1, clear the NW bit of CR0 to 0, and flush all caches with a
+#   WBINVD instruction.
+#
+# Notes:
+#
+#------------------------------------------------------------------------------
+
+#------------------------------------------------------------------------------
+# VOID
+# EFIAPI
+# AsmDisableCache (
+#   VOID
+#   );
+#------------------------------------------------------------------------------
+.globl ASM_PFX(AsmDisableCache)
+ASM_PFX(AsmDisableCache):
+    movl    %cr0, %rax
+    btsl    $30, %rax
+    btrl    $29, %rax
+    movl    %rax, %cr0
+    wbinvd
+    ret

MdePkg/Library/BaseLib/X64/DisableCache.asm

@@ -0,0 +1,43 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation
+; All rights reserved. This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+;   DisableCache.Asm
+;
+; Abstract:
+;
+;   Set the CD bit of CR0 to 1, clear the NW bit of CR0 to 0, and flush all caches with a
+;   WBINVD instruction.
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+    .code
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmDisableCache (
+;   VOID
+;   );
+;------------------------------------------------------------------------------
+AsmDisableCache PROC
+    mov     rax, cr0
+    bts     rax, 30
+    btr     rax, 29
+    mov     cr0, rax
+    wbinvd
+    ret
+AsmDisableCache ENDP
+
+    END

MdePkg/Library/BaseLib/X64/EnableCache.S

@@ -0,0 +1,39 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2006 - 2008, Intel Corporation
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+# Module Name:
+#
+#   EnableCache.S
+#
+# Abstract:
+#
+#   Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear 
+#   the NW bit of CR0 to 0
+#
+# Notes:
+#
+#------------------------------------------------------------------------------
+
+#------------------------------------------------------------------------------
+# VOID
+# EFIAPI
+# AsmEnableCache (
+#   VOID
+#   );
+#------------------------------------------------------------------------------
+.globl ASM_PFX(AsmEnableCache)
+ASM_PFX(AsmEnableCache):
+    wbinvd
+    movl    %cr0, %rax
+    btrl    $30, %rax
+    btrl    $29, %rax
+    movl    %rax, %cr0
+    ret

MdePkg/Library/BaseLib/X64/EnableCache.asm

@@ -0,0 +1,43 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation
+; All rights reserved. This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+;   EnableCache.Asm
+;
+; Abstract:
+;
+;  Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear 
+;  the NW bit of CR0 to 0
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+    .code
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmEnableCache (
+;   VOID
+;   );
+;------------------------------------------------------------------------------
+AsmEnableCache PROC
+    wbinvd
+    mov     rax, cr0
+    btr     rax, 29
+    btr     rax, 30
+    mov     cr0, rax
+    ret
+AsmEnableCache ENDP
+
+    END