Clean up code.

Contributed-under: TianoCore Contribution Agreement 1.0

Signed off by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed by: Eric Dong <eric.dong@intel.com>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15743 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
jyao1
2014-08-04 06:34:41 +00:00
committed by jyao1
parent 4e07e87fe4
commit a0e0fb6d9f
5 changed files with 15 additions and 4 deletions

View File

@ -41,6 +41,7 @@ UINT64 mIdtEntryTemplate = 0xffff8e000008ffe4ULL;
@param[in] SizeOfRam Size of the temporary memory available for use.
@param[in] TempRamBase Base address of tempory ram
@param[in] BootFirmwareVolume Base address of the Boot Firmware Volume.
@param[in] PeiCoreEntry Pei Core entrypoint.
@return This function never returns.
@ -50,7 +51,8 @@ EFIAPI
SecStartup (
IN UINT32 SizeOfRam,
IN UINT32 TempRamBase,
IN VOID *BootFirmwareVolume
IN VOID *BootFirmwareVolume,
IN UINTN PeiCoreEntry
)
{
EFI_SEC_PEI_HAND_OFF SecCoreData;
@ -119,7 +121,7 @@ SecStartup (
//
// Call PeiCore Entry
//
PeiCore = (PEI_CORE_ENTRY)(*(UINTN *)((&BootFirmwareVolume) + 1));
PeiCore = (PEI_CORE_ENTRY)(PeiCoreEntry);
PeiCore (&SecCoreData, mPeiSecPlatformInformationPpi);
//

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@ -107,6 +107,7 @@ InitializeFloatingPointUnits (
@param[in] SizeOfRam Size of the temporary memory available for use.
@param[in] TempRamBase Base address of tempory ram
@param[in] BootFirmwareVolume Base address of the Boot Firmware Volume.
@param[in] PeiCoreEntry Pei Core entrypoint.
@return This function never returns.
@ -116,7 +117,8 @@ EFIAPI
SecStartup (
IN UINT32 SizeOfRam,
IN UINT32 TempRamBase,
IN VOID *BootFirmwareVolume
IN VOID *BootFirmwareVolume,
IN UINTN PeiCoreEntry
);
/**

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@ -244,6 +244,8 @@ FspHobProcess (
LowMemorySize
);
S3PeiMemBase = 0;
S3PeiMemSize = 0;
Status = GetS3MemoryInfo (&S3PeiMemBase, &S3PeiMemSize);
ASSERT_EFI_ERROR (Status);
DEBUG((DEBUG_INFO, "S3 memory %Xh - %Xh bytes\n", S3PeiMemBase, S3PeiMemSize));

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@ -12,6 +12,9 @@
**/
#ifndef __FSP_H__
#define __FSP_H__
//
// Fv Header
//
@ -41,3 +44,5 @@
//
#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C
#define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30
#endif

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@ -52,7 +52,7 @@
Ia32/PeiCoreEntry.asm
Ia32/AsmSaveSecContext.asm
Ia32/Stack.asm
Ia32/Fsp.h
Ia32/SecEntry.S
Ia32/PeiCoreEntry.S
Ia32/AsmSaveSecContext.S