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1. refine the comments

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2. use BITx

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@6695 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
vanjeff
2008-11-24 06:42:33 +00:00
parent 3745e1a61e
commit a2461f6bc7
8 changed files with 148 additions and 147 deletions
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27
MdePkg/Include/IndustryStandard/Pci22.h
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@@ -123,9 +123,9 @@ typedef struct {
UINT16 BridgeControl; ///< Bridge Control
} PCI_CARDBUS_CONTROL_REGISTER;
///
/// Definitions of PCI class bytes and manipulation macros.
///
//
// Definitions of PCI class bytes and manipulation macros.
//
#define PCI_CLASS_OLD 0x00
#define PCI_CLASS_OLD_OTHER 0x00
#define PCI_CLASS_OLD_VGA 0x01
@@ -350,9 +350,9 @@ typedef struct {
#define PCI_MAXGNT_OFFSET 0x3E ///< Max Grant Register
#define PCI_MAXLAT_OFFSET 0x3F ///< Max Latency Register
///
/// defined in PCI-to-PCI Bridge Architecture Specification
///
//
// defined in PCI-to-PCI Bridge Architecture Specification
//
#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18
#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19
#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a
@@ -389,9 +389,9 @@ typedef union {
#define EFI_PCI_COMMAND_SERR BIT8 ///< 0x0100
#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200
///
/// defined in PCI-to-PCI Bridge Architecture Specification
///
//
// defined in PCI-to-PCI Bridge Architecture Specification
//
#define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE BIT0 ///< 0x0001
#define EFI_PCI_BRIDGE_CONTROL_SERR BIT1 ///< 0x0002
#define EFI_PCI_BRIDGE_CONTROL_ISA BIT2 ///< 0x0004
@@ -405,9 +405,9 @@ typedef union {
#define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS BIT10 ///< 0x0400
#define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR BIT11 ///< 0x0800
///
/// Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard
///
//
// Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard
//
#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7 ///< 0x0080
#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8 ///< 0x0100
#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200
@@ -436,6 +436,7 @@ typedef union {
#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04
#define EFI_PCI_CAPABILITY_ID_MSI 0x05
#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
typedef struct {
UINT8 CapabilityID;
UINT8 NextItemPtr;
@@ -543,7 +544,7 @@ typedef struct {
#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55
#define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R')
#define PCI_CODE_TYPE_PCAT_IMAGE 0x00
#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///<defined in UEFI spec.
#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///< defined in UEFI spec.
typedef struct {
UINT16 Signature; ///< 0xaa55