diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index 431ec7fc6e..aa7e23c048 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -221,6 +221,7 @@
   Ia32/SetJump.asm | INTEL 
   Ia32/RRotU64.nasm| INTEL
   Ia32/RRotU64.asm | INTEL 
+  Ia32/RShiftU64.nasm| INTEL
   Ia32/RShiftU64.asm | INTEL 
   Ia32/ReadPmc.asm | INTEL 
   Ia32/ReadTsc.asm | INTEL 
@@ -319,6 +320,7 @@
   Ia32/RRotU64.S | GCC 
   Ia32/LRotU64.S | GCC 
   Ia32/ARShiftU64.S | GCC 
+  Ia32/RShiftU64.nasm| GCC
   Ia32/RShiftU64.S | GCC 
   Ia32/LShiftU64.S | GCC 
   Ia32/EnableCache.S | GCC
diff --git a/MdePkg/Library/BaseLib/Ia32/RShiftU64.nasm b/MdePkg/Library/BaseLib/Ia32/RShiftU64.nasm
new file mode 100644
index 0000000000..7203ddbb11
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Ia32/RShiftU64.nasm
@@ -0,0 +1,45 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+;   RShiftU64.nasm
+;
+; Abstract:
+;
+;   64-bit logical right shift function for IA-32
+;
+;------------------------------------------------------------------------------
+
+    SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; InternalMathRShiftU64 (
+;   IN      UINT64                    Operand,
+;   IN      UINTN                     Count
+;   );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalMathRShiftU64)
+ASM_PFX(InternalMathRShiftU64):
+    mov     cl, [esp + 12]              ; cl <- Count
+    xor     edx, edx
+    mov     eax, [esp + 8]
+    test    cl, 32                      ; Count >= 32?
+    jnz     .0
+    mov     edx, eax
+    mov     eax, [esp + 4]
+.0:
+    shrd    eax, edx, cl
+    shr     edx, cl
+    ret
+