Add IntelFspWrapper to support boot EDKII on FSP bin.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed off by: Jiewen Yao <jiewen.yao@intel.com> Reviewed by: Ravi Rangarajan <ravi.p.rangarajan@intel.com> Reviewed by: Maurice Ma <maurice.ma@intel.com> Reviewed by: Giri Mudusuru <giri.p.mudusuru@intel.com> Reviewed by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15676 6f19259b-4bc3-4df7-8a09-765794883524
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105
IntelFspPkg/Include/FspInfoHeader.h
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105
IntelFspPkg/Include/FspInfoHeader.h
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/** @file
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Intel FSP Info Header definition from Intel Firmware Support Package External
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Architecture Specification, April 2014, revision 001.
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Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _FSP_INFO_HEADER_H_
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#define _FSP_INFO_HEADER_H_
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///
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/// Fixed FSP header offset in the FSP image
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///
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#define FSP_INFO_HEADER_OFF 0x94
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#define OFFSET_IN_FSP_INFO_HEADER(x) (UINT32)&((FSP_INFO_HEADER *)(UINTN)0)->x
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#pragma pack(1)
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typedef struct {
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///
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/// Signature ('FSPH') for the FSP Information Header
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///
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UINT32 Signature;
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///
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/// Length of the FSP Information Header
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///
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UINT32 HeaderLength;
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///
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/// Reserved
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///
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UINT8 Reserved1[3];
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///
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/// Revision of the FSP Information Header
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///
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UINT8 HeaderRevision;
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///
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/// Revision of the FSP binary
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///
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UINT32 ImageRevision;
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///
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/// Signature string that will help match the FSP Binary to a supported
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/// hardware configuration.
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///
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CHAR8 ImageId[8];
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///
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/// Size of the entire FSP binary
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///
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UINT32 ImageSize;
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///
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/// FSP binary preferred base address
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///
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UINT32 ImageBase;
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///
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/// Attribute for the FSP binary
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///
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UINT32 ImageAttribute;
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///
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/// Offset of the FSP configuration region
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///
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UINT32 CfgRegionOffset;
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///
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/// Size of the FSP configuration region
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///
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UINT32 CfgRegionSize;
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///
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/// Number of API entries this FSP supports
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///
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UINT32 ApiEntryNum;
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///
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/// TempRamInit API entry offset
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///
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UINT32 TempRamInitEntryOffset;
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///
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/// FspInit API entry offset
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///
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UINT32 FspInitEntryOffset;
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///
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/// NotifyPhase API entry offset
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///
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UINT32 NotifyPhaseEntryOffset;
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///
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/// Reserved
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///
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UINT32 Reserved2;
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} FSP_INFO_HEADER;
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#pragma pack()
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#endif
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