MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
Some SD Host Controllers use different values in Host Control 2 Register to select UHS Mode. This patch adds a new UhsSignaling type routine to the NotifyPhase of the SdMmcOverride protocol. UHS signaling configuration is moved to a common, default routine (SdMmcHcUhsSignaling). After it is executed, the protocol producer can override the values if needed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
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@@ -740,10 +740,13 @@ EmmcSwitchToHighSpeed (
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IN UINT8 BusWidth
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)
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{
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EFI_STATUS Status;
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UINT8 HsTiming;
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UINT8 HostCtrl1;
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UINT8 HostCtrl2;
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EFI_STATUS Status;
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UINT8 HsTiming;
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UINT8 HostCtrl1;
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SD_MMC_BUS_MODE Timing;
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SD_MMC_HC_PRIVATE_DATA *Private;
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Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
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Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, IsDdr, BusWidth);
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if (EFI_ERROR (Status)) {
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@@ -758,25 +761,15 @@ EmmcSwitchToHighSpeed (
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return Status;
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}
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//
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// Clean UHS Mode Select field of Host Control 2 reigster before update
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//
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HostCtrl2 = (UINT8)~0x7;
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Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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//
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// Set UHS Mode Select field of Host Control 2 reigster to SDR12/25/50
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//
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if (IsDdr) {
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HostCtrl2 = BIT2;
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Timing = SdMmcMmcHsDdr;
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} else if (ClockFreq == 52) {
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HostCtrl2 = BIT0;
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Timing = SdMmcMmcHsSdr;
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} else {
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HostCtrl2 = 0;
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Timing = SdMmcMmcLegacy;
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}
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Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
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Status = SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, Timing);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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@@ -814,10 +807,13 @@ EmmcSwitchToHS200 (
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IN UINT8 BusWidth
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)
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{
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EFI_STATUS Status;
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UINT8 HsTiming;
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UINT8 HostCtrl2;
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UINT16 ClockCtrl;
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EFI_STATUS Status;
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UINT8 HsTiming;
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UINT16 ClockCtrl;
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SD_MMC_BUS_MODE Timing;
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SD_MMC_HC_PRIVATE_DATA *Private;
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Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
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if ((BusWidth != 4) && (BusWidth != 8)) {
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return EFI_INVALID_PARAMETER;
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@@ -837,22 +833,14 @@ EmmcSwitchToHS200 (
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if (EFI_ERROR (Status)) {
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return Status;
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}
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//
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// Clean UHS Mode Select field of Host Control 2 reigster before update
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//
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HostCtrl2 = (UINT8)~0x7;
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Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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//
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// Set UHS Mode Select field of Host Control 2 reigster to SDR104
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//
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HostCtrl2 = BIT0 | BIT1;
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Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
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Timing = SdMmcMmcHs200;
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Status = SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, Timing);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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//
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// Wait Internal Clock Stable in the Clock Control register to be 1 before set SD Clock Enable bit
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//
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@@ -910,9 +898,12 @@ EmmcSwitchToHS400 (
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IN UINT32 ClockFreq
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)
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{
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EFI_STATUS Status;
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UINT8 HsTiming;
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UINT8 HostCtrl2;
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EFI_STATUS Status;
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UINT8 HsTiming;
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SD_MMC_BUS_MODE Timing;
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SD_MMC_HC_PRIVATE_DATA *Private;
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Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
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Status = EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, ClockFreq, 8);
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if (EFI_ERROR (Status)) {
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@@ -933,19 +924,10 @@ EmmcSwitchToHS400 (
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if (EFI_ERROR (Status)) {
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return Status;
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}
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//
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// Clean UHS Mode Select field of Host Control 2 reigster before update
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//
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HostCtrl2 = (UINT8)~0x7;
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Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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//
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// Set UHS Mode Select field of Host Control 2 reigster to HS400
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//
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HostCtrl2 = BIT0 | BIT2;
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Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
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Timing = SdMmcMmcHs400;
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Status = SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, Timing);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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