MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
Some SD Host Controllers use different values in Host Control 2 Register to select UHS Mode. This patch adds a new UhsSignaling type routine to the NotifyPhase of the SdMmcOverride protocol. UHS signaling configuration is moved to a common, default routine (SdMmcHcUhsSignaling). After it is executed, the protocol producer can override the values if needed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
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@@ -784,8 +784,8 @@ SdCardSetBusMode (
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UINT8 BusWidth;
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UINT8 AccessMode;
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UINT8 HostCtrl1;
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UINT8 HostCtrl2;
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UINT8 SwitchResp[64];
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SD_MMC_BUS_MODE Timing;
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SD_MMC_HC_PRIVATE_DATA *Private;
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Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
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@@ -817,18 +817,23 @@ SdCardSetBusMode (
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if (S18A && (Capability->Sdr104 != 0) && ((SwitchResp[13] & BIT3) != 0)) {
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ClockFreq = 208;
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AccessMode = 3;
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Timing = SdMmcUhsSdr104;
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} else if (S18A && (Capability->Sdr50 != 0) && ((SwitchResp[13] & BIT2) != 0)) {
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ClockFreq = 100;
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AccessMode = 2;
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Timing = SdMmcUhsSdr50;
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} else if (S18A && (Capability->Ddr50 != 0) && ((SwitchResp[13] & BIT4) != 0)) {
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ClockFreq = 50;
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AccessMode = 4;
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Timing = SdMmcUhsDdr50;
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} else if ((SwitchResp[13] & BIT1) != 0) {
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ClockFreq = 50;
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AccessMode = 1;
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Timing = SdMmcUhsSdr25;
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} else {
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ClockFreq = 25;
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AccessMode = 0;
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Timing = SdMmcUhsSdr12;
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}
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Status = SdCardSwitch (PassThru, Slot, AccessMode, 0xF, 0xF, 0xF, TRUE, SwitchResp);
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@@ -854,13 +859,7 @@ SdCardSetBusMode (
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}
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}
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HostCtrl2 = (UINT8)~0x7;
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Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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HostCtrl2 = AccessMode;
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Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
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Status = SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, Timing);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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