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MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol

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Some SD Host Controllers use different values in Host Control 2 Register
to select UHS Mode. This patch adds a new UhsSignaling type routine to
the NotifyPhase of the SdMmcOverride protocol.

UHS signaling configuration is moved to a common, default routine
(SdMmcHcUhsSignaling). After it is executed, the protocol producer
can override the values if needed.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
This commit is contained in:
Tomasz Michalec
2018-11-10 07:01:25 +08:00
committed by Hao Wu
parent 49c9953425
commit a4708009cc
5 changed files with 181 additions and 60 deletions
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34
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
View File

@@ -62,6 +62,21 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#define SD_MMC_HC_SLOT_INT_STS 0xFC
#define SD_MMC_HC_CTRL_VER 0xFE
//
// SD Host Controller bits to HOST_CTRL2 register
//
#define SD_MMC_HC_CTRL_UHS_MASK 0x0007
#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000
#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001
#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002
#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003
#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004
#define SD_MMC_HC_CTRL_MMC_LEGACY 0x0000
#define SD_MMC_HC_CTRL_MMC_HS_SDR 0x0001
#define SD_MMC_HC_CTRL_MMC_HS_DDR 0x0004
#define SD_MMC_HC_CTRL_MMC_HS200 0x0003
#define SD_MMC_HC_CTRL_MMC_HS400 0x0005
//
// The transfer modes supported by SD Host Controller
// Simplified Spec 3.0 Table 1-2
@@ -518,4 +533,23 @@ SdMmcHcInitTimeoutCtrl (
IN UINT8 Slot
);
/**
Set SD Host Controller control 2 registry according to selected speed.
@param[in] ControllerHandle The handle of the controller.
@param[in] PciIo The PCI IO protocol instance.
@param[in] Slot The slot number of the SD card to send the command to.
@param[in] Timing The timing to select.
@retval EFI_SUCCESS The timing is set successfully.
@retval Others The timing isn't set successfully.
**/
EFI_STATUS
SdMmcHcUhsSignaling (
IN EFI_HANDLE ControllerHandle,
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot,
IN SD_MMC_BUS_MODE Timing
);
#endif