Add CPU DXE driver for IA32 & X64 processor architectures.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@8395 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
jljusten
363
UefiCpuPkg/CpuDxe/X64/CpuAsm.S
Executable file
363
UefiCpuPkg/CpuDxe/X64/CpuAsm.S
Executable file
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# TITLE CpuAsm.asm:
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#------------------------------------------------------------------------------
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#*
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#* Copyright 2008 - 2009, Intel Corporation
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#* All rights reserved. This program and the accompanying materials
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#* are licensed and made available under the terms and conditions of the BSD License
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#* which accompanies this distribution. The full text of the license may be found at
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#* http://opensource.org/licenses/bsd-license.php
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#*
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#* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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#* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#*
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#* CpuAsm.S
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#*
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#* Abstract:
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#*
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#------------------------------------------------------------------------------
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#text SEGMENT
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#EXTRN ASM_PFX(mErrorCodeFlag):DWORD # Error code flags for exceptions
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#
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# point to the external interrupt vector table
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#
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ExternalVectorTablePtr:
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.byte 0, 0, 0, 0, 0, 0, 0, 0
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.intel_syntax
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ASM_GLOBAL ASM_PFX(InitializeExternalVectorTablePtr)
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ASM_PFX(InitializeExternalVectorTablePtr):
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lea %rax, [%rip+ExternalVectorTablePtr] # save vector number
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mov [%rax], %rcx
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ret
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#------------------------------------------------------------------------------
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# VOID
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# SetCodeSelector (
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# UINT16 Selector
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# );
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#------------------------------------------------------------------------------
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.intel_syntax
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ASM_GLOBAL ASM_PFX(SetCodeSelector)
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ASM_PFX(SetCodeSelector):
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sub %rsp, 0x10
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lea %rax, [%rip+setCodeSelectorLongJump]
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mov [%rsp], %rax
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mov [%rsp+4], %cx
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jmp fword ptr [%rsp]
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setCodeSelectorLongJump:
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add %rsp, 0x10
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ret
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#------------------------------------------------------------------------------
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# VOID
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# SetDataSelectors (
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# UINT16 Selector
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# );
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#------------------------------------------------------------------------------
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.intel_syntax
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ASM_GLOBAL ASM_PFX(SetDataSelectors)
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ASM_PFX(SetDataSelectors):
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mov %ss, %cx
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mov %ds, %cx
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mov %es, %cx
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mov %fs, %cx
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mov %gs, %cx
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ret
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#---------------------------------------;
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# CommonInterruptEntry ;
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#---------------------------------------;
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# The follow algorithm is used for the common interrupt routine.
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.intel_syntax
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ASM_GLOBAL ASM_PFX(CommonInterruptEntry)
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ASM_PFX(CommonInterruptEntry):
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cli
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#
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# All interrupt handlers are invoked through interrupt gates, so
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# IF flag automatically cleared at the entry point
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#
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#
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# Calculate vector number
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#
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xchg %rcx, [%rsp] # get the return address of call, actually, it is the address of vector number.
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movzx %ecx, word ptr [%rcx]
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cmp %ecx, 32 # Intel reserved vector for exceptions?
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jae NoErrorCode
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push %rax
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lea %rax, [%rip+ASM_PFX(mErrorCodeFlag)]
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bt dword ptr [%rax], %ecx
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pop %rax
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jc CommonInterruptEntry_al_0000
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NoErrorCode:
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#
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# Push a dummy error code on the stack
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# to maintain coherent stack map
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#
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push [%rsp]
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mov qword ptr [%rsp + 8], 0
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CommonInterruptEntry_al_0000:
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push %rbp
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mov %rbp, %rsp
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#
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# Stack:
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# +---------------------+ <-- 16-byte aligned ensured by processor
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# + Old SS +
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# +---------------------+
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# + Old RSP +
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# +---------------------+
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# + RFlags +
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# +---------------------+
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# + CS +
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# +---------------------+
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# + RIP +
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# +---------------------+
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# + Error Code +
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# +---------------------+
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# + RCX / Vector Number +
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# +---------------------+
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# + RBP +
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# +---------------------+ <-- RBP, 16-byte aligned
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#
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#
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# Since here the stack pointer is 16-byte aligned, so
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# EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
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# is 16-byte aligned
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#
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#; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
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#; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
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push %r15
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push %r14
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push %r13
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push %r12
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push %r11
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push %r10
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push %r9
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push %r8
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push %rax
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push qword ptr [%rbp + 8] # RCX
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push %rdx
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push %rbx
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push qword ptr [%rbp + 48] # RSP
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push qword ptr [%rbp] # RBP
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push %rsi
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push %rdi
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#; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
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movzx %rax, word ptr [%rbp + 56]
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push %rax # for ss
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movzx %rax, word ptr [%rbp + 32]
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push %rax # for cs
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mov %rax, %ds
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push %rax
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mov %rax, %es
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push %rax
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mov %rax, %fs
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push %rax
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mov %rax, %gs
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push %rax
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mov [%rbp + 8], %rcx # save vector number
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#; UINT64 Rip;
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push qword ptr [%rbp + 24]
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#; UINT64 Gdtr[2], Idtr[2];
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xor %rax, %rax
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push %rax
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push %rax
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sidt [%rsp]
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xchg %rax, [%rsp + 2]
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xchg %rax, [%rsp]
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xchg %rax, [%rsp + 8]
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xor %rax, %rax
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push %rax
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push %rax
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sgdt [%rsp]
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xchg %rax, [%rsp + 2]
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xchg %rax, [%rsp]
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xchg %rax, [%rsp + 8]
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#; UINT64 Ldtr, Tr;
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xor %rax, %rax
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str %ax
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push %rax
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sldt %ax
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push %rax
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#; UINT64 RFlags;
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push qword ptr [%rbp + 40]
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#; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
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mov %rax, %cr8
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push %rax
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mov %rax, %cr4
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or %rax, 0x208
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mov %cr4, %rax
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push %rax
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mov %rax, %cr3
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push %rax
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mov %rax, %cr2
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push %rax
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xor %rax, %rax
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push %rax
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mov %rax, %cr0
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push %rax
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#; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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mov %rax, %dr7
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push %rax
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#; clear Dr7 while executing debugger itself
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xor %rax, %rax
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mov %dr7, %rax
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mov %rax, %dr6
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push %rax
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#; insure all status bits in dr6 are clear...
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xor %rax, %rax
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mov %dr6, %rax
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mov %rax, %dr3
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push %rax
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mov %rax, %dr2
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push %rax
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mov %rax, %dr1
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push %rax
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mov %rax, %dr0
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push %rax
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#; FX_SAVE_STATE_X64 FxSaveState;
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sub %rsp, 512
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mov %rdi, %rsp
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.byte 0x0f, 0x0ae, 0x07 #fxsave [rdi]
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#; UINT32 ExceptionData;
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push qword ptr [%rbp + 16]
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#; call into exception handler
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mov %rcx, [%rbp + 8]
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lea %rax, [%rip+ExternalVectorTablePtr]
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mov %eax, [%eax]
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mov %rax, [%rax + %rcx * 8]
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or %rax, %rax # NULL?
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je nonNullValue#
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#; Prepare parameter and call
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# mov rcx, [rbp + 8]
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mov %rdx, %rsp
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#
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# Per X64 calling convention, allocate maximum parameter stack space
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# and make sure RSP is 16-byte aligned
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#
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sub %rsp, 4 * 8 + 8
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call %rax
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add %rsp, 4 * 8 + 8
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nonNullValue:
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cli
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#; UINT64 ExceptionData;
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add %rsp, 8
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#; FX_SAVE_STATE_X64 FxSaveState;
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mov %rsi, %rsp
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.byte 0x0f, 0x0ae, 0x0E # fxrstor [rsi]
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add %rsp, 512
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#; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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pop %rax
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mov %dr0, %rax
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pop %rax
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mov %dr1, %rax
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pop %rax
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mov %dr2, %rax
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pop %rax
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mov %dr3, %rax
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#; skip restore of dr6. We cleared dr6 during the context save.
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add %rsp, 8
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pop %rax
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mov %dr7, %rax
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#; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
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pop %rax
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mov %cr0, %rax
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add %rsp, 8 # not for Cr1
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pop %rax
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mov %cr2, %rax
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pop %rax
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mov %cr3, %rax
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pop %rax
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mov %cr4, %rax
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pop %rax
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mov %cr8, %rax
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#; UINT64 RFlags;
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pop qword ptr [%rbp + 40]
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#; UINT64 Ldtr, Tr;
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#; UINT64 Gdtr[2], Idtr[2];
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#; Best not let anyone mess with these particular registers...
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add %rsp, 48
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#; UINT64 Rip;
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pop qword ptr [%rbp + 24]
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#; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
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pop %rax
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# mov gs, rax ; not for gs
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pop %rax
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# mov fs, rax ; not for fs
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# (X64 will not use fs and gs, so we do not restore it)
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pop %rax
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mov %es, %rax
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pop %rax
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mov %ds, %rax
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pop qword ptr [%rbp + 32] # for cs
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pop qword ptr [%rbp + 56] # for ss
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#; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
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#; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
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pop %rdi
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pop %rsi
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add %rsp, 8 # not for rbp
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pop qword ptr [%rbp + 48] # for rsp
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pop %rbx
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pop %rdx
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pop %rcx
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pop %rax
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pop %r8
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pop %r9
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pop %r10
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pop %r11
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pop %r12
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pop %r13
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pop %r14
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pop %r15
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mov %rsp, %rbp
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pop %rbp
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add %rsp, 16
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iretq
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#text ENDS
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#END
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