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MdeModulePkg/XhciDxe: Event Ring traverse algorithm enhancement to avoid that those completed async transfer events don't get handled in time and are flushed by newer coming events.

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Signed-off-by: erictian
Reviewed-by: li-elvin


git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13145 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
erictian
2012-03-27 12:07:38 +00:00
parent ecc722ad41
commit a50f7c4c09
7 changed files with 2346 additions and 2287 deletions
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11
MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
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@@ -2,7 +2,7 @@
This file contains the register definition of XHCI host controller.
Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2011 - 2012, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -172,6 +172,15 @@ typedef union {
#define XHC_PORTSC_CEC BIT23 // Port Config Error Change
#define XHC_PORTSC_CAS BIT24 // Cold Attach Status
#define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status
#define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled
#define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active
#define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset
#define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power
#define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change
#define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change
#define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change
#define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change
#define XHC_IMAN_IP BIT0 // Interrupt Pending
#define XHC_IMAN_IE BIT1 // Interrupt Enable