MdeModulePkg: Add PciSioSerialDxe driver
PciSioSerialDxe driver can manages UARTs on a SIO chip or a PCI/PCIE card. It manages the SIO instance whose last device path node is a ACPI device path and the HID in the ACPI device path node equals to EISA_PNP_ID (0x501). It also manages the PCI IO instance whose class code is 7/0/2 (16550 UART). But when proper value is set to PcdPciSerialParameters, the driver can also manage non-standard PCI serial cards by matching the Vendor ID and Device ID specified in PcdPciSerialParameters. The PCI BAR index, IO/MMIO offset, register stride, clock rate can also be specified through the same PCD. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19179 6f19259b-4bc3-4df7-8a09-765794883524
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@@ -686,6 +686,12 @@
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# @Prompt Enable S3 performance data support.
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gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwarePerformanceDataTableS3Support|TRUE|BOOLEAN|0x00010064
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## Indicates if Serial device uses half hand shake.<BR><BR>
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# TRUE - Serial device uses half hand shake.<BR>
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# FALSE - Serial device doesn't use half hand shake.<BR>
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# @Prompt Enable Serial device Half Hand Shake
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gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHalfHandshake|FALSE|BOOLEAN|0x00010073
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[PcdsFeatureFlag.IA32, PcdsFeatureFlag.X64]
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## Indicates if DxeIpl should switch to long mode to enter DXE phase.
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# It is assumed that 64-bit DxeCore is built in firmware if it is true; otherwise 32-bit DxeCore
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@@ -971,6 +977,38 @@
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# @Prompt Pci Serial Device Info
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gEfiMdeModulePkgTokenSpaceGuid.PcdSerialPciDeviceInfo|{0xFF}|VOID*|0x00010067
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## PCI Serial Parameters. It is an array of VendorID, DeviceID, ClockRate, Offset,
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# BarIndex, RegisterStride, ReceiveFifoDepth, TransmitFifoDepth information that
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# describes the parameters of special PCI serial devices.
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# Each array entry is 24-byte in length. The array is terminated
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# by an array entry with a PCI Vendor ID of 0xFFFF. If a platform only contains a
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# standard 16550 PCI serial device whose class code is 7/0/2, the value is 0xFFFF.
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# The C style structure is defined as below:
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# typedef struct {
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# UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.
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# UINT16 DeviceId; ///< Device ID to match the PCI device
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# UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz
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# UINT64 Offset; ///< The byte offset into to the BAR
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# UINT8 BarIndex; ///< Which BAR to get the UART base address
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# UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.
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# UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
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# UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
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# UINT8 Reserved[2];
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# } PCI_SERIAL_PARAMETER;
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# It contains zero or more instances of the above structure.
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# For example, if a PCI device contains two UARTs, PcdPciSerialParameters needs
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# to contain two instances of the above structure, with the VendorId and DeviceId
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# equals to the Device ID and Vendor ID of the device; If the PCI device uses the
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# first two BARs to support two UARTs, BarIndex of first instance equals to 0 and
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# BarIndex of second one equals to 1; If the PCI device uses the first BAR to
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# support both UARTs, BarIndex of both instance equals to 0, Offset of first
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# instance equals to 0 and Offset of second one equals to a value bigger than or
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# equal to 8.
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# For certain UART whose register needs to be accessed in DWORD aligned address,
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# RegisterStride equals to 4.
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# @Prompt Pci Serial Parameters
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gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters|{0xFF, 0xFF}|VOID*|0x00010071
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## Serial Port Extended Transmit FIFO Size. The default is 64 bytes.
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# @Prompt Serial Port Extended Transmit FIFO Size in Bytes
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gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|64|UINT32|0x00010068
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