UefiCpuPkg/LocalApic.h: Remove duplicated/conflicted definitions
#define MSR_IA32_APIC_BASE_ADDRESS is duplicated with #define MSR_IA32_APIC_BASE defined in UefiCpuPkg/Include/Register/ArchitecturalMsr.h, so we could remove it and update the modules to use MSR_IA32_APIC_BASE from ArchitecturalMsr.h. Structure MSR_IA32_APIC_BASE conflicts with #define MSR_IA32_APIC_BASE defined in UefiCpuPkg/Include/Register/ArchitecturalMsr.h, so we could remove it and update the modules to use structure MSR_IA32_APIC_BASE_REGISTER from ArchitecturalMsr.h. v5: 1. Update SourceLevelDebugPkg to use APIC Base MSR from ArchitecturalMsr.h. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com>
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@@ -1,7 +1,7 @@
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/** @file
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IA32 Local APIC Definitions.
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Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@@ -15,11 +15,6 @@
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#ifndef __LOCAL_APIC_H__
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#define __LOCAL_APIC_H__
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//
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// Definitions for IA32 architectural MSRs
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//
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#define MSR_IA32_APIC_BASE_ADDRESS 0x1B
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//
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// Definition for Local APIC registers and related values
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//
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@@ -53,19 +48,6 @@
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#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2
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#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3
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typedef union {
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struct {
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UINT32 Reserved0:8; ///< Reserved.
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UINT32 Bsp:1; ///< Processor is BSP.
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UINT32 Reserved1:1; ///< Reserved.
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UINT32 Extd:1; ///< Enable x2APIC mode.
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UINT32 En:1; ///< xAPIC global enable/disable.
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UINT32 ApicBaseLow:20; ///< APIC Base physical address. The actual field width depends on physical address width.
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UINT32 ApicBaseHigh:32;
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} Bits;
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UINT64 Uint64;
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} MSR_IA32_APIC_BASE;
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//
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// Local APIC Version Register.
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//
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