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UefiCpuPkg/LocalApic.h: Remove duplicated/conflicted definitions

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#define MSR_IA32_APIC_BASE_ADDRESS is duplicated with #define MSR_IA32_APIC_BASE
defined in UefiCpuPkg/Include/Register/ArchitecturalMsr.h, so we could remove it
and update the modules to use MSR_IA32_APIC_BASE from ArchitecturalMsr.h.

Structure MSR_IA32_APIC_BASE conflicts with #define MSR_IA32_APIC_BASE defined
in UefiCpuPkg/Include/Register/ArchitecturalMsr.h, so we could remove it and
update the modules to use structure MSR_IA32_APIC_BASE_REGISTER from
ArchitecturalMsr.h.

v5:
  1. Update SourceLevelDebugPkg to use APIC Base MSR from ArchitecturalMsr.h.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
This commit is contained in:
Jeff Fan
2016-07-20 22:11:47 +08:00
parent 584fcb7de2
commit a742e1865d
7 changed files with 60 additions and 71 deletions
Download Patch File Download Diff File Expand all files Collapse all files

29
UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
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@@ -3,7 +3,7 @@
This local APIC library instance supports xAPIC mode only.
Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -15,6 +15,7 @@
**/
#include <Register/Cpuid.h>
#include <Register/Msr.h>
#include <Register/LocalApic.h>
#include <Library/BaseLib.h>
@@ -67,7 +68,7 @@ GetLocalApicBaseAddress (
VOID
)
{
MSR_IA32_APIC_BASE ApicBaseMsr;
MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
if (!LocalApicBaseAddressMsrSupported ()) {
//
@@ -77,10 +78,10 @@ GetLocalApicBaseAddress (
return PcdGet32 (PcdCpuLocalApicBaseAddress);
}
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32)) +
(((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12);
return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +
(((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
}
/**
@@ -97,7 +98,7 @@ SetLocalApicBaseAddress (
IN UINTN BaseAddress
)
{
MSR_IA32_APIC_BASE ApicBaseMsr;
MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);
@@ -108,12 +109,12 @@ SetLocalApicBaseAddress (
return;
}
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
ApicBaseMsr.Bits.ApicBaseLow = (UINT32) (BaseAddress >> 12);
ApicBaseMsr.Bits.ApicBaseHigh = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));
ApicBaseMsr.Bits.ApicBase = (UINT32) (BaseAddress >> 12);
ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));
AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
}
/**
@@ -246,18 +247,18 @@ GetApicMode (
{
DEBUG_CODE (
{
MSR_IA32_APIC_BASE ApicBaseMsr;
MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
//
// Check to see if the CPU supports the APIC Base Address MSR
//
if (LocalApicBaseAddressMsrSupported ()) {
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
//
// Local APIC should have been enabled
//
ASSERT (ApicBaseMsr.Bits.En != 0);
ASSERT (ApicBaseMsr.Bits.Extd == 0);
ASSERT (ApicBaseMsr.Bits.EN != 0);
ASSERT (ApicBaseMsr.Bits.EXTD == 0);
}
}
);