UefiCpuPkg/LocalApic.h: Remove duplicated/conflicted definitions
#define MSR_IA32_APIC_BASE_ADDRESS is duplicated with #define MSR_IA32_APIC_BASE defined in UefiCpuPkg/Include/Register/ArchitecturalMsr.h, so we could remove it and update the modules to use MSR_IA32_APIC_BASE from ArchitecturalMsr.h. Structure MSR_IA32_APIC_BASE conflicts with #define MSR_IA32_APIC_BASE defined in UefiCpuPkg/Include/Register/ArchitecturalMsr.h, so we could remove it and update the modules to use structure MSR_IA32_APIC_BASE_REGISTER from ArchitecturalMsr.h. v5: 1. Update SourceLevelDebugPkg to use APIC Base MSR from ArchitecturalMsr.h. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com>
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@@ -4,7 +4,7 @@
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This local APIC library instance supports x2APIC capable processors
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which have xAPIC and x2APIC modes.
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Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@@ -16,6 +16,7 @@
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**/
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#include <Register/Cpuid.h>
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#include <Register/Msr.h>
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#include <Register/LocalApic.h>
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#include <Library/BaseLib.h>
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@@ -68,7 +69,7 @@ GetLocalApicBaseAddress (
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VOID
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)
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{
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MSR_IA32_APIC_BASE ApicBaseMsr;
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MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
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if (!LocalApicBaseAddressMsrSupported ()) {
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//
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@@ -78,10 +79,10 @@ GetLocalApicBaseAddress (
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return PcdGet32 (PcdCpuLocalApicBaseAddress);
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}
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ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
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ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
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return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32)) +
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(((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12);
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return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +
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(((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
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}
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/**
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@@ -98,7 +99,7 @@ SetLocalApicBaseAddress (
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IN UINTN BaseAddress
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)
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{
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MSR_IA32_APIC_BASE ApicBaseMsr;
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MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
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ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);
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@@ -109,12 +110,12 @@ SetLocalApicBaseAddress (
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return;
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}
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ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
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ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
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ApicBaseMsr.Bits.ApicBaseLow = (UINT32) (BaseAddress >> 12);
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ApicBaseMsr.Bits.ApicBaseHigh = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));
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ApicBaseMsr.Bits.ApicBase = (UINT32) (BaseAddress >> 12);
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ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));
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AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
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AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
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}
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/**
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@@ -301,7 +302,7 @@ GetApicMode (
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VOID
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)
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{
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MSR_IA32_APIC_BASE ApicBaseMsr;
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MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
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if (!LocalApicBaseAddressMsrSupported ()) {
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//
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@@ -310,12 +311,12 @@ GetApicMode (
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return LOCAL_APIC_MODE_XAPIC;
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}
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ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
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ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
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//
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// Local APIC should have been enabled
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//
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ASSERT (ApicBaseMsr.Bits.En != 0);
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if (ApicBaseMsr.Bits.Extd != 0) {
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ASSERT (ApicBaseMsr.Bits.EN != 0);
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if (ApicBaseMsr.Bits.EXTD != 0) {
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return LOCAL_APIC_MODE_X2APIC;
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} else {
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return LOCAL_APIC_MODE_XAPIC;
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@@ -339,8 +340,8 @@ SetApicMode (
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IN UINTN ApicMode
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)
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{
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UINTN CurrentMode;
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MSR_IA32_APIC_BASE ApicBaseMsr;
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UINTN CurrentMode;
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MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
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if (!LocalApicBaseAddressMsrSupported ()) {
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//
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@@ -355,9 +356,9 @@ SetApicMode (
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case LOCAL_APIC_MODE_XAPIC:
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break;
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case LOCAL_APIC_MODE_X2APIC:
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ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
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ApicBaseMsr.Bits.Extd = 1;
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AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
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ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
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ApicBaseMsr.Bits.EXTD = 1;
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AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
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break;
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default:
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ASSERT (FALSE);
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@@ -369,12 +370,12 @@ SetApicMode (
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// Transition from x2APIC mode to xAPIC mode is a two-step process:
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// x2APIC -> Local APIC disabled -> xAPIC
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//
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ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
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ApicBaseMsr.Bits.Extd = 0;
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ApicBaseMsr.Bits.En = 0;
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AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
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ApicBaseMsr.Bits.En = 1;
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AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
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ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
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ApicBaseMsr.Bits.EXTD = 0;
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ApicBaseMsr.Bits.EN = 0;
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AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
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ApicBaseMsr.Bits.EN = 1;
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AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
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break;
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case LOCAL_APIC_MODE_X2APIC:
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break;
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