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QuarkPlatformPkg/PlatformInit: Clear memory based on TCG MOR request

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If TCG Memory Overwrite Request is set, then clear all memory
available for use by an OS.  An OS may optionally use embedded
SRAM in Quark SoC X1000, so the embedded SRAM should is cleared
too.  TCG MOR requests are communicated through a UEFI variable.
This module reads UEFI variable to check state of MOR request.

Cc: Kelly Steele <kelly.steele@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Kelly Steele <kelly.steele@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19776 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Michael Kinney
2016-01-29 23:38:52 +00:00
committed by mdkinney
parent e3dca1859b
commit a9054761e7
2 changed files with 90 additions and 2 deletions
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51
QuarkPlatformPkg/Platform/Pei/PlatformInit/MemoryCallback.c
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@@ -7,7 +7,7 @@ following action is performed in this file,
4. Set MTRR for PEI
5. Create FV HOB and Flash HOB
Copyright (c) 2013 Intel Corporation.
Copyright (c) 2013 - 2016, Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -108,6 +108,9 @@ MemoryDiscoveredPpiNotifyCallback (
UINT8 CpuAddressWidth;
UINT32 RegEax;
MTRR_SETTINGS MtrrSettings;
EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
UINT8 MorControl;
UINTN DataSize;
DEBUG ((EFI_D_INFO, "Platform PEIM Memory Callback\n"));
@@ -151,6 +154,52 @@ MemoryDiscoveredPpiNotifyCallback (
PERF_END (NULL, "SetCache", NULL, 0);
//
// Get necessary PPI
//
Status = PeiServicesLocatePpi (
&gEfiPeiReadOnlyVariable2PpiGuid, // GUID
0, // INSTANCE
NULL, // EFI_PEI_PPI_DESCRIPTOR
(VOID **)&VariableServices // PPI
);
ASSERT_EFI_ERROR (Status);
//
// Detect MOR request by the OS.
//
MorControl = 0;
DataSize = sizeof (MorControl);
Status = VariableServices->GetVariable (
VariableServices,
MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME,
&gEfiMemoryOverwriteControlDataGuid,
NULL,
&DataSize,
&MorControl
);
//
// If OS requested a memory overwrite perform it now for Embedded SRAM
//
if (MOR_CLEAR_MEMORY_VALUE (MorControl)) {
DEBUG ((EFI_D_INFO, "Clear Embedded SRAM per MOR request.\n"));
if (PcdGet32 (PcdESramMemorySize) > 0) {
if (PcdGet32 (PcdEsramStage1Base) == 0) {
//
// ZeroMem() generates an ASSERT() if Buffer parameter is NULL.
// Clear byte at 0 and start clear operation at address 1.
//
*(UINT8 *)(0) = 0;
ZeroMem ((VOID *)1, (UINTN)PcdGet32 (PcdESramMemorySize) - 1);
} else {
ZeroMem (
(VOID *)(UINTN)PcdGet32 (PcdEsramStage1Base),
(UINTN)PcdGet32 (PcdESramMemorySize)
);
}
}
}
//
// Install PeiReset for PeiResetSystem service
//