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Introduce PcdDxeIplSwitchToLongMode to DxeIplPeim and remove DxeIplX64Peim.

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git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@2018 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
qhuang8
2006-11-27 10:14:02 +00:00
parent ad3e8660d3
commit abb26634f2
20 changed files with 488 additions and 1913 deletions
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2
EdkModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c
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@@ -19,7 +19,7 @@ Abstract:
--*/
#include <DxeIpl.h>
#include "DxeIpl.h"
EFI_STATUS
CreateArchSpecificHobs (

2
EdkModulePkg/Core/DxeIplPeim/Ia32/ImageRead.c
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@@ -17,7 +17,7 @@ Abstract:
--*/
#include <DxeIpl.h>
#include "DxeIpl.h"
EFI_STATUS
EFIAPI

296
EdkModulePkg/Core/DxeIplPeim/Ia32/LongMode.S Normal file
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@@ -0,0 +1,296 @@
#------------------------------------------------------------------------------
#*
#* Copyright (c) 2006, Intel Corporation
#* All rights reserved. This program and the accompanying materials
#* are licensed and made available under the terms and conditions of the BSD License
#* which accompanies this distribution. The full text of the license may be found at
#* http://opensource.org/licenses/bsd-license.php
#*
#* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
#* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#*
#* LongMode.S
#*
#* Abstract:
#*
#* Transition from 32-bit protected mode EFI environment into x64
#* 64-bit bit long mode.
#*
#* This file is not fully ported or operational.
#*
#------------------------------------------------------------------------------
.686p:
#.MODEL flat
#
# Create the exception handler code in IA32 C code
#
.code:
.stack:
.MMX:
.XMM:
.global _LoadGo64Gdt;
_LoadGo64Gdt:
pushl %ebp # C prolog
pushl %edi
movl %esp, %ebp
#
# Disable interrupts
#
cli
#
# Reload the selectors
# Note:
# Make the Selectors 64-bit ready
#
movl gdtr, %edi # Load GDT register
movw %cs, %ax # Get the selector data from our code image
mov %ax, %es
# FIXME MISMATCH: " lgdt FWORD PTR es:[edi] "
.byte 0x67
.byte 0xea # Far Jump Offset:Selector to reload CS
# FIXME MISMATCH: " dd OFFSET DataSelectorRld"
# FIXME MISMATCH: " dw LINEAR_CODE_SEL "
DataSelectorRld:
movw SYS_DATA_SEL, %ax # Update the Base for the new selectors, too
movw %ax, %ds
movw %ax, %es
movw %ax, %fs
movw %ax, %gs
movw %ax, %ss
popl %edi
popl %ebp
ret
#_LoadGo64Gdt ENDP
# VOID
# ActivateLongMode (
# IN EFI_PHYSICAL_ADDRESS PageTables,
# IN EFI_PHYSICAL_ADDRESS HobStart,
# IN EFI_PHYSICAL_ADDRESS Stack,
# IN EFI_PHYSICAL_ADDRESS PpisNeededByDxeIplEntryPoint,
# IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint
# )
#
# Input: [ebp][0h] = Original ebp
# [ebp][4h] = Return address
# [ebp][8h] = PageTables
# [ebp][10h] = HobStart
# [ebp][18h] = Stack
# [ebp][20h] = CodeEntryPoint1 <--- Call this first (for each call, pass HOB pointer)
# [ebp][28h] = CodeEntryPoint2 <--- Call this second
#
#
.global _ActivateLongMode;
_ActivateLongMode:
pushl %ebp # C prolog
movl %esp, %ebp
#
# Use CPUID to determine if the processor supports long mode.
#
movl $0x80000000, %eax # Extended-function code 8000000h.
cpuid # Is largest extended function
cmpl $0x80000000, %eax # any function > 80000000h?
jbe no_long_mode # If not, no long mode.
movl $0x80000001, %eax # Extended-function code 8000001h.
cpuid # Now EDX = extended-features flags.
btl $29, %edx # Test if long mode is supported.
jnc no_long_mode # Exit if not supported.
#
# Enable the 64-bit page-translation-table entries by
# setting CR4.PAE=1 (this is _required_ before activating
# long mode). Paging is not enabled until after long mode
# is enabled.
#
movl %cr4, %eax
btsl $5, %eax
movl %eax, %cr4
#
# Get the long-mode page tables, and initialize the
# 64-bit CR3 (page-table base address) to point to the base
# of the PML4 page table. The PML4 page table must be located
# below 4 Gbytes because only 32 bits of CR3 are loaded when
# the processor is not in 64-bit mode.
#
movl 0x8(%ebp), %eax # Get Page Tables
movl %eax, %cr3 # Initialize CR3 with PML4 base.
#
# Enable long mode (set EFER.LME=1).
#
movl $0xc0000080, %ecx # EFER MSR number.
rdmsr # Read EFER.
btsl $8, %eax # Set LME=1.
wrmsr # Write EFER.
#
# Enable paging to activate long mode (set CR0.PG=1)
#
movl %cr0, %eax # Read CR0.
btsl $31, %eax # Set PG=1.
movl %eax, %cr0 # Write CR0.
jmp go_to_long_mode
go_to_long_mode:
#
# This is the next instruction after enabling paging. Jump to long mode
#
.byte 0x67
.byte 0xea # Far Jump Offset:Selector to reload CS
#FIXME MISMATCH: " dd OFFSET in_long_mode"
#FIXME MISMATCH: " dw SYS_CODE64_SEL "
in_long_mode:
movw SYS_DATA64_SEL, %ax
movw %ax, %es
movw %ax, %ss
movw %ax, %ds
jmp .
#
# We're in long mode, so marshall the arguments to call the
# passed in function pointers
# Recall
# [ebp][10h] = HobStart
# [ebp][18h] = Stack
# [ebp][20h] = PpisNeededByDxeIplEntryPoint <--- Call this first (for each call, pass HOB pointer)
# [ebp][28h] = DxeCoreEntryPoint <--- Call this second
#
.byte 0x48
movl 0x18(%ebp), %ebx # Setup the stack
.byte 0x48
movl %ebx, %esp # On a new stack now
## 00000905 FF D0 call rax
.byte 0x48
movl 0x10(%ebp), %ecx # Pass Hob Start in RCX
.byte 0x48
movl 0x28(%ebp), %eax # Get the function pointer for
# DxeCoreEntryPoint into EAX
## 00000905 FF D0 call rax
.byte 0xff
.byte 0xd0
#
# WE SHOULD NEVER GET HERE!!!!!!!!!!!!!
#
no_long_mode:
jmp no_long_mode
#_ActivateLongMode ENDP
.align 16
gdtr: #FIXME MISMATCH: "gdtr dw _GDT_END - _GDT_BASE - 1 "
#FIXME MISMATCH: " dd OFFSET _GDT_BASE "
#-----------------------------------------------------------------------------;
# global descriptor table (GDT)
#-----------------------------------------------------------------------------;
.align 16
.global _GDT_BASE
_GDT_BASE:
# null descriptor
.equ NULL_SEL, .-_GDT_BASE # Selector [0]
.word 0 # limit 15:0
.word 0 # base 15:0
.byte 0 # base 23:16
.byte 0 # type
.byte 0 # limit 19:16, flags
.byte 0 # base 31:24
# linear data segment descriptor
.equ LINEAR_SEL, .-_GDT_BASE # Selector [0x8]
.word 0xFFFF # limit 0xFFFFF
.word 0 # base 0
.byte 0
.byte 0x92 # present, ring 0, data, expand-up, writable
.byte 0xCF # page-granular, 32-bit
.byte 0
# linear code segment descriptor
.equ LINEAR_CODE_SEL, .-_GDT_BASE # Selector [0x10]
.word 0xFFFF # limit 0xFFFFF
.word 0 # base 0
.byte 0
.byte 0x9F # present, ring 0, data, expand-up, writable
.byte 0xCF # page-granular, 32-bit
.byte 0
# system data segment descriptor
.equ SYS_DATA_SEL, .-_GDT_BASE # Selector [0x18]
.word 0xFFFF # limit 0xFFFFF
.word 0 # base 0
.byte 0
.byte 0x93 # present, ring 0, data, expand-up, writable
.byte 0xCF # page-granular, 32-bit
.byte 0
# system code segment descriptor
.equ SYS_CODE_SEL, .-_GDT_BASE # Selector [0x20]
.word 0xFFFF # limit 0xFFFFF
.word 0 # base 0
.byte 0
.byte 0x9A # present, ring 0, data, expand-up, writable
.byte 0xCF # page-granular, 32-bit
.byte 0
# spare segment descriptor
.equ SPARE3_SEL, .-_GDT_BASE # Selector [0x28]
.word 0 # limit 0xFFFFF
.word 0 # base 0
.byte 0
.byte 0 # present, ring 0, data, expand-up, writable
.byte 0 # page-granular, 32-bit
.byte 0
#
# system data segment descriptor
#
.equ SYS_DATA64_SEL, .-_GDT_BASE # Selector [0x30]
.word 0xFFFF # limit 0xFFFFF
.word 0 # base 0
.byte 0
.byte 0x92 # P | DPL [1..2] | 1 | 1 | C | R | A
.byte 0xCF # G | D | L | AVL | Segment [19..16]
.byte 0
#
# system code segment descriptor
#
.equ SYS_CODE64_SEL, .-_GDT_BASE # Selector [0x38]
.word 0xFFFF # limit 0xFFFFF
.word 0 # base 0
.byte 0
.byte 0x9A # P | DPL [1..2] | 1 | 1 | C | R | A
.byte 0xAF # G | D | L | AVL | Segment [19..16]
.byte 0
# spare segment descriptor
.equ SPARE4_SEL, .-_GDT_BASE # Selector [0x40]
.word 0 # limit 0xFFFFF
.word 0 # base 0
.byte 0
.byte 0 # present, ring 0, data, expand-up, writable
.byte 0 # page-granular, 32-bit
.byte 0
_GDT_END:

294
EdkModulePkg/Core/DxeIplPeim/Ia32/LongMode.asm Normal file
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@@ -0,0 +1,294 @@
TITLE LongMode.asm: Assembly code for the entering long mode
;------------------------------------------------------------------------------
;*
;* Copyright (c) 2006, Intel Corporation
;* All rights reserved. This program and the accompanying materials
;* are licensed and made available under the terms and conditions of the BSD License
;* which accompanies this distribution. The full text of the license may be found at
;* http://opensource.org/licenses/bsd-license.php
;*
;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;*
;* LongMode.asm
;*
;* Abstract:
;*
;* Transition from 32-bit protected mode EFI environment into x64
;* 64-bit bit long mode.
;*
;------------------------------------------------------------------------------
.686p
.model flat
;
; Create the exception handler code in IA32 C code
;
.code
.stack
.MMX
.XMM
_LoadGo64Gdt PROC Near Public
push ebp ; C prolog
push edi
mov ebp, esp
;
; Disable interrupts
;
cli
;
; Reload the selectors
; Note:
; Make the Selectors 64-bit ready
;
mov edi, OFFSET gdtr ; Load GDT register
mov ax,cs ; Get the selector data from our code image
mov es,ax
lgdt FWORD PTR es:[edi] ; and update the GDTR
db 067h
db 0eah ; Far Jump Offset:Selector to reload CS
dd OFFSET DataSelectorRld; Offset is ensuing instruction boundary
dw LINEAR_CODE_SEL ; Selector is our code selector, 10h
DataSelectorRld::
mov ax, SYS_DATA_SEL ; Update the Base for the new selectors, too
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
mov ss, ax
pop edi
pop ebp
ret
_LoadGo64Gdt endp
; VOID
; ActivateLongMode (
; IN EFI_PHYSICAL_ADDRESS PageTables,
; IN EFI_PHYSICAL_ADDRESS HobStart,
; IN EFI_PHYSICAL_ADDRESS Stack,
; IN EFI_PHYSICAL_ADDRESS PpisNeededByDxeIplEntryPoint,
; IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint
; )
;
; Input: [ebp][0h] = Original ebp
; [ebp][4h] = Return address
; [ebp][8h] = PageTables
; [ebp][10h] = HobStart
; [ebp][18h] = Stack
; [ebp][20h] = CodeEntryPoint1 <--- Call this first (for each call, pass HOB pointer)
; [ebp][28h] = CodeEntryPoint2 <--- Call this second
;
;
_ActivateLongMode PROC Near Public
push ebp ; C prolog
mov ebp, esp
;
; Use CPUID to determine if the processor supports long mode.
;
mov eax, 80000000h ; Extended-function code 8000000h.
cpuid ; Is largest extended function
cmp eax, 80000000h ; any function > 80000000h?
jbe no_long_mode ; If not, no long mode.
mov eax, 80000001h ; Extended-function code 8000001h.
cpuid ; Now EDX = extended-features flags.
bt edx, 29 ; Test if long mode is supported.
jnc no_long_mode ; Exit if not supported.
;
; Enable the 64-bit page-translation-table entries by
; setting CR4.PAE=1 (this is _required_ before activating
; long mode). Paging is not enabled until after long mode
; is enabled.
;
mov eax, cr4
bts eax, 5
mov cr4, eax
;
; Get the long-mode page tables, and initialize the
; 64-bit CR3 (page-table base address) to point to the base
; of the PML4 page table. The PML4 page table must be located
; below 4 Gbytes because only 32 bits of CR3 are loaded when
; the processor is not in 64-bit mode.
;
mov eax, [ebp+8h] ; Get Page Tables
mov cr3, eax ; Initialize CR3 with PML4 base.
;
; Enable long mode (set EFER.LME=1).
;
mov ecx, 0c0000080h ; EFER MSR number.
rdmsr ; Read EFER.
bts eax, 8 ; Set LME=1.
wrmsr ; Write EFER.
;
; Enable paging to activate long mode (set CR0.PG=1)
;
mov eax, cr0 ; Read CR0.
bts eax, 31 ; Set PG=1.
mov cr0, eax ; Write CR0.
jmp go_to_long_mode
go_to_long_mode:
;
; This is the next instruction after enabling paging. Jump to long mode
;
db 067h
db 0eah ; Far Jump Offset:Selector to reload CS
dd OFFSET in_long_mode; Offset is ensuing instruction boundary
dw SYS_CODE64_SEL ; Selector is our code selector, 10h
in_long_mode::
mov ax, SYS_DATA64_SEL
mov es, ax
mov ss, ax
mov ds, ax
;; jmp $
;
; We're in long mode, so marshall the arguments to call the
; passed in function pointers
; Recall
; [ebp][10h] = HobStart
; [ebp][18h] = Stack
; [ebp][20h] = PpisNeededByDxeIplEntryPoint <--- Call this first (for each call, pass HOB pointer)
; [ebp][28h] = DxeCoreEntryPoint <--- Call this second
;
db 48h
mov ebx, [ebp+18h] ; Setup the stack
db 48h
mov esp, ebx ; On a new stack now
;; 00000905 FF D0 call rax
db 48h
mov ecx, [ebp+10h] ; Pass Hob Start in RCX
db 48h
mov eax, [ebp+28h] ; Get the function pointer for
; DxeCoreEntryPoint into EAX
;; 00000905 FF D0 call rax
db 0ffh
db 0d0h
;
; WE SHOULD NEVER GET HERE!!!!!!!!!!!!!
;
no_long_mode:
jmp no_long_mode
_ActivateLongMode endp
align 16
gdtr dw GDT_END - GDT_BASE - 1 ; GDT limit
dd OFFSET GDT_BASE ; (GDT base gets set above)
;-----------------------------------------------------------------------------;
; global descriptor table (GDT)
;-----------------------------------------------------------------------------;
align 16
public GDT_BASE
GDT_BASE:
; null descriptor
NULL_SEL equ $-GDT_BASE ; Selector [0]
dw 0 ; limit 15:0
dw 0 ; base 15:0
db 0 ; base 23:16
db 0 ; type
db 0 ; limit 19:16, flags
db 0 ; base 31:24
; linear data segment descriptor
LINEAR_SEL equ $-GDT_BASE ; Selector [0x8]
dw 0FFFFh ; limit 0xFFFFF
dw 0 ; base 0
db 0
db 092h ; present, ring 0, data, expand-up, writable
db 0CFh ; page-granular, 32-bit
db 0
; linear code segment descriptor
LINEAR_CODE_SEL equ $-GDT_BASE ; Selector [0x10]
dw 0FFFFh ; limit 0xFFFFF
dw 0 ; base 0
db 0
db 09Fh ; present, ring 0, data, expand-up, writable
db 0CFh ; page-granular, 32-bit
db 0
; system data segment descriptor
SYS_DATA_SEL equ $-GDT_BASE ; Selector [0x18]
dw 0FFFFh ; limit 0xFFFFF
dw 0 ; base 0
db 0
db 093h ; present, ring 0, data, expand-up, writable
db 0CFh ; page-granular, 32-bit
db 0
; system code segment descriptor
SYS_CODE_SEL equ $-GDT_BASE ; Selector [0x20]
dw 0FFFFh ; limit 0xFFFFF
dw 0 ; base 0
db 0
db 09Ah ; present, ring 0, data, expand-up, writable
db 0CFh ; page-granular, 32-bit
db 0
; spare segment descriptor
SPARE3_SEL equ $-GDT_BASE ; Selector [0x28]
dw 0 ; limit 0xFFFFF
dw 0 ; base 0
db 0
db 0 ; present, ring 0, data, expand-up, writable
db 0 ; page-granular, 32-bit
db 0
;
; system data segment descriptor
;
SYS_DATA64_SEL equ $-GDT_BASE ; Selector [0x30]
dw 0FFFFh ; limit 0xFFFFF
dw 0 ; base 0
db 0
db 092h ; P | DPL [1..2] | 1 | 1 | C | R | A
db 0CFh ; G | D | L | AVL | Segment [19..16]
db 0
;
; system code segment descriptor
;
SYS_CODE64_SEL equ $-GDT_BASE ; Selector [0x38]
dw 0FFFFh ; limit 0xFFFFF
dw 0 ; base 0
db 0
db 09Ah ; P | DPL [1..2] | 1 | 1 | C | R | A
db 0AFh ; G | D | L | AVL | Segment [19..16]
db 0
; spare segment descriptor
SPARE4_SEL equ $-GDT_BASE ; Selector [0x40]
dw 0 ; limit 0xFFFFF
dw 0 ; base 0
db 0
db 0 ; present, ring 0, data, expand-up, writable
db 0 ; page-granular, 32-bit
db 0
GDT_END:
END

160
EdkModulePkg/Core/DxeIplPeim/Ia32/VirtualMemory.c Normal file
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/*++
Copyright (c) 2006, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
VirtualMemory.c
Abstract:
x64 Virtual Memory Management Services in the form of an IA-32 driver.
Used to establish a 1:1 Virtual to Physical Mapping that is required to
enter Long Mode (x64 64-bit mode).
While we make a 1:1 mapping (identity mapping) for all physical pages
we still need to use the MTRR's to ensure that the cachability attirbutes
for all memory regions is correct.
The basic idea is to use 2MB page table entries where ever possible. If
more granularity of cachability is required then 4K page tables are used.
References:
1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel
2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
--*/
#include "VirtualMemory.h"
EFI_PHYSICAL_ADDRESS
CreateIdentityMappingPageTables (
VOID
)
/*++
Routine Description:
Allocates and fills in the Page Directory and Page Table Entries to
establish a 1:1 Virtual to Physical mapping.
Arguments:
NumberOfProcessorPhysicalAddressBits - Number of processor address bits to use.
Limits the number of page table entries
to the physical address space.
Returns:
EFI_SUCCESS The 1:1 Virtual to Physical identity mapping was created
--*/
{
UINT32 RegEax;
UINT8 PhysicalAddressBits;
EFI_PHYSICAL_ADDRESS PageAddress;
UINTN IndexOfPml4Entries;
UINTN IndexOfPdpEntries;
UINTN IndexOfPageDirectoryEntries;
UINTN NumberOfPml4EntriesNeeded;
UINTN NumberOfPdpEntriesNeeded;
PAGE_MAP_AND_DIRECTORY_POINTER *PageMapLevel4Entry;
PAGE_MAP_AND_DIRECTORY_POINTER *PageMap;
PAGE_MAP_AND_DIRECTORY_POINTER *PageDirectoryPointerEntry;
PAGE_TABLE_ENTRY *PageDirectoryEntry;
//
// By architecture only one PageMapLevel4 exists - so lets allocate storage for it.
//
PageMap = AllocatePages (1);
ASSERT (PageMap != NULL);
//
// Get physical address bits supported.
//
AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
if (RegEax >= 0x80000008) {
AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
PhysicalAddressBits = (UINT8) RegEax;
} else {
PhysicalAddressBits = 36;
}
//
// Calculate the table entries needed.
//
if (PhysicalAddressBits <= 39 ) {
NumberOfPml4EntriesNeeded = 1;
NumberOfPdpEntriesNeeded = 1 << (PhysicalAddressBits - 30);
} else {
NumberOfPml4EntriesNeeded = 1 << (PhysicalAddressBits - 39);
NumberOfPdpEntriesNeeded = 512;
}
PageMapLevel4Entry = PageMap;
PageAddress = 0;
for (IndexOfPml4Entries = 0; IndexOfPml4Entries < NumberOfPml4EntriesNeeded; IndexOfPml4Entries++, PageMapLevel4Entry++) {
//
// Each PML4 entry points to a page of Page Directory Pointer entires.
// So lets allocate space for them and fill them in in the IndexOfPdpEntries loop.
//
PageDirectoryPointerEntry = AllocatePages (1);
ASSERT (PageDirectoryPointerEntry != NULL);
//
// Make a PML4 Entry
//
PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry;
PageMapLevel4Entry->Bits.ReadWrite = 1;
PageMapLevel4Entry->Bits.Present = 1;
for (IndexOfPdpEntries = 0; IndexOfPdpEntries < NumberOfPdpEntriesNeeded; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {
//
// Each Directory Pointer entries points to a page of Page Directory entires.
// So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.
//
PageDirectoryEntry = AllocatePages (1);
ASSERT (PageDirectoryEntry != NULL);
//
// Fill in a Page Directory Pointer Entries
//
PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry;
PageDirectoryPointerEntry->Bits.ReadWrite = 1;
PageDirectoryPointerEntry->Bits.Present = 1;
for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += 0x200000) {
//
// Fill in the Page Directory entries
//
PageDirectoryEntry->Uint64 = (UINT64)PageAddress;
PageDirectoryEntry->Bits.ReadWrite = 1;
PageDirectoryEntry->Bits.Present = 1;
PageDirectoryEntry->Bits.MustBe1 = 1;
}
}
}
//
// For the PML4 entries we are not using fill in a null entry.
// For now we just copy the first entry.
//
for (; IndexOfPml4Entries < 512; IndexOfPml4Entries++, PageMapLevel4Entry++) {
CopyMem (
PageMapLevel4Entry,
PageMap,
sizeof (PAGE_MAP_AND_DIRECTORY_POINTER)
);
}
return (EFI_PHYSICAL_ADDRESS) (UINTN)PageMap; // FIXME
}

86
EdkModulePkg/Core/DxeIplPeim/Ia32/VirtualMemory.h Normal file
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/*++
Copyright (c) 2006, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
VirtualMemory.h
Abstract:
x64 Long Mode Virtual Memory Management Definitions
References:
1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel
2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
4) AMD64 Architecture Programmer's Manual Volume 2: System Programming
--*/
#ifndef _VIRTUAL_MEMORY_H_
#define _VIRTUAL_MEMORY_H_
#pragma pack(1)
//
// Page-Map Level-4 Offset (PML4) and
// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
//
typedef union {
struct {
UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
UINT64 Reserved:1; // Reserved
UINT64 MustBeZero:2; // Must Be Zero
UINT64 Available:3; // Available for use by system software
UINT64 PageTableBaseAddress:40; // Page Table Base Address
UINT64 AvabilableHigh:11; // Available for use by system software
UINT64 Nx:1; // No Execute bit
} Bits;
UINT64 Uint64;
} PAGE_MAP_AND_DIRECTORY_POINTER;
//
// Page Table Entry 2MB
//
typedef union {
struct {
UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page
UINT64 MustBe1:1; // Must be 1
UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
UINT64 Available:3; // Available for use by system software
UINT64 PAT:1; //
UINT64 MustBeZero:8; // Must be zero;
UINT64 PageTableBaseAddress:31; // Page Table Base Address
UINT64 AvabilableHigh:11; // Available for use by system software
UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution
} Bits;
UINT64 Uint64;
} PAGE_TABLE_ENTRY;
#pragma pack()
EFI_PHYSICAL_ADDRESS
CreateIdentityMappingPageTables (
VOID
)
;
#endif