OvmfPkg: Apply uncrustify changes
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the OvmfPkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Andrew Fish <afish@apple.com>
This commit is contained in:
Michael Kubacki
committed by
mergify[bot]
mergify[bot]
parent
d1050b9dff
commit
ac0a286f4d
@@ -152,9 +152,9 @@
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* at Documentation/devicetree/bindings/arm/xen.txt.
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*/
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#define XEN_HYPERCALL_TAG 0xEA1
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#define XEN_HYPERCALL_TAG 0xEA1
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#define uint64_aligned_t UINT64 __attribute__((aligned(8)))
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#define uint64_aligned_t UINT64 __attribute__((aligned(8)))
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#ifndef __ASSEMBLY__
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#define ___DEFINE_XEN_GUEST_HANDLE(name, type) \
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@@ -173,134 +173,137 @@
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#define __DEFINE_XEN_GUEST_HANDLE(name, type) \
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___DEFINE_XEN_GUEST_HANDLE(name, type); \
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___DEFINE_XEN_GUEST_HANDLE(const_##name, const type)
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#define DEFINE_XEN_GUEST_HANDLE(name) __DEFINE_XEN_GUEST_HANDLE(name, name)
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#define __XEN_GUEST_HANDLE(name) __guest_handle_64_ ## name
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#define XEN_GUEST_HANDLE(name) __XEN_GUEST_HANDLE(name)
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#define DEFINE_XEN_GUEST_HANDLE(name) __DEFINE_XEN_GUEST_HANDLE(name, name)
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#define __XEN_GUEST_HANDLE(name) __guest_handle_64_ ## name
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#define XEN_GUEST_HANDLE(name) __XEN_GUEST_HANDLE(name)
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/* this is going to be changed on 64 bit */
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#define XEN_GUEST_HANDLE_PARAM(name) __guest_handle_ ## name
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#define XEN_GUEST_HANDLE_PARAM(name) __guest_handle_ ## name
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#define set_xen_guest_handle_raw(hnd, val) \
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do { \
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typeof(&(hnd)) _sxghr_tmp = &(hnd); \
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_sxghr_tmp->q = 0; \
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_sxghr_tmp->p = val; \
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} while ( 0 )
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#ifdef __XEN_TOOLS__
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#ifdef __XEN_TOOLS__
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#define get_xen_guest_handle(val, hnd) do { val = (hnd).p; } while (0)
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#endif
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#define set_xen_guest_handle(hnd, val) set_xen_guest_handle_raw(hnd, val)
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#endif
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#define set_xen_guest_handle(hnd, val) set_xen_guest_handle_raw(hnd, val)
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#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
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#if defined (__GNUC__) && !defined (__STRICT_ANSI__)
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/* Anonymous union includes both 32- and 64-bit names (e.g., r0/x0). */
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# define __DECL_REG(n64, n32) union { \
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#define __DECL_REG(n64, n32) union { \
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UINT64 n64; \
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UINT32 n32; \
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}
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#else
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#else
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/* Non-gcc sources must always use the proper 64-bit name (e.g., x0). */
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#define __DECL_REG(n64, n32) UINT64 n64
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#endif
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#define __DECL_REG(n64, n32) UINT64 n64
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#endif
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struct vcpu_guest_core_regs
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{
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/* Aarch64 Aarch32 */
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__DECL_REG(x0, r0_usr);
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__DECL_REG(x1, r1_usr);
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__DECL_REG(x2, r2_usr);
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__DECL_REG(x3, r3_usr);
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__DECL_REG(x4, r4_usr);
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__DECL_REG(x5, r5_usr);
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__DECL_REG(x6, r6_usr);
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__DECL_REG(x7, r7_usr);
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__DECL_REG(x8, r8_usr);
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__DECL_REG(x9, r9_usr);
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__DECL_REG(x10, r10_usr);
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__DECL_REG(x11, r11_usr);
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__DECL_REG(x12, r12_usr);
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struct vcpu_guest_core_regs {
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/* Aarch64 Aarch32 */
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__DECL_REG (x0, r0_usr);
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__DECL_REG (x1, r1_usr);
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__DECL_REG (x2, r2_usr);
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__DECL_REG (x3, r3_usr);
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__DECL_REG (x4, r4_usr);
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__DECL_REG (x5, r5_usr);
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__DECL_REG (x6, r6_usr);
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__DECL_REG (x7, r7_usr);
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__DECL_REG (x8, r8_usr);
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__DECL_REG (x9, r9_usr);
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__DECL_REG (x10, r10_usr);
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__DECL_REG (x11, r11_usr);
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__DECL_REG (x12, r12_usr);
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__DECL_REG(x13, sp_usr);
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__DECL_REG(x14, lr_usr);
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__DECL_REG (x13, sp_usr);
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__DECL_REG (x14, lr_usr);
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__DECL_REG(x15, __unused_sp_hyp);
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__DECL_REG (x15, __unused_sp_hyp);
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__DECL_REG(x16, lr_irq);
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__DECL_REG(x17, sp_irq);
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__DECL_REG (x16, lr_irq);
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__DECL_REG (x17, sp_irq);
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__DECL_REG(x18, lr_svc);
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__DECL_REG(x19, sp_svc);
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__DECL_REG (x18, lr_svc);
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__DECL_REG (x19, sp_svc);
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__DECL_REG(x20, lr_abt);
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__DECL_REG(x21, sp_abt);
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__DECL_REG (x20, lr_abt);
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__DECL_REG (x21, sp_abt);
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__DECL_REG(x22, lr_und);
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__DECL_REG(x23, sp_und);
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__DECL_REG (x22, lr_und);
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__DECL_REG (x23, sp_und);
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__DECL_REG(x24, r8_fiq);
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__DECL_REG(x25, r9_fiq);
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__DECL_REG(x26, r10_fiq);
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__DECL_REG(x27, r11_fiq);
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__DECL_REG(x28, r12_fiq);
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__DECL_REG (x24, r8_fiq);
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__DECL_REG (x25, r9_fiq);
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__DECL_REG (x26, r10_fiq);
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__DECL_REG (x27, r11_fiq);
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__DECL_REG (x28, r12_fiq);
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__DECL_REG(x29, sp_fiq);
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__DECL_REG(x30, lr_fiq);
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__DECL_REG (x29, sp_fiq);
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__DECL_REG (x30, lr_fiq);
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/* Return address and mode */
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__DECL_REG(pc64, pc32); /* ELR_EL2 */
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UINT32 cpsr; /* SPSR_EL2 */
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/* Return address and mode */
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__DECL_REG (pc64, pc32); /* ELR_EL2 */
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UINT32 cpsr; /* SPSR_EL2 */
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union {
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UINT32 spsr_el1; /* AArch64 */
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UINT32 spsr_svc; /* AArch32 */
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};
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union {
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UINT32 spsr_el1; /* AArch64 */
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UINT32 spsr_svc; /* AArch32 */
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};
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/* AArch32 guests only */
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UINT32 spsr_fiq, spsr_irq, spsr_und, spsr_abt;
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/* AArch32 guests only */
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UINT32 spsr_fiq, spsr_irq, spsr_und, spsr_abt;
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/* AArch64 guests only */
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UINT64 sp_el0;
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UINT64 sp_el1, elr_el1;
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/* AArch64 guests only */
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UINT64 sp_el0;
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UINT64 sp_el1, elr_el1;
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};
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typedef struct vcpu_guest_core_regs vcpu_guest_core_regs_t;
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DEFINE_XEN_GUEST_HANDLE(vcpu_guest_core_regs_t);
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#undef __DECL_REG
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typedef struct vcpu_guest_core_regs vcpu_guest_core_regs_t;
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DEFINE_XEN_GUEST_HANDLE (vcpu_guest_core_regs_t);
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#undef __DECL_REG
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typedef UINT64 xen_pfn_t;
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#define PRI_xen_pfn PRIx64
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#define PRI_xen_pfn PRIx64
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/* Maximum number of virtual CPUs in legacy multi-processor guests. */
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/* Only one. All other VCPUS must use VCPUOP_register_vcpu_info */
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#define XEN_LEGACY_MAX_VCPUS 1
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#define XEN_LEGACY_MAX_VCPUS 1
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typedef UINT64 xen_ulong_t;
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#define PRI_xen_ulong PRIx64
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#define PRI_xen_ulong PRIx64
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#if defined(__XEN__) || defined(__XEN_TOOLS__)
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#if defined (__XEN__) || defined (__XEN_TOOLS__)
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struct vcpu_guest_context {
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#define _VGCF_online 0
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#define VGCF_online (1<<_VGCF_online)
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UINT32 flags; /* VGCF_* */
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#define _VGCF_online 0
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#define VGCF_online (1<<_VGCF_online)
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UINT32 flags; /* VGCF_* */
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struct vcpu_guest_core_regs user_regs; /* Core CPU registers */
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struct vcpu_guest_core_regs user_regs; /* Core CPU registers */
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UINT32 sctlr;
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UINT64 ttbcr, ttbr0, ttbr1;
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UINT32 sctlr;
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UINT64 ttbcr, ttbr0, ttbr1;
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};
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typedef struct vcpu_guest_context vcpu_guest_context_t;
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DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t);
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#endif
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DEFINE_XEN_GUEST_HANDLE (vcpu_guest_context_t);
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#endif
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struct arch_vcpu_info {
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};
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typedef struct arch_vcpu_info arch_vcpu_info_t;
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struct arch_shared_info {
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};
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typedef struct arch_shared_info arch_shared_info_t;
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typedef UINT64 xen_callback_t;
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typedef UINT64 xen_callback_t;
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#endif
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#if defined(__XEN__) || defined(__XEN_TOOLS__)
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#if defined (__XEN__) || defined (__XEN_TOOLS__)
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/* PSR bits (CPSR, SPSR)*/
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@@ -314,30 +317,30 @@ typedef UINT64 xen_callback_t;
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#define PSR_JAZELLE (1<<24) /* Jazelle Mode */
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/* 32 bit modes */
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#define PSR_MODE_USR 0x10
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#define PSR_MODE_FIQ 0x11
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#define PSR_MODE_IRQ 0x12
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#define PSR_MODE_SVC 0x13
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#define PSR_MODE_MON 0x16
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#define PSR_MODE_ABT 0x17
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#define PSR_MODE_HYP 0x1a
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#define PSR_MODE_UND 0x1b
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#define PSR_MODE_SYS 0x1f
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#define PSR_MODE_USR 0x10
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#define PSR_MODE_FIQ 0x11
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#define PSR_MODE_IRQ 0x12
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#define PSR_MODE_SVC 0x13
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#define PSR_MODE_MON 0x16
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#define PSR_MODE_ABT 0x17
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#define PSR_MODE_HYP 0x1a
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#define PSR_MODE_UND 0x1b
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#define PSR_MODE_SYS 0x1f
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/* 64 bit modes */
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#define PSR_MODE_BIT 0x10 /* Set iff AArch32 */
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#define PSR_MODE_EL3h 0x0d
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#define PSR_MODE_EL3t 0x0c
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#define PSR_MODE_EL2h 0x09
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#define PSR_MODE_EL2t 0x08
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#define PSR_MODE_EL1h 0x05
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#define PSR_MODE_EL1t 0x04
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#define PSR_MODE_EL0t 0x00
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#define PSR_MODE_BIT 0x10/* Set iff AArch32 */
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#define PSR_MODE_EL3h 0x0d
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#define PSR_MODE_EL3t 0x0c
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#define PSR_MODE_EL2h 0x09
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#define PSR_MODE_EL2t 0x08
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#define PSR_MODE_EL1h 0x05
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#define PSR_MODE_EL1t 0x04
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#define PSR_MODE_EL0t 0x00
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#define PSR_GUEST32_INIT (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_SVC)
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#define PSR_GUEST64_INIT (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_EL1h)
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#define PSR_GUEST64_INIT (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_EL1h)
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#define SCTLR_GUEST_INIT 0x00c50078
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#define SCTLR_GUEST_INIT 0x00c50078
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/*
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* Virtual machine platform (memory layout, interrupts)
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@@ -354,56 +357,56 @@ typedef UINT64 xen_callback_t;
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*/
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/* vGIC v2 mappings */
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#define GUEST_GICD_BASE 0x03001000ULL
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#define GUEST_GICD_SIZE 0x00001000ULL
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#define GUEST_GICC_BASE 0x03002000ULL
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#define GUEST_GICC_SIZE 0x00000100ULL
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#define GUEST_GICD_BASE 0x03001000ULL
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#define GUEST_GICD_SIZE 0x00001000ULL
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#define GUEST_GICC_BASE 0x03002000ULL
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#define GUEST_GICC_SIZE 0x00000100ULL
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/* vGIC v3 mappings */
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#define GUEST_GICV3_GICD_BASE 0x03001000ULL
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#define GUEST_GICV3_GICD_SIZE 0x00010000ULL
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#define GUEST_GICV3_GICD_BASE 0x03001000ULL
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#define GUEST_GICV3_GICD_SIZE 0x00010000ULL
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#define GUEST_GICV3_RDIST_STRIDE 0x20000ULL
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#define GUEST_GICV3_RDIST_REGIONS 1
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#define GUEST_GICV3_GICR0_BASE 0x03020000ULL /* vCPU0 - vCPU7 */
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#define GUEST_GICV3_GICR0_SIZE 0x00100000ULL
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#define GUEST_GICV3_GICR0_BASE 0x03020000ULL /* vCPU0 - vCPU7 */
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#define GUEST_GICV3_GICR0_SIZE 0x00100000ULL
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/* 16MB == 4096 pages reserved for guest to use as a region to map its
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* grant table in.
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*/
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#define GUEST_GNTTAB_BASE 0x38000000ULL
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#define GUEST_GNTTAB_SIZE 0x01000000ULL
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#define GUEST_GNTTAB_BASE 0x38000000ULL
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#define GUEST_GNTTAB_SIZE 0x01000000ULL
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#define GUEST_MAGIC_BASE 0x39000000ULL
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#define GUEST_MAGIC_SIZE 0x01000000ULL
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#define GUEST_RAM_BANKS 2
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#define GUEST_RAM_BANKS 2
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#define GUEST_RAM0_BASE 0x40000000ULL /* 3GB of low RAM @ 1GB */
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#define GUEST_RAM0_SIZE 0xc0000000ULL
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#define GUEST_RAM0_BASE 0x40000000ULL /* 3GB of low RAM @ 1GB */
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#define GUEST_RAM0_SIZE 0xc0000000ULL
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#define GUEST_RAM1_BASE 0x0200000000ULL /* 1016GB of RAM @ 8GB */
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#define GUEST_RAM1_SIZE 0xfe00000000ULL
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#define GUEST_RAM1_BASE 0x0200000000ULL /* 1016GB of RAM @ 8GB */
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#define GUEST_RAM1_SIZE 0xfe00000000ULL
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#define GUEST_RAM_BASE GUEST_RAM0_BASE /* Lowest RAM address */
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#define GUEST_RAM_BASE GUEST_RAM0_BASE /* Lowest RAM address */
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/* Largest amount of actual RAM, not including holes */
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#define GUEST_RAM_MAX (GUEST_RAM0_SIZE + GUEST_RAM1_SIZE)
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#define GUEST_RAM_MAX (GUEST_RAM0_SIZE + GUEST_RAM1_SIZE)
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/* Suitable for e.g. const uint64_t ramfoo[] = GUEST_RAM_BANK_FOOS; */
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#define GUEST_RAM_BANK_BASES { GUEST_RAM0_BASE, GUEST_RAM1_BASE }
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#define GUEST_RAM_BANK_SIZES { GUEST_RAM0_SIZE, GUEST_RAM1_SIZE }
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#define GUEST_RAM_BANK_BASES { GUEST_RAM0_BASE, GUEST_RAM1_BASE }
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#define GUEST_RAM_BANK_SIZES { GUEST_RAM0_SIZE, GUEST_RAM1_SIZE }
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/* Interrupts */
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#define GUEST_TIMER_VIRT_PPI 27
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#define GUEST_TIMER_PHYS_S_PPI 29
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#define GUEST_TIMER_PHYS_NS_PPI 30
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#define GUEST_EVTCHN_PPI 31
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#define GUEST_TIMER_VIRT_PPI 27
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#define GUEST_TIMER_PHYS_S_PPI 29
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#define GUEST_TIMER_PHYS_NS_PPI 30
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#define GUEST_EVTCHN_PPI 31
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/* PSCI functions */
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#define PSCI_cpu_suspend 0
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#define PSCI_cpu_off 1
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#define PSCI_cpu_on 2
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#define PSCI_migrate 3
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#define PSCI_cpu_suspend 0
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#define PSCI_cpu_off 1
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#define PSCI_cpu_on 2
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#define PSCI_migrate 3
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#endif
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