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OvmfPkg: Apply uncrustify changes

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the OvmfPkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Andrew Fish <afish@apple.com>
This commit is contained in:
Michael Kubacki
2021-12-05 14:54:09 -08:00
committed by mergify[bot]
parent d1050b9dff
commit ac0a286f4d
445 changed files with 30894 additions and 26369 deletions
Download Patch File Download Diff File Expand all files Collapse all files

46
OvmfPkg/PlatformPei/AmdSev.c
View File

@@ -58,10 +58,10 @@ AmdSevEsInitialize (
// make them reserved.
//
GhcbPageCount = mMaxCpuCount * 2;
GhcbBase = AllocateReservedPages (GhcbPageCount);
GhcbBase = AllocateReservedPages (GhcbPageCount);
ASSERT (GhcbBase != NULL);
GhcbBasePa = (PHYSICAL_ADDRESS)(UINTN) GhcbBase;
GhcbBasePa = (PHYSICAL_ADDRESS)(UINTN)GhcbBase;
//
// Each vCPU gets two consecutive pages, the first is the GHCB and the
@@ -70,10 +70,10 @@ AmdSevEsInitialize (
//
for (PageCount = 0; PageCount < GhcbPageCount; PageCount += 2) {
DecryptStatus = MemEncryptSevClearPageEncMask (
0,
GhcbBasePa + EFI_PAGES_TO_SIZE (PageCount),
1
);
0,
GhcbBasePa + EFI_PAGES_TO_SIZE (PageCount),
1
);
ASSERT_RETURN_ERROR (DecryptStatus);
}
@@ -84,16 +84,19 @@ AmdSevEsInitialize (
PcdStatus = PcdSet64S (PcdGhcbSize, EFI_PAGES_TO_SIZE (GhcbPageCount));
ASSERT_RETURN_ERROR (PcdStatus);
DEBUG ((DEBUG_INFO,
DEBUG ((
DEBUG_INFO,
"SEV-ES is enabled, %lu GHCB pages allocated starting at 0x%p\n",
(UINT64)GhcbPageCount, GhcbBase));
(UINT64)GhcbPageCount,
GhcbBase
));
//
// Allocate #VC recursion backup pages. The number of backup pages needed is
// one less than the maximum VC count.
//
GhcbBackupPageCount = mMaxCpuCount * (VMGEXIT_MAXIMUM_VC_COUNT - 1);
GhcbBackupBase = AllocatePages (GhcbBackupPageCount);
GhcbBackupBase = AllocatePages (GhcbBackupPageCount);
ASSERT (GhcbBackupBase != NULL);
GhcbBackupPages = GhcbBackupBase;
@@ -105,9 +108,12 @@ AmdSevEsInitialize (
GhcbBackupPages += EFI_PAGE_SIZE * (VMGEXIT_MAXIMUM_VC_COUNT - 1);
}
DEBUG ((DEBUG_INFO,
DEBUG ((
DEBUG_INFO,
"SEV-ES is enabled, %lu GHCB backup pages allocated starting at 0x%p\n",
(UINT64)GhcbBackupPageCount, GhcbBackupBase));
(UINT64)GhcbBackupPageCount,
GhcbBackupBase
));
AsmWriteMsr64 (MSR_SEV_ES_GHCB, GhcbBasePa);
@@ -120,11 +126,11 @@ AmdSevEsInitialize (
//
AsmReadGdtr (&Gdtr);
Gdt = AllocatePages (EFI_SIZE_TO_PAGES ((UINTN) Gdtr.Limit + 1));
Gdt = AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Gdtr.Limit + 1));
ASSERT (Gdt != NULL);
CopyMem (Gdt, (VOID *) Gdtr.Base, Gdtr.Limit + 1);
Gdtr.Base = (UINTN) Gdt;
CopyMem (Gdt, (VOID *)Gdtr.Base, Gdtr.Limit + 1);
Gdtr.Base = (UINTN)Gdt;
AsmWriteGdtr (&Gdtr);
}
@@ -139,8 +145,8 @@ AmdSevInitialize (
VOID
)
{
UINT64 EncryptionMask;
RETURN_STATUS PcdStatus;
UINT64 EncryptionMask;
RETURN_STATUS PcdStatus;
//
// Check if SEV is enabled
@@ -153,7 +159,7 @@ AmdSevInitialize (
// Set Memory Encryption Mask PCD
//
EncryptionMask = MemEncryptSevGetEncryptionMask ();
PcdStatus = PcdSet64S (PcdPteMemoryEncryptionAddressOrMask, EncryptionMask);
PcdStatus = PcdSet64S (PcdPteMemoryEncryptionAddressOrMask, EncryptionMask);
ASSERT_RETURN_ERROR (PcdStatus);
DEBUG ((DEBUG_INFO, "SEV is enabled (mask 0x%lx)\n", EncryptionMask));
@@ -176,9 +182,9 @@ AmdSevInitialize (
// hypervisor.
//
if (FeaturePcdGet (PcdSmmSmramRequire) && (mBootMode != BOOT_ON_S3_RESUME)) {
RETURN_STATUS LocateMapStatus;
UINTN MapPagesBase;
UINTN MapPagesCount;
RETURN_STATUS LocateMapStatus;
UINTN MapPagesBase;
UINTN MapPagesCount;
LocateMapStatus = MemEncryptSevLocateInitialSmramSaveStateMapPages (
&MapPagesBase,

36
OvmfPkg/PlatformPei/ClearCache.c
View File

@@ -29,7 +29,7 @@ STATIC
VOID
EFIAPI
ClearCache (
IN OUT VOID *WorkSpace
IN OUT VOID *WorkSpace
)
{
WriteBackInvalidateDataCache ();
@@ -56,8 +56,8 @@ ClearCacheOnMpServicesAvailable (
IN VOID *Ppi
)
{
EFI_PEI_MP_SERVICES_PPI *MpServices;
EFI_STATUS Status;
EFI_PEI_MP_SERVICES_PPI *MpServices;
EFI_STATUS Status;
DEBUG ((DEBUG_INFO, "%a: %a\n", gEfiCallerBaseName, __FUNCTION__));
@@ -65,15 +65,15 @@ ClearCacheOnMpServicesAvailable (
// Clear cache on all the APs in parallel.
//
MpServices = Ppi;
Status = MpServices->StartupAllAPs (
(CONST EFI_PEI_SERVICES **)PeiServices,
MpServices,
ClearCache, // Procedure
FALSE, // SingleThread
0, // TimeoutInMicroSeconds: inf.
NULL // ProcedureArgument
);
if (EFI_ERROR (Status) && Status != EFI_NOT_STARTED) {
Status = MpServices->StartupAllAPs (
(CONST EFI_PEI_SERVICES **)PeiServices,
MpServices,
ClearCache, // Procedure
FALSE, // SingleThread
0, // TimeoutInMicroSeconds: inf.
NULL // ProcedureArgument
);
if (EFI_ERROR (Status) && (Status != EFI_NOT_STARTED)) {
DEBUG ((DEBUG_ERROR, "%a: StartupAllAps(): %r\n", __FUNCTION__, Status));
return Status;
}
@@ -89,7 +89,7 @@ ClearCacheOnMpServicesAvailable (
// Notification object for registering the callback, for when
// EFI_PEI_MP_SERVICES_PPI becomes available.
//
STATIC CONST EFI_PEI_NOTIFY_DESCRIPTOR mMpServicesNotify = {
STATIC CONST EFI_PEI_NOTIFY_DESCRIPTOR mMpServicesNotify = {
EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | // Flags
EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
&gEfiPeiMpServicesPpiGuid, // Guid
@@ -101,11 +101,15 @@ InstallClearCacheCallback (
VOID
)
{
EFI_STATUS Status;
EFI_STATUS Status;
Status = PeiServicesNotifyPpi (&mMpServicesNotify);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: failed to set up MP Services callback: %r\n",
__FUNCTION__, Status));
DEBUG ((
DEBUG_ERROR,
"%a: failed to set up MP Services callback: %r\n",
__FUNCTION__,
Status
));
}
}

13
OvmfPkg/PlatformPei/Cmos.c
View File

@@ -6,7 +6,6 @@
**/
#include "Cmos.h"
#include "Library/IoLib.h"
@@ -24,14 +23,13 @@
UINT8
EFIAPI
CmosRead8 (
IN UINTN Index
IN UINTN Index
)
{
IoWrite8 (0x70, (UINT8) Index);
IoWrite8 (0x70, (UINT8)Index);
return IoRead8 (0x71);
}
/**
Writes 8-bits of CMOS data.
@@ -47,12 +45,11 @@ CmosRead8 (
UINT8
EFIAPI
CmosWrite8 (
IN UINTN Index,
IN UINT8 Value
IN UINTN Index,
IN UINT8 Value
)
{
IoWrite8 (0x70, (UINT8) Index);
IoWrite8 (0x70, (UINT8)Index);
IoWrite8 (0x71, Value);
return Value;
}

8
OvmfPkg/PlatformPei/Cmos.h
View File

@@ -23,7 +23,7 @@
UINT8
EFIAPI
CmosRead8 (
IN UINTN Index
IN UINTN Index
);
/**
@@ -41,10 +41,8 @@ CmosRead8 (
UINT8
EFIAPI
CmosWrite8 (
IN UINTN Index,
IN UINT8 Value
IN UINTN Index,
IN UINT8 Value
);
#endif

52
OvmfPkg/PlatformPei/FeatureControl.c
View File

@@ -18,7 +18,7 @@
//
// The value to be written to the Feature Control MSR, retrieved from fw_cfg.
//
STATIC UINT64 mFeatureControlValue;
STATIC UINT64 mFeatureControlValue;
/**
Write the Feature Control MSR on an Application Processor or the Boot
@@ -34,7 +34,7 @@ STATIC
VOID
EFIAPI
WriteFeatureControl (
IN OUT VOID *WorkSpace
IN OUT VOID *WorkSpace
)
{
AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, mFeatureControlValue);
@@ -60,8 +60,8 @@ OnMpServicesAvailable (
IN VOID *Ppi
)
{
EFI_PEI_MP_SERVICES_PPI *MpServices;
EFI_STATUS Status;
EFI_PEI_MP_SERVICES_PPI *MpServices;
EFI_STATUS Status;
DEBUG ((DEBUG_VERBOSE, "%a: %a\n", gEfiCallerBaseName, __FUNCTION__));
@@ -69,15 +69,15 @@ OnMpServicesAvailable (
// Write the MSR on all the APs in parallel.
//
MpServices = Ppi;
Status = MpServices->StartupAllAPs (
(CONST EFI_PEI_SERVICES **)PeiServices,
MpServices,
WriteFeatureControl, // Procedure
FALSE, // SingleThread
0, // TimeoutInMicroSeconds: inf.
NULL // ProcedureArgument
);
if (EFI_ERROR (Status) && Status != EFI_NOT_STARTED) {
Status = MpServices->StartupAllAPs (
(CONST EFI_PEI_SERVICES **)PeiServices,
MpServices,
WriteFeatureControl, // Procedure
FALSE, // SingleThread
0, // TimeoutInMicroSeconds: inf.
NULL // ProcedureArgument
);
if (EFI_ERROR (Status) && (Status != EFI_NOT_STARTED)) {
DEBUG ((DEBUG_ERROR, "%a: StartupAllAps(): %r\n", __FUNCTION__, Status));
return Status;
}
@@ -93,7 +93,7 @@ OnMpServicesAvailable (
// Notification object for registering the callback, for when
// EFI_PEI_MP_SERVICES_PPI becomes available.
//
STATIC CONST EFI_PEI_NOTIFY_DESCRIPTOR mMpServicesNotify = {
STATIC CONST EFI_PEI_NOTIFY_DESCRIPTOR mMpServicesNotify = {
EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | // Flags
EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
&gEfiPeiMpServicesPpiGuid, // Guid
@@ -105,24 +105,32 @@ InstallFeatureControlCallback (
VOID
)
{
EFI_STATUS Status;
FIRMWARE_CONFIG_ITEM FwCfgItem;
UINTN FwCfgSize;
EFI_STATUS Status;
FIRMWARE_CONFIG_ITEM FwCfgItem;
UINTN FwCfgSize;
Status = QemuFwCfgFindFile ("etc/msr_feature_control", &FwCfgItem,
&FwCfgSize);
if (EFI_ERROR (Status) || FwCfgSize != sizeof mFeatureControlValue) {
Status = QemuFwCfgFindFile (
"etc/msr_feature_control",
&FwCfgItem,
&FwCfgSize
);
if (EFI_ERROR (Status) || (FwCfgSize != sizeof mFeatureControlValue)) {
//
// Nothing to do.
//
return;
}
QemuFwCfgSelectItem (FwCfgItem);
QemuFwCfgReadBytes (sizeof mFeatureControlValue, &mFeatureControlValue);
Status = PeiServicesNotifyPpi (&mMpServicesNotify);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: failed to set up MP Services callback: %r\n",
__FUNCTION__, Status));
DEBUG ((
DEBUG_ERROR,
"%a: failed to set up MP Services callback: %r\n",
__FUNCTION__,
Status
));
}
}

8
OvmfPkg/PlatformPei/Fv.c
View File

@@ -13,7 +13,6 @@
#include <Library/PeiServicesLib.h>
#include <Library/PcdLib.h>
/**
Publish PEI & DXE (Decompressed) Memory based FVs to let PEI
and DXE know about them.
@@ -26,7 +25,7 @@ PeiFvInitialization (
VOID
)
{
BOOLEAN SecureS3Needed;
BOOLEAN SecureS3Needed;
DEBUG ((DEBUG_INFO, "Platform PEI Firmware Volume Initialization\n"));
@@ -67,7 +66,7 @@ PeiFvInitialization (
// of DXEFV, so let's keep away the OS from there too.
//
if (SecureS3Needed) {
UINT32 DxeMemFvEnd;
UINT32 DxeMemFvEnd;
DxeMemFvEnd = PcdGet32 (PcdOvmfDxeMemFvBase) +
PcdGet32 (PcdOvmfDxeMemFvSize);
@@ -83,7 +82,7 @@ PeiFvInitialization (
//
PeiServicesInstallFvInfoPpi (
NULL,
(VOID *)(UINTN) PcdGet32 (PcdOvmfDxeMemFvBase),
(VOID *)(UINTN)PcdGet32 (PcdOvmfDxeMemFvBase),
PcdGet32 (PcdOvmfDxeMemFvSize),
NULL,
NULL
@@ -91,4 +90,3 @@ PeiFvInitialization (
return EFI_SUCCESS;
}

354
OvmfPkg/PlatformPei/MemDetect.c
View File

@@ -39,24 +39,24 @@ Module Name:
#include "Platform.h"
#include "Cmos.h"
UINT8 mPhysMemAddressWidth;
UINT8 mPhysMemAddressWidth;
STATIC UINT32 mS3AcpiReservedMemoryBase;
STATIC UINT32 mS3AcpiReservedMemorySize;
STATIC UINT32 mS3AcpiReservedMemoryBase;
STATIC UINT32 mS3AcpiReservedMemorySize;
STATIC UINT16 mQ35TsegMbytes;
STATIC UINT16 mQ35TsegMbytes;
BOOLEAN mQ35SmramAtDefaultSmbase;
BOOLEAN mQ35SmramAtDefaultSmbase;
UINT32 mQemuUc32Base;
UINT32 mQemuUc32Base;
VOID
Q35TsegMbytesInitialization (
VOID
)
{
UINT16 ExtendedTsegMbytes;
RETURN_STATUS PcdStatus;
UINT16 ExtendedTsegMbytes;
RETURN_STATUS PcdStatus;
ASSERT (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);
@@ -94,46 +94,53 @@ Q35TsegMbytesInitialization (
mQ35TsegMbytes = ExtendedTsegMbytes;
}
VOID
Q35SmramAtDefaultSmbaseInitialization (
VOID
)
{
RETURN_STATUS PcdStatus;
RETURN_STATUS PcdStatus;
ASSERT (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);
mQ35SmramAtDefaultSmbase = FALSE;
if (FeaturePcdGet (PcdCsmEnable)) {
DEBUG ((DEBUG_INFO, "%a: SMRAM at default SMBASE not checked due to CSM\n",
__FUNCTION__));
DEBUG ((
DEBUG_INFO,
"%a: SMRAM at default SMBASE not checked due to CSM\n",
__FUNCTION__
));
} else {
UINTN CtlReg;
UINT8 CtlRegVal;
UINTN CtlReg;
UINT8 CtlRegVal;
CtlReg = DRAMC_REGISTER_Q35 (MCH_DEFAULT_SMBASE_CTL);
PciWrite8 (CtlReg, MCH_DEFAULT_SMBASE_QUERY);
CtlRegVal = PciRead8 (CtlReg);
CtlRegVal = PciRead8 (CtlReg);
mQ35SmramAtDefaultSmbase = (BOOLEAN)(CtlRegVal ==
MCH_DEFAULT_SMBASE_IN_RAM);
DEBUG ((DEBUG_INFO, "%a: SMRAM at default SMBASE %a\n", __FUNCTION__,
mQ35SmramAtDefaultSmbase ? "found" : "not found"));
DEBUG ((
DEBUG_INFO,
"%a: SMRAM at default SMBASE %a\n",
__FUNCTION__,
mQ35SmramAtDefaultSmbase ? "found" : "not found"
));
}
PcdStatus = PcdSetBoolS (PcdQ35SmramAtDefaultSmbase,
mQ35SmramAtDefaultSmbase);
PcdStatus = PcdSetBoolS (
PcdQ35SmramAtDefaultSmbase,
mQ35SmramAtDefaultSmbase
);
ASSERT_RETURN_ERROR (PcdStatus);
}
VOID
QemuUc32BaseInitialization (
VOID
)
{
UINT32 LowerMemorySize;
UINT32 Uc32Size;
UINT32 LowerMemorySize;
UINT32 Uc32Size;
if (mHostBridgeDevId == 0xffff /* microvm */) {
return;
@@ -159,8 +166,8 @@ QemuUc32BaseInitialization (
// while keeping the end affixed to 4GB. This will round the base up.
//
LowerMemorySize = GetSystemMemorySizeBelow4gb ();
Uc32Size = GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize));
mQemuUc32Base = (UINT32)(SIZE_4GB - Uc32Size);
Uc32Size = GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize));
mQemuUc32Base = (UINT32)(SIZE_4GB - Uc32Size);
//
// Assuming that LowerMemorySize is at least 1 byte, Uc32Size is at most 2GB.
// Therefore mQemuUc32Base is at least 2GB.
@@ -168,13 +175,18 @@ QemuUc32BaseInitialization (
ASSERT (mQemuUc32Base >= BASE_2GB);
if (mQemuUc32Base != LowerMemorySize) {
DEBUG ((DEBUG_VERBOSE, "%a: rounded UC32 base from 0x%x up to 0x%x, for "
"an UC32 size of 0x%x\n", __FUNCTION__, LowerMemorySize, mQemuUc32Base,
Uc32Size));
DEBUG ((
DEBUG_VERBOSE,
"%a: rounded UC32 base from 0x%x up to 0x%x, for "
"an UC32 size of 0x%x\n",
__FUNCTION__,
LowerMemorySize,
mQemuUc32Base,
Uc32Size
));
}
}
/**
Iterate over the RAM entries in QEMU's fw_cfg E820 RAM map that start outside
of the 32-bit address range.
@@ -204,19 +216,20 @@ QemuUc32BaseInitialization (
STATIC
EFI_STATUS
ScanOrAdd64BitE820Ram (
OUT UINT64 *MaxAddress OPTIONAL
OUT UINT64 *MaxAddress OPTIONAL
)
{
EFI_STATUS Status;
FIRMWARE_CONFIG_ITEM FwCfgItem;
UINTN FwCfgSize;
EFI_E820_ENTRY64 E820Entry;
UINTN Processed;
EFI_STATUS Status;
FIRMWARE_CONFIG_ITEM FwCfgItem;
UINTN FwCfgSize;
EFI_E820_ENTRY64 E820Entry;
UINTN Processed;
Status = QemuFwCfgFindFile ("etc/e820", &FwCfgItem, &FwCfgSize);
if (EFI_ERROR (Status)) {
return Status;
}
if (FwCfgSize % sizeof E820Entry != 0) {
return EFI_PROTOCOL_ERROR;
}
@@ -236,18 +249,19 @@ ScanOrAdd64BitE820Ram (
E820Entry.Length,
E820Entry.Type
));
if (E820Entry.Type == EfiAcpiAddressRangeMemory &&
E820Entry.BaseAddr >= BASE_4GB) {
if ((E820Entry.Type == EfiAcpiAddressRangeMemory) &&
(E820Entry.BaseAddr >= BASE_4GB))
{
if (MaxAddress == NULL) {
UINT64 Base;
UINT64 End;
UINT64 Base;
UINT64 End;
//
// Round up the start address, and round down the end address.
//
Base = ALIGN_VALUE (E820Entry.BaseAddr, (UINT64)EFI_PAGE_SIZE);
End = (E820Entry.BaseAddr + E820Entry.Length) &
~(UINT64)EFI_PAGE_MASK;
End = (E820Entry.BaseAddr + E820Entry.Length) &
~(UINT64)EFI_PAGE_MASK;
if (Base < End) {
AddMemoryRangeHob (Base, End);
DEBUG ((
@@ -259,7 +273,7 @@ ScanOrAdd64BitE820Ram (
));
}
} else {
UINT64 Candidate;
UINT64 Candidate;
Candidate = E820Entry.BaseAddr + E820Entry.Length;
if (Candidate > *MaxAddress) {
@@ -274,17 +288,17 @@ ScanOrAdd64BitE820Ram (
}
}
}
return EFI_SUCCESS;
}
UINT32
GetSystemMemorySizeBelow4gb (
VOID
)
{
UINT8 Cmos0x34;
UINT8 Cmos0x35;
UINT8 Cmos0x34;
UINT8 Cmos0x35;
//
// CMOS 0x34/0x35 specifies the system memory above 16 MB.
@@ -295,20 +309,19 @@ GetSystemMemorySizeBelow4gb (
// into the calculation to get the total memory size.
//
Cmos0x34 = (UINT8) CmosRead8 (0x34);
Cmos0x35 = (UINT8) CmosRead8 (0x35);
Cmos0x34 = (UINT8)CmosRead8 (0x34);
Cmos0x35 = (UINT8)CmosRead8 (0x35);
return (UINT32) (((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB);
return (UINT32)(((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB);
}
STATIC
UINT64
GetSystemMemorySizeAbove4gb (
)
{
UINT32 Size;
UINTN CmosIndex;
UINT32 Size;
UINTN CmosIndex;
//
// CMOS 0x5b-0x5d specifies the system memory above 4GB MB.
@@ -320,13 +333,12 @@ GetSystemMemorySizeAbove4gb (
Size = 0;
for (CmosIndex = 0x5d; CmosIndex >= 0x5b; CmosIndex--) {
Size = (UINT32) (Size << 8) + (UINT32) CmosRead8 (CmosIndex);
Size = (UINT32)(Size << 8) + (UINT32)CmosRead8 (CmosIndex);
}
return LShiftU64 (Size, 16);
}
/**
Return the highest address that DXE could possibly use, plus one.
**/
@@ -336,14 +348,14 @@ GetFirstNonAddress (
VOID
)
{
UINT64 FirstNonAddress;
UINT64 Pci64Base, Pci64Size;
UINT32 FwCfgPciMmio64Mb;
EFI_STATUS Status;
FIRMWARE_CONFIG_ITEM FwCfgItem;
UINTN FwCfgSize;
UINT64 HotPlugMemoryEnd;
RETURN_STATUS PcdStatus;
UINT64 FirstNonAddress;
UINT64 Pci64Base, Pci64Size;
UINT32 FwCfgPciMmio64Mb;
EFI_STATUS Status;
FIRMWARE_CONFIG_ITEM FwCfgItem;
UINTN FwCfgSize;
UINT64 HotPlugMemoryEnd;
RETURN_STATUS PcdStatus;
//
// set FirstNonAddress to suppress incorrect compiler/analyzer warnings
@@ -367,11 +379,12 @@ GetFirstNonAddress (
// resources to 32-bit anyway. See DegradeResource() in
// "PciResourceSupport.c".
//
#ifdef MDE_CPU_IA32
#ifdef MDE_CPU_IA32
if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
return FirstNonAddress;
}
#endif
#endif
//
// Otherwise, in order to calculate the highest address plus one, we must
@@ -386,31 +399,40 @@ GetFirstNonAddress (
// As signaled by the "X-" prefix, this knob is experimental, and might go
// away at any time.
//
Status = QemuFwCfgParseUint32 ("opt/ovmf/X-PciMmio64Mb", FALSE,
&FwCfgPciMmio64Mb);
Status = QemuFwCfgParseUint32 (
"opt/ovmf/X-PciMmio64Mb",
FALSE,
&FwCfgPciMmio64Mb
);
switch (Status) {
case EFI_UNSUPPORTED:
case EFI_NOT_FOUND:
break;
case EFI_SUCCESS:
if (FwCfgPciMmio64Mb <= 0x1000000) {
Pci64Size = LShiftU64 (FwCfgPciMmio64Mb, 20);
case EFI_UNSUPPORTED:
case EFI_NOT_FOUND:
break;
}
case EFI_SUCCESS:
if (FwCfgPciMmio64Mb <= 0x1000000) {
Pci64Size = LShiftU64 (FwCfgPciMmio64Mb, 20);
break;
}
//
// fall through
//
default:
DEBUG ((DEBUG_WARN,
"%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\n",
__FUNCTION__));
break;
default:
DEBUG ((
DEBUG_WARN,
"%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\n",
__FUNCTION__
));
break;
}
if (Pci64Size == 0) {
if (mBootMode != BOOT_ON_S3_RESUME) {
DEBUG ((DEBUG_INFO, "%a: disabling 64-bit PCI host aperture\n",
__FUNCTION__));
DEBUG ((
DEBUG_INFO,
"%a: disabling 64-bit PCI host aperture\n",
__FUNCTION__
));
PcdStatus = PcdSet64S (PcdPciMmio64Size, 0);
ASSERT_RETURN_ERROR (PcdStatus);
}
@@ -429,13 +451,20 @@ GetFirstNonAddress (
// starts right at the end of the memory above 4GB. The 64-bit PCI host
// aperture must be placed above it.
//
Status = QemuFwCfgFindFile ("etc/reserved-memory-end", &FwCfgItem,
&FwCfgSize);
if (!EFI_ERROR (Status) && FwCfgSize == sizeof HotPlugMemoryEnd) {
Status = QemuFwCfgFindFile (
"etc/reserved-memory-end",
&FwCfgItem,
&FwCfgSize
);
if (!EFI_ERROR (Status) && (FwCfgSize == sizeof HotPlugMemoryEnd)) {
QemuFwCfgSelectItem (FwCfgItem);
QemuFwCfgReadBytes (FwCfgSize, &HotPlugMemoryEnd);
DEBUG ((DEBUG_VERBOSE, "%a: HotPlugMemoryEnd=0x%Lx\n", __FUNCTION__,
HotPlugMemoryEnd));
DEBUG ((
DEBUG_VERBOSE,
"%a: HotPlugMemoryEnd=0x%Lx\n",
__FUNCTION__,
HotPlugMemoryEnd
));
ASSERT (HotPlugMemoryEnd >= FirstNonAddress);
FirstNonAddress = HotPlugMemoryEnd;
@@ -467,8 +496,13 @@ GetFirstNonAddress (
PcdStatus = PcdSet64S (PcdPciMmio64Size, Pci64Size);
ASSERT_RETURN_ERROR (PcdStatus);
DEBUG ((DEBUG_INFO, "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",
__FUNCTION__, Pci64Base, Pci64Size));
DEBUG ((
DEBUG_INFO,
"%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",
__FUNCTION__,
Pci64Base,
Pci64Size
));
}
//
@@ -478,7 +512,6 @@ GetFirstNonAddress (
return FirstNonAddress;
}
/**
Initialize the mPhysMemAddressWidth variable, based on guest RAM size.
**/
@@ -487,7 +520,7 @@ AddressWidthInitialization (
VOID
)
{
UINT64 FirstNonAddress;
UINT64 FirstNonAddress;
//
// As guest-physical memory size grows, the permanent PEI RAM requirements
@@ -515,10 +548,10 @@ AddressWidthInitialization (
if (mPhysMemAddressWidth <= 36) {
mPhysMemAddressWidth = 36;
}
ASSERT (mPhysMemAddressWidth <= 48);
}
/**
Calculate the cap for the permanent PEI memory.
**/
@@ -528,21 +561,22 @@ GetPeiMemoryCap (
VOID
)
{
BOOLEAN Page1GSupport;
UINT32 RegEax;
UINT32 RegEdx;
UINT32 Pml4Entries;
UINT32 PdpEntries;
UINTN TotalPages;
BOOLEAN Page1GSupport;
UINT32 RegEax;
UINT32 RegEdx;
UINT32 Pml4Entries;
UINT32 PdpEntries;
UINTN TotalPages;
//
// If DXE is 32-bit, then just return the traditional 64 MB cap.
//
#ifdef MDE_CPU_IA32
#ifdef MDE_CPU_IA32
if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
return SIZE_64MB;
}
#endif
#endif
//
// Dependent on physical address width, PEI memory allocations can be
@@ -563,7 +597,7 @@ GetPeiMemoryCap (
if (mPhysMemAddressWidth <= 39) {
Pml4Entries = 1;
PdpEntries = 1 << (mPhysMemAddressWidth - 30);
PdpEntries = 1 << (mPhysMemAddressWidth - 30);
ASSERT (PdpEntries <= 0x200);
} else {
Pml4Entries = 1 << (mPhysMemAddressWidth - 39);
@@ -572,7 +606,7 @@ GetPeiMemoryCap (
}
TotalPages = Page1GSupport ? Pml4Entries + 1 :
(PdpEntries + 1) * Pml4Entries + 1;
(PdpEntries + 1) * Pml4Entries + 1;
ASSERT (TotalPages <= 0x40201);
//
@@ -583,7 +617,6 @@ GetPeiMemoryCap (
return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB);
}
/**
Publish PEI core memory
@@ -595,11 +628,11 @@ PublishPeiMemory (
VOID
)
{
EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS MemoryBase;
UINT64 MemorySize;
UINT32 LowerMemorySize;
UINT32 PeiMemoryCap;
EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS MemoryBase;
UINT64 MemorySize;
UINT32 LowerMemorySize;
UINT32 PeiMemoryCap;
LowerMemorySize = GetSystemMemorySizeBelow4gb ();
if (FeaturePcdGet (PcdSmmSmramRequire)) {
@@ -616,10 +649,10 @@ PublishPeiMemory (
//
if (mS3Supported) {
mS3AcpiReservedMemorySize = SIZE_512KB +
mMaxCpuCount *
PcdGet32 (PcdCpuApStackSize);
mMaxCpuCount *
PcdGet32 (PcdCpuApStackSize);
mS3AcpiReservedMemoryBase = LowerMemorySize - mS3AcpiReservedMemorySize;
LowerMemorySize = mS3AcpiReservedMemoryBase;
LowerMemorySize = mS3AcpiReservedMemoryBase;
}
if (mBootMode == BOOT_ON_S3_RESUME) {
@@ -627,8 +660,13 @@ PublishPeiMemory (
MemorySize = mS3AcpiReservedMemorySize;
} else {
PeiMemoryCap = GetPeiMemoryCap ();
DEBUG ((DEBUG_INFO, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",
__FUNCTION__, mPhysMemAddressWidth, PeiMemoryCap >> 10));
DEBUG ((
DEBUG_INFO,
"%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",
__FUNCTION__,
mPhysMemAddressWidth,
PeiMemoryCap >> 10
));
//
// Determine the range of memory to use during PEI
@@ -641,8 +679,8 @@ PublishPeiMemory (
// shouldn't overlap with that HOB.
//
MemoryBase = mS3Supported && FeaturePcdGet (PcdSmmSmramRequire) ?
PcdGet32 (PcdOvmfDecompressionScratchEnd) :
PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);
PcdGet32 (PcdOvmfDecompressionScratchEnd) :
PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);
MemorySize = LowerMemorySize - MemoryBase;
if (MemorySize > PeiMemoryCap) {
MemoryBase = LowerMemorySize - PeiMemoryCap;
@@ -662,13 +700,12 @@ PublishPeiMemory (
//
// Publish this memory to the PEI Core
//
Status = PublishSystemMemory(MemoryBase, MemorySize);
Status = PublishSystemMemory (MemoryBase, MemorySize);
ASSERT_EFI_ERROR (Status);
return Status;
}
STATIC
VOID
QemuInitializeRamBelow1gb (
@@ -677,20 +714,24 @@ QemuInitializeRamBelow1gb (
{
if (FeaturePcdGet (PcdSmmSmramRequire) && mQ35SmramAtDefaultSmbase) {
AddMemoryRangeHob (0, SMM_DEFAULT_SMBASE);
AddReservedMemoryBaseSizeHob (SMM_DEFAULT_SMBASE, MCH_DEFAULT_SMBASE_SIZE,
TRUE /* Cacheable */);
AddReservedMemoryBaseSizeHob (
SMM_DEFAULT_SMBASE,
MCH_DEFAULT_SMBASE_SIZE,
TRUE /* Cacheable */
);
STATIC_ASSERT (
SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE < BASE_512KB + BASE_128KB,
"end of SMRAM at default SMBASE ends at, or exceeds, 640KB"
);
AddMemoryRangeHob (SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE,
BASE_512KB + BASE_128KB);
AddMemoryRangeHob (
SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE,
BASE_512KB + BASE_128KB
);
} else {
AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);
}
}
/**
Peform Memory Detection for QEMU / KVM
@@ -701,10 +742,10 @@ QemuInitializeRam (
VOID
)
{
UINT64 LowerMemorySize;
UINT64 UpperMemorySize;
MTRR_SETTINGS MtrrSettings;
EFI_STATUS Status;
UINT64 LowerMemorySize;
UINT64 UpperMemorySize;
MTRR_SETTINGS MtrrSettings;
EFI_STATUS Status;
DEBUG ((DEBUG_INFO, "%a called\n", __FUNCTION__));
@@ -743,12 +784,15 @@ QemuInitializeRam (
QemuInitializeRamBelow1gb ();
if (FeaturePcdGet (PcdSmmSmramRequire)) {
UINT32 TsegSize;
UINT32 TsegSize;
TsegSize = mQ35TsegMbytes * SIZE_1MB;
AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize);
AddReservedMemoryBaseSizeHob (LowerMemorySize - TsegSize, TsegSize,
TRUE);
AddReservedMemoryBaseSizeHob (
LowerMemorySize - TsegSize,
TsegSize,
TRUE
);
} else {
AddMemoryRangeHob (BASE_1MB, LowerMemorySize);
}
@@ -759,7 +803,7 @@ QemuInitializeRam (
// memory size read from the CMOS.
//
Status = ScanOrAdd64BitE820Ram (NULL);
if (EFI_ERROR (Status) && UpperMemorySize != 0) {
if (EFI_ERROR (Status) && (UpperMemorySize != 0)) {
AddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);
}
}
@@ -796,16 +840,22 @@ QemuInitializeRam (
//
// Set memory range from 640KB to 1MB to uncacheable
//
Status = MtrrSetMemoryAttribute (BASE_512KB + BASE_128KB,
BASE_1MB - (BASE_512KB + BASE_128KB), CacheUncacheable);
Status = MtrrSetMemoryAttribute (
BASE_512KB + BASE_128KB,
BASE_1MB - (BASE_512KB + BASE_128KB),
CacheUncacheable
);
ASSERT_EFI_ERROR (Status);
//
// Set the memory range from the start of the 32-bit MMIO area (32-bit PCI
// MMIO aperture on i440fx, PCIEXBAR on q35) to 4GB as uncacheable.
//
Status = MtrrSetMemoryAttribute (mQemuUc32Base, SIZE_4GB - mQemuUc32Base,
CacheUncacheable);
Status = MtrrSetMemoryAttribute (
mQemuUc32Base,
SIZE_4GB - mQemuUc32Base,
CacheUncacheable
);
ASSERT_EFI_ERROR (Status);
}
}
@@ -821,7 +871,7 @@ InitializeRamRegions (
{
QemuInitializeRam ();
if (mS3Supported && mBootMode != BOOT_ON_S3_RESUME) {
if (mS3Supported && (mBootMode != BOOT_ON_S3_RESUME)) {
//
// This is the memory range that will be used for PEI on S3 resume
//
@@ -851,7 +901,7 @@ InitializeRamRegions (
EfiACPIMemoryNVS
);
#ifdef MDE_CPU_X64
#ifdef MDE_CPU_X64
//
// Reserve the initial page tables built by the reset vector code.
//
@@ -859,8 +909,8 @@ InitializeRamRegions (
// resume, it must be reserved as ACPI NVS.
//
BuildMemoryAllocationHob (
(EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfSecPageTablesBase),
(UINT64)(UINTN) PcdGet32 (PcdOvmfSecPageTablesSize),
(EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecPageTablesBase),
(UINT64)(UINTN)PcdGet32 (PcdOvmfSecPageTablesSize),
EfiACPIMemoryNVS
);
@@ -875,22 +925,23 @@ InitializeRamRegions (
// resume, it must be reserved as ACPI NVS.
//
BuildMemoryAllocationHob (
(EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfSecGhcbPageTableBase),
(UINT64)(UINTN) PcdGet32 (PcdOvmfSecGhcbPageTableSize),
(EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecGhcbPageTableBase),
(UINT64)(UINTN)PcdGet32 (PcdOvmfSecGhcbPageTableSize),
EfiACPIMemoryNVS
);
BuildMemoryAllocationHob (
(EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfSecGhcbBase),
(UINT64)(UINTN) PcdGet32 (PcdOvmfSecGhcbSize),
(EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecGhcbBase),
(UINT64)(UINTN)PcdGet32 (PcdOvmfSecGhcbSize),
EfiACPIMemoryNVS
);
BuildMemoryAllocationHob (
(EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfSecGhcbBackupBase),
(UINT64)(UINTN) PcdGet32 (PcdOvmfSecGhcbBackupSize),
(EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecGhcbBackupBase),
(UINT64)(UINTN)PcdGet32 (PcdOvmfSecGhcbBackupSize),
EfiACPIMemoryNVS
);
}
#endif
#endif
}
if (mBootMode != BOOT_ON_S3_RESUME) {
@@ -906,18 +957,18 @@ InitializeRamRegions (
// such that they would overlap the LockBox storage.
//
ZeroMem (
(VOID*)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),
(UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize)
(VOID *)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase),
(UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize)
);
BuildMemoryAllocationHob (
(EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),
(UINT64)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize),
(EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase),
(UINT64)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize),
mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData
);
}
if (FeaturePcdGet (PcdSmmSmramRequire)) {
UINT32 TsegSize;
UINT32 TsegSize;
//
// Make sure the TSEG area that we reported as a reserved memory resource
@@ -925,7 +976,7 @@ InitializeRamRegions (
//
TsegSize = mQ35TsegMbytes * SIZE_1MB;
BuildMemoryAllocationHob (
GetSystemMemorySizeBelow4gb() - TsegSize,
GetSystemMemorySizeBelow4gb () - TsegSize,
TsegSize,
EfiReservedMemoryType
);
@@ -942,7 +993,7 @@ InitializeRamRegions (
}
}
#ifdef MDE_CPU_X64
#ifdef MDE_CPU_X64
if (FixedPcdGet32 (PcdOvmfWorkAreaSize) != 0) {
//
// Reserve the work area.
@@ -955,11 +1006,12 @@ InitializeRamRegions (
// such that they would overlap the work area.
//
BuildMemoryAllocationHob (
(EFI_PHYSICAL_ADDRESS)(UINTN) FixedPcdGet32 (PcdOvmfWorkAreaBase),
(UINT64)(UINTN) FixedPcdGet32 (PcdOvmfWorkAreaSize),
(EFI_PHYSICAL_ADDRESS)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaBase),
(UINT64)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaSize),
mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData
);
}
#endif
#endif
}
}

78
OvmfPkg/PlatformPei/MemTypeInfo.c
View File

@@ -20,13 +20,13 @@
#define MEMORY_TYPE_INFO_DEFAULT(Type) \
{ Type, FixedPcdGet32 (PcdMemoryType ## Type) }
STATIC EFI_MEMORY_TYPE_INFORMATION mMemoryTypeInformation[] = {
STATIC EFI_MEMORY_TYPE_INFORMATION mMemoryTypeInformation[] = {
MEMORY_TYPE_INFO_DEFAULT (EfiACPIMemoryNVS),
MEMORY_TYPE_INFO_DEFAULT (EfiACPIReclaimMemory),
MEMORY_TYPE_INFO_DEFAULT (EfiReservedMemoryType),
MEMORY_TYPE_INFO_DEFAULT (EfiRuntimeServicesCode),
MEMORY_TYPE_INFO_DEFAULT (EfiRuntimeServicesData),
{ EfiMaxMemoryType, 0 }
{ EfiMaxMemoryType, 0}
};
STATIC
@@ -64,28 +64,28 @@ BuildMemTypeInfoHob (
STATIC
VOID
RefreshMemTypeInfo (
IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *ReadOnlyVariable2
IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *ReadOnlyVariable2
)
{
UINTN DataSize;
EFI_MEMORY_TYPE_INFORMATION Entries[EfiMaxMemoryType + 1];
EFI_STATUS Status;
UINTN NumEntries;
UINTN HobRecordIdx;
UINTN DataSize;
EFI_MEMORY_TYPE_INFORMATION Entries[EfiMaxMemoryType + 1];
EFI_STATUS Status;
UINTN NumEntries;
UINTN HobRecordIdx;
//
// Read the MemoryTypeInformation UEFI variable from the
// gEfiMemoryTypeInformationGuid namespace.
//
DataSize = sizeof Entries;
Status = ReadOnlyVariable2->GetVariable (
ReadOnlyVariable2,
EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME,
&gEfiMemoryTypeInformationGuid,
NULL,
&DataSize,
Entries
);
Status = ReadOnlyVariable2->GetVariable (
ReadOnlyVariable2,
EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME,
&gEfiMemoryTypeInformationGuid,
NULL,
&DataSize,
Entries
);
if (EFI_ERROR (Status)) {
//
// If the UEFI variable does not exist (EFI_NOT_FOUND), we can't use it for
@@ -108,10 +108,15 @@ RefreshMemTypeInfo (
// Sanity-check the UEFI variable size against the record size.
//
if (DataSize % sizeof Entries[0] != 0) {
DEBUG ((DEBUG_ERROR, "%a: invalid UEFI variable size %Lu\n", __FUNCTION__,
(UINT64)DataSize));
DEBUG ((
DEBUG_ERROR,
"%a: invalid UEFI variable size %Lu\n",
__FUNCTION__,
(UINT64)DataSize
));
return;
}
NumEntries = DataSize / sizeof Entries[0];
//
@@ -121,10 +126,11 @@ RefreshMemTypeInfo (
//
for (HobRecordIdx = 0;
HobRecordIdx < ARRAY_SIZE (mMemoryTypeInformation) - 1;
HobRecordIdx++) {
EFI_MEMORY_TYPE_INFORMATION *HobRecord;
UINTN Idx;
EFI_MEMORY_TYPE_INFORMATION *VariableRecord;
HobRecordIdx++)
{
EFI_MEMORY_TYPE_INFORMATION *HobRecord;
UINTN Idx;
EFI_MEMORY_TYPE_INFORMATION *VariableRecord;
HobRecord = &mMemoryTypeInformation[HobRecordIdx];
@@ -139,11 +145,17 @@ RefreshMemTypeInfo (
//
// If there is a match, allow the UEFI variable to increase NumberOfPages.
//
if (Idx < NumEntries &&
HobRecord->NumberOfPages < VariableRecord->NumberOfPages) {
DEBUG ((DEBUG_VERBOSE, "%a: Type 0x%x: NumberOfPages 0x%x -> 0x%x\n",
__FUNCTION__, HobRecord->Type, HobRecord->NumberOfPages,
VariableRecord->NumberOfPages));
if ((Idx < NumEntries) &&
(HobRecord->NumberOfPages < VariableRecord->NumberOfPages))
{
DEBUG ((
DEBUG_VERBOSE,
"%a: Type 0x%x: NumberOfPages 0x%x -> 0x%x\n",
__FUNCTION__,
HobRecord->Type,
HobRecord->NumberOfPages,
VariableRecord->NumberOfPages
));
HobRecord->NumberOfPages = VariableRecord->NumberOfPages;
}
@@ -182,7 +194,7 @@ OnReadOnlyVariable2Available (
// Notification object for registering the callback, for when
// EFI_PEI_READ_ONLY_VARIABLE2_PPI becomes available.
//
STATIC CONST EFI_PEI_NOTIFY_DESCRIPTOR mReadOnlyVariable2Notify = {
STATIC CONST EFI_PEI_NOTIFY_DESCRIPTOR mReadOnlyVariable2Notify = {
(EFI_PEI_PPI_DESCRIPTOR_NOTIFY_DISPATCH |
EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), // Flags
&gEfiPeiReadOnlyVariable2PpiGuid, // Guid
@@ -194,7 +206,7 @@ MemTypeInfoInitialization (
VOID
)
{
EFI_STATUS Status;
EFI_STATUS Status;
if (!FeaturePcdGet (PcdSmmSmramRequire)) {
//
@@ -207,8 +219,12 @@ MemTypeInfoInitialization (
Status = PeiServicesNotifyPpi (&mReadOnlyVariable2Notify);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: failed to set up R/O Variable 2 callback: %r\n",
__FUNCTION__, Status));
DEBUG ((
DEBUG_ERROR,
"%a: failed to set up R/O Variable 2 callback: %r\n",
__FUNCTION__,
Status
));
ASSERT (FALSE);
CpuDeadLoop ();
}

242
OvmfPkg/PlatformPei/Platform.c
View File

@@ -40,7 +40,7 @@
#include "Platform.h"
#include "Cmos.h"
EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
{
EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
&gEfiPeiMasterBootModePpiGuid,
@@ -48,27 +48,26 @@ EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
}
};
UINT16 mHostBridgeDevId;
UINT16 mHostBridgeDevId;
EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
BOOLEAN mS3Supported = FALSE;
BOOLEAN mS3Supported = FALSE;
UINT32 mMaxCpuCount;
UINT32 mMaxCpuCount;
VOID
AddIoMemoryBaseSizeHob (
EFI_PHYSICAL_ADDRESS MemoryBase,
UINT64 MemorySize
EFI_PHYSICAL_ADDRESS MemoryBase,
UINT64 MemorySize
)
{
BuildResourceDescriptorHob (
EFI_RESOURCE_MEMORY_MAPPED_IO,
EFI_RESOURCE_ATTRIBUTE_PRESENT |
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
EFI_RESOURCE_ATTRIBUTE_TESTED,
EFI_RESOURCE_ATTRIBUTE_PRESENT |
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
EFI_RESOURCE_ATTRIBUTE_TESTED,
MemoryBase,
MemorySize
);
@@ -76,23 +75,23 @@ AddIoMemoryBaseSizeHob (
VOID
AddReservedMemoryBaseSizeHob (
EFI_PHYSICAL_ADDRESS MemoryBase,
UINT64 MemorySize,
BOOLEAN Cacheable
EFI_PHYSICAL_ADDRESS MemoryBase,
UINT64 MemorySize,
BOOLEAN Cacheable
)
{
BuildResourceDescriptorHob (
EFI_RESOURCE_MEMORY_RESERVED,
EFI_RESOURCE_ATTRIBUTE_PRESENT |
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
(Cacheable ?
EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
0
) |
EFI_RESOURCE_ATTRIBUTE_TESTED,
EFI_RESOURCE_ATTRIBUTE_PRESENT |
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
(Cacheable ?
EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
0
) |
EFI_RESOURCE_ATTRIBUTE_TESTED,
MemoryBase,
MemorySize
);
@@ -100,57 +99,54 @@ AddReservedMemoryBaseSizeHob (
VOID
AddIoMemoryRangeHob (
EFI_PHYSICAL_ADDRESS MemoryBase,
EFI_PHYSICAL_ADDRESS MemoryLimit
EFI_PHYSICAL_ADDRESS MemoryBase,
EFI_PHYSICAL_ADDRESS MemoryLimit
)
{
AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
}
VOID
AddMemoryBaseSizeHob (
EFI_PHYSICAL_ADDRESS MemoryBase,
UINT64 MemorySize
EFI_PHYSICAL_ADDRESS MemoryBase,
UINT64 MemorySize
)
{
BuildResourceDescriptorHob (
EFI_RESOURCE_SYSTEM_MEMORY,
EFI_RESOURCE_ATTRIBUTE_PRESENT |
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
EFI_RESOURCE_ATTRIBUTE_TESTED,
EFI_RESOURCE_ATTRIBUTE_PRESENT |
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
EFI_RESOURCE_ATTRIBUTE_TESTED,
MemoryBase,
MemorySize
);
}
VOID
AddMemoryRangeHob (
EFI_PHYSICAL_ADDRESS MemoryBase,
EFI_PHYSICAL_ADDRESS MemoryLimit
EFI_PHYSICAL_ADDRESS MemoryBase,
EFI_PHYSICAL_ADDRESS MemoryLimit
)
{
AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
}
VOID
MemMapInitialization (
VOID
)
{
UINT64 PciIoBase;
UINT64 PciIoSize;
RETURN_STATUS PcdStatus;
UINT32 TopOfLowRam;
UINT64 PciExBarBase;
UINT32 PciBase;
UINT32 PciSize;
UINT64 PciIoBase;
UINT64 PciIoSize;
RETURN_STATUS PcdStatus;
UINT32 TopOfLowRam;
UINT64 PciExBarBase;
UINT32 PciBase;
UINT32 PciSize;
PciIoBase = 0xC000;
PciIoSize = 0x4000;
@@ -167,7 +163,7 @@ MemMapInitialization (
return;
}
TopOfLowRam = GetSystemMemorySizeBelow4gb ();
TopOfLowRam = GetSystemMemorySizeBelow4gb ();
PciExBarBase = 0;
if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
//
@@ -229,10 +225,14 @@ MemMapInitialization (
// uncacheable reserved memory right here.
//
AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);
BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,
EfiReservedMemoryType);
BuildMemoryAllocationHob (
PciExBarBase,
SIZE_256MB,
EfiReservedMemoryType
);
}
AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
AddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), SIZE_1MB);
//
// On Q35, the IO Port space is available for PCI resource allocations from
@@ -286,8 +286,8 @@ PciExBarInitialization (
)
{
union {
UINT64 Uint64;
UINT32 Uint32[2];
UINT64 Uint64;
UINT32 Uint32[2];
} PciExBarBase;
//
@@ -326,13 +326,13 @@ MiscInitialization (
VOID
)
{
UINTN PmCmd;
UINTN Pmba;
UINT32 PmbaAndVal;
UINT32 PmbaOrVal;
UINTN AcpiCtlReg;
UINT8 AcpiEnBit;
RETURN_STATUS PcdStatus;
UINTN PmCmd;
UINTN Pmba;
UINT32 PmbaAndVal;
UINT32 PmbaOrVal;
UINTN AcpiCtlReg;
UINT8 AcpiEnBit;
RETURN_STATUS PcdStatus;
//
// Disable A20 Mask
@@ -368,16 +368,23 @@ MiscInitialization (
break;
case 0xffff: /* microvm */
DEBUG ((DEBUG_INFO, "%a: microvm\n", __FUNCTION__));
PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId,
MICROVM_PSEUDO_DEVICE_ID);
PcdStatus = PcdSet16S (
PcdOvmfHostBridgePciDevId,
MICROVM_PSEUDO_DEVICE_ID
);
ASSERT_RETURN_ERROR (PcdStatus);
return;
default:
DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
__FUNCTION__, mHostBridgeDevId));
DEBUG ((
DEBUG_ERROR,
"%a: Unknown Host Bridge Device ID: 0x%04x\n",
__FUNCTION__,
mHostBridgeDevId
));
ASSERT (FALSE);
return;
}
PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
ASSERT_RETURN_ERROR (PcdStatus);
@@ -420,17 +427,17 @@ MiscInitialization (
}
}
VOID
BootModeInitialization (
VOID
)
{
EFI_STATUS Status;
EFI_STATUS Status;
if (CmosRead8 (0xF) == 0xFE) {
mBootMode = BOOT_ON_S3_RESUME;
}
CmosWrite8 (0xF, 0x00);
Status = PeiServicesSetBootMode (mBootMode);
@@ -440,13 +447,12 @@ BootModeInitialization (
ASSERT_EFI_ERROR (Status);
}
VOID
ReserveEmuVariableNvStore (
)
{
EFI_PHYSICAL_ADDRESS VariableStore;
RETURN_STATUS PcdStatus;
EFI_PHYSICAL_ADDRESS VariableStore;
RETURN_STATUS PcdStatus;
//
// Allocate storage for NV variables early on so it will be
@@ -456,25 +462,25 @@ ReserveEmuVariableNvStore (
//
VariableStore =
(EFI_PHYSICAL_ADDRESS)(UINTN)
AllocateRuntimePages (
EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))
);
DEBUG ((DEBUG_INFO,
"Reserved variable store memory: 0x%lX; size: %dkb\n",
VariableStore,
(2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
));
AllocateRuntimePages (
EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))
);
DEBUG ((
DEBUG_INFO,
"Reserved variable store memory: 0x%lX; size: %dkb\n",
VariableStore,
(2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
));
PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);
ASSERT_RETURN_ERROR (PcdStatus);
}
VOID
DebugDumpCmos (
VOID
)
{
UINT32 Loop;
UINT32 Loop;
DEBUG ((DEBUG_INFO, "CMOS:\n"));
@@ -482,6 +488,7 @@ DebugDumpCmos (
if ((Loop % 0x10) == 0) {
DEBUG ((DEBUG_INFO, "%02x:", Loop));
}
DEBUG ((DEBUG_INFO, " %02x", CmosRead8 (Loop)));
if ((Loop % 0x10) == 0xf) {
DEBUG ((DEBUG_INFO, "\n"));
@@ -489,27 +496,34 @@ DebugDumpCmos (
}
}
VOID
S3Verification (
VOID
)
{
#if defined (MDE_CPU_X64)
#if defined (MDE_CPU_X64)
if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {
DEBUG ((DEBUG_ERROR,
"%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));
DEBUG ((DEBUG_ERROR,
DEBUG ((
DEBUG_ERROR,
"%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n",
__FUNCTION__
));
DEBUG ((
DEBUG_ERROR,
"%a: Please disable S3 on the QEMU command line (see the README),\n",
__FUNCTION__));
DEBUG ((DEBUG_ERROR,
"%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));
__FUNCTION__
));
DEBUG ((
DEBUG_ERROR,
"%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n",
__FUNCTION__
));
ASSERT (FALSE);
CpuDeadLoop ();
}
#endif
}
#endif
}
VOID
Q35BoardVerification (
@@ -532,7 +546,6 @@ Q35BoardVerification (
CpuDeadLoop ();
}
/**
Fetch the boot CPU count and the possible CPU count from QEMU, and expose
them to UefiCpuPkg modules. Set the mMaxCpuCount variable.
@@ -542,8 +555,8 @@ MaxCpuCountInitialization (
VOID
)
{
UINT16 BootCpuCount;
RETURN_STATUS PcdStatus;
UINT16 BootCpuCount;
RETURN_STATUS PcdStatus;
//
// Try to fetch the boot CPU count.
@@ -566,8 +579,8 @@ MaxCpuCountInitialization (
//
// Now try to fetch the possible CPU count.
//
UINTN CpuHpBase;
UINT32 CmdData2;
UINTN CpuHpBase;
UINT32 CmdData2;
CpuHpBase = ((mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) ?
ICH9_CPU_HOTPLUG_BASE : PIIX4_CPU_HOTPLUG_BASE);
@@ -616,16 +629,19 @@ MaxCpuCountInitialization (
// QEMU doesn't support the modern CPU hotplug interface. Assume that the
// possible CPU count equals the boot CPU count (precluding hotplug).
//
DEBUG ((DEBUG_WARN, "%a: modern CPU hotplug interface unavailable\n",
__FUNCTION__));
DEBUG ((
DEBUG_WARN,
"%a: modern CPU hotplug interface unavailable\n",
__FUNCTION__
));
mMaxCpuCount = BootCpuCount;
} else {
//
// Grab the possible CPU count from the modern CPU hotplug interface.
//
UINT32 Present, Possible, Selected;
UINT32 Present, Possible, Selected;
Present = 0;
Present = 0;
Possible = 0;
//
@@ -637,7 +653,7 @@ MaxCpuCountInitialization (
IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible);
do {
UINT8 CpuStatus;
UINT8 CpuStatus;
//
// Read the status of the currently selected CPU. This will help with a
@@ -647,6 +663,7 @@ MaxCpuCountInitialization (
if ((CpuStatus & QEMU_CPUHP_STAT_ENABLED) != 0) {
++Present;
}
//
// Attempt to select the next CPU.
//
@@ -666,8 +683,14 @@ MaxCpuCountInitialization (
// return the same boot CPU count.
//
if (BootCpuCount != Present) {
DEBUG ((DEBUG_WARN, "%a: QEMU v2.7 reset bug: BootCpuCount=%d "
"Present=%u\n", __FUNCTION__, BootCpuCount, Present));
DEBUG ((
DEBUG_WARN,
"%a: QEMU v2.7 reset bug: BootCpuCount=%d "
"Present=%u\n",
__FUNCTION__,
BootCpuCount,
Present
));
//
// The handling of QemuFwCfgItemSmpCpuCount, across CPU hotplug plus
// platform reset (including S3), was corrected in QEMU commit
@@ -681,8 +704,13 @@ MaxCpuCountInitialization (
}
}
DEBUG ((DEBUG_INFO, "%a: BootCpuCount=%d mMaxCpuCount=%u\n", __FUNCTION__,
BootCpuCount, mMaxCpuCount));
DEBUG ((
DEBUG_INFO,
"%a: BootCpuCount=%d mMaxCpuCount=%u\n",
__FUNCTION__,
BootCpuCount,
mMaxCpuCount
));
ASSERT (BootCpuCount <= mMaxCpuCount);
PcdStatus = PcdSet32S (PcdCpuBootLogicalProcessorNumber, BootCpuCount);
@@ -691,7 +719,6 @@ MaxCpuCountInitialization (
ASSERT_RETURN_ERROR (PcdStatus);
}
/**
Perform Platform PEI initialization.
@@ -708,7 +735,7 @@ InitializePlatform (
IN CONST EFI_PEI_SERVICES **PeiServices
)
{
EFI_STATUS Status;
EFI_STATUS Status;
DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));
@@ -717,7 +744,7 @@ InitializePlatform (
if (QemuFwCfgS3Enabled ()) {
DEBUG ((DEBUG_INFO, "S3 support was detected on QEMU\n"));
mS3Supported = TRUE;
Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);
Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);
ASSERT_EFI_ERROR (Status);
}
@@ -748,6 +775,7 @@ InitializePlatform (
if (!FeaturePcdGet (PcdSmmSmramRequire)) {
ReserveEmuVariableNvStore ();
}
PeiFvInitialization ();
MemTypeInfoInitialization ();
MemMapInitialization ();

36
OvmfPkg/PlatformPei/Platform.h
View File

@@ -13,33 +13,33 @@
VOID
AddIoMemoryBaseSizeHob (
EFI_PHYSICAL_ADDRESS MemoryBase,
UINT64 MemorySize
EFI_PHYSICAL_ADDRESS MemoryBase,
UINT64 MemorySize
);
VOID
AddIoMemoryRangeHob (
EFI_PHYSICAL_ADDRESS MemoryBase,
EFI_PHYSICAL_ADDRESS MemoryLimit
EFI_PHYSICAL_ADDRESS MemoryBase,
EFI_PHYSICAL_ADDRESS MemoryLimit
);
VOID
AddMemoryBaseSizeHob (
EFI_PHYSICAL_ADDRESS MemoryBase,
UINT64 MemorySize
EFI_PHYSICAL_ADDRESS MemoryBase,
UINT64 MemorySize
);
VOID
AddMemoryRangeHob (
EFI_PHYSICAL_ADDRESS MemoryBase,
EFI_PHYSICAL_ADDRESS MemoryLimit
EFI_PHYSICAL_ADDRESS MemoryBase,
EFI_PHYSICAL_ADDRESS MemoryLimit
);
VOID
AddReservedMemoryBaseSizeHob (
EFI_PHYSICAL_ADDRESS MemoryBase,
UINT64 MemorySize,
BOOLEAN Cacheable
EFI_PHYSICAL_ADDRESS MemoryBase,
UINT64 MemorySize,
BOOLEAN Cacheable
);
VOID
@@ -102,18 +102,18 @@ AmdSevInitialize (
VOID
);
extern EFI_BOOT_MODE mBootMode;
extern EFI_BOOT_MODE mBootMode;
extern BOOLEAN mS3Supported;
extern BOOLEAN mS3Supported;
extern UINT8 mPhysMemAddressWidth;
extern UINT8 mPhysMemAddressWidth;
extern UINT32 mMaxCpuCount;
extern UINT32 mMaxCpuCount;
extern UINT16 mHostBridgeDevId;
extern UINT16 mHostBridgeDevId;
extern BOOLEAN mQ35SmramAtDefaultSmbase;
extern BOOLEAN mQ35SmramAtDefaultSmbase;
extern UINT32 mQemuUc32Base;
extern UINT32 mQemuUc32Base;
#endif // _PLATFORM_PEI_H_INCLUDED_