ArmPkg/ArmLib: remove unused ArmCleanDataCacheToPoU()
The function ArmCleanDataCacheToPoU() has no users, and its purpose is unclear, since it uses cache maintenance by set/way to perform the clean to PoU, which is a dubious practice to begin with. So remove the declaration and all definitions. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18752 6f19259b-4bc3-4df7-8a09-765794883524
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abiesheuvel
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@@ -40,7 +40,6 @@ GCC_ASM_EXPORT (ArmEnableAlignmentCheck)
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GCC_ASM_EXPORT (ArmEnableBranchPrediction)
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GCC_ASM_EXPORT (ArmDisableBranchPrediction)
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GCC_ASM_EXPORT (AArch64AllDataCachesOperation)
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GCC_ASM_EXPORT (AArch64PerformPoUDataCacheOperation)
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GCC_ASM_EXPORT (ArmDataMemoryBarrier)
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GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)
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GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
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@@ -324,19 +323,6 @@ ASM_PFX(AArch64AllDataCachesOperation):
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// right to ease the access to CSSELR and the Set/Way operation.
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cbz x3, L_Finished // No need to clean if LoC is 0
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mov x10, #0 // Start clean at cache level 0
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b Loop1
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ASM_PFX(AArch64PerformPoUDataCacheOperation):
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// We can use regs 0-7 and 9-15 without having to save/restore.
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// Save our link register on the stack. - The stack must always be quad-word aligned
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str x30, [sp, #-16]!
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mov x1, x0 // Save Function call in x1
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mrs x6, clidr_el1 // Read EL1 CLIDR
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and x3, x6, #0x38000000 // Mask out all but Point of Unification (PoU)
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lsr x3, x3, #26 // Left align cache level value - the level is shifted by 1 to the
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// right to ease the access to CSSELR and the Set/Way operation.
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cbz x3, L_Finished // No need to clean if LoC is 0
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mov x10, #0 // Start clean at cache level 0
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Loop1:
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add x2, x10, x10, lsr #1 // Work out 3x cachelevel for cache info
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