ArmPkg/ArmLib: remove unused ArmCleanDataCacheToPoU()
The function ArmCleanDataCacheToPoU() has no users, and its purpose is unclear, since it uses cache maintenance by set/way to perform the clean to PoU, which is a dubious practice to begin with. So remove the declaration and all definitions. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18752 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Ard Biesheuvel
abiesheuvel
parent
cf93a37859
commit
acdb6dc8b7
@ -241,12 +241,6 @@ ArmCleanDataCache (
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VOID
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VOID
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);
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);
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VOID
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EFIAPI
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ArmCleanDataCacheToPoU (
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VOID
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);
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VOID
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VOID
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EFIAPI
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EFIAPI
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ArmInvalidateInstructionCache (
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ArmInvalidateInstructionCache (
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@ -206,26 +206,6 @@ AArch64DataCacheOperation (
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}
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}
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}
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}
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VOID
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AArch64PoUDataCacheOperation (
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IN AARCH64_CACHE_OPERATION DataCacheOperation
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)
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{
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UINTN SavedInterruptState;
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SavedInterruptState = ArmGetInterruptState ();
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ArmDisableInterrupts ();
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AArch64PerformPoUDataCacheOperation (DataCacheOperation);
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ArmDrainWriteBuffer ();
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if (SavedInterruptState) {
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ArmEnableInterrupts ();
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}
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}
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VOID
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VOID
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EFIAPI
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EFIAPI
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ArmInvalidateDataCache (
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ArmInvalidateDataCache (
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@ -255,13 +235,3 @@ ArmCleanDataCache (
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ArmDrainWriteBuffer ();
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ArmDrainWriteBuffer ();
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AArch64DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
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AArch64DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
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}
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}
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VOID
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EFIAPI
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ArmCleanDataCacheToPoU (
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VOID
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)
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{
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ArmDrainWriteBuffer ();
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AArch64PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);
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}
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@ -18,12 +18,6 @@
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typedef VOID (*AARCH64_CACHE_OPERATION)(UINTN);
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typedef VOID (*AARCH64_CACHE_OPERATION)(UINTN);
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VOID
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AArch64PerformPoUDataCacheOperation (
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IN AARCH64_CACHE_OPERATION DataCacheOperation
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);
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VOID
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VOID
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AArch64AllDataCachesOperation (
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AArch64AllDataCachesOperation (
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IN AARCH64_CACHE_OPERATION DataCacheOperation
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IN AARCH64_CACHE_OPERATION DataCacheOperation
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@ -40,7 +40,6 @@ GCC_ASM_EXPORT (ArmEnableAlignmentCheck)
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GCC_ASM_EXPORT (ArmEnableBranchPrediction)
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GCC_ASM_EXPORT (ArmEnableBranchPrediction)
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GCC_ASM_EXPORT (ArmDisableBranchPrediction)
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GCC_ASM_EXPORT (ArmDisableBranchPrediction)
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GCC_ASM_EXPORT (AArch64AllDataCachesOperation)
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GCC_ASM_EXPORT (AArch64AllDataCachesOperation)
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GCC_ASM_EXPORT (AArch64PerformPoUDataCacheOperation)
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GCC_ASM_EXPORT (ArmDataMemoryBarrier)
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GCC_ASM_EXPORT (ArmDataMemoryBarrier)
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GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)
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GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)
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GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
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GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
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@ -324,19 +323,6 @@ ASM_PFX(AArch64AllDataCachesOperation):
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// right to ease the access to CSSELR and the Set/Way operation.
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// right to ease the access to CSSELR and the Set/Way operation.
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cbz x3, L_Finished // No need to clean if LoC is 0
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cbz x3, L_Finished // No need to clean if LoC is 0
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mov x10, #0 // Start clean at cache level 0
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mov x10, #0 // Start clean at cache level 0
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b Loop1
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ASM_PFX(AArch64PerformPoUDataCacheOperation):
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// We can use regs 0-7 and 9-15 without having to save/restore.
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// Save our link register on the stack. - The stack must always be quad-word aligned
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str x30, [sp, #-16]!
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mov x1, x0 // Save Function call in x1
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mrs x6, clidr_el1 // Read EL1 CLIDR
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and x3, x6, #0x38000000 // Mask out all but Point of Unification (PoU)
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lsr x3, x3, #26 // Left align cache level value - the level is shifted by 1 to the
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// right to ease the access to CSSELR and the Set/Way operation.
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cbz x3, L_Finished // No need to clean if LoC is 0
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mov x10, #0 // Start clean at cache level 0
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Loop1:
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Loop1:
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add x2, x10, x10, lsr #1 // Work out 3x cachelevel for cache info
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add x2, x10, x10, lsr #1 // Work out 3x cachelevel for cache info
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@ -208,26 +208,6 @@ ArmV7DataCacheOperation (
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}
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}
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}
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}
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VOID
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ArmV7PoUDataCacheOperation (
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IN ARM_V7_CACHE_OPERATION DataCacheOperation
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)
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{
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UINTN SavedInterruptState;
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SavedInterruptState = ArmGetInterruptState ();
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ArmDisableInterrupts ();
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ArmV7PerformPoUDataCacheOperation (DataCacheOperation);
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ArmDrainWriteBuffer ();
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if (SavedInterruptState) {
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ArmEnableInterrupts ();
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}
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}
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VOID
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VOID
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EFIAPI
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EFIAPI
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ArmInvalidateDataCache (
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ArmInvalidateDataCache (
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@ -257,13 +237,3 @@ ArmCleanDataCache (
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ArmDrainWriteBuffer ();
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ArmDrainWriteBuffer ();
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ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
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ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
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}
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}
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VOID
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EFIAPI
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ArmCleanDataCacheToPoU (
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VOID
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)
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{
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ArmDrainWriteBuffer ();
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ArmV7PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);
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}
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@ -17,12 +17,6 @@
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typedef VOID (*ARM_V7_CACHE_OPERATION)(UINT32);
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typedef VOID (*ARM_V7_CACHE_OPERATION)(UINT32);
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VOID
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ArmV7PerformPoUDataCacheOperation (
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IN ARM_V7_CACHE_OPERATION DataCacheOperation
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);
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VOID
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VOID
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ArmV7AllDataCachesOperation (
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ArmV7AllDataCachesOperation (
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IN ARM_V7_CACHE_OPERATION DataCacheOperation
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IN ARM_V7_CACHE_OPERATION DataCacheOperation
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@ -38,7 +38,6 @@ GCC_ASM_EXPORT (ArmDisableBranchPrediction)
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GCC_ASM_EXPORT (ArmSetLowVectors)
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GCC_ASM_EXPORT (ArmSetLowVectors)
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GCC_ASM_EXPORT (ArmSetHighVectors)
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GCC_ASM_EXPORT (ArmSetHighVectors)
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GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)
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GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)
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GCC_ASM_EXPORT (ArmV7PerformPoUDataCacheOperation)
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GCC_ASM_EXPORT (ArmDataMemoryBarrier)
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GCC_ASM_EXPORT (ArmDataMemoryBarrier)
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GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)
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GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)
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GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
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GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
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@ -268,55 +267,6 @@ L_Finished:
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ldmfd SP!, {r4-r12, lr}
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ldmfd SP!, {r4-r12, lr}
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bx LR
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bx LR
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ASM_PFX(ArmV7PerformPoUDataCacheOperation):
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stmfd SP!,{r4-r12, LR}
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mov R1, R0 @ Save Function call in R1
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mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR
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ands R3, R6, #0x38000000 @ Mask out all but Level of Unification (LoU)
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mov R3, R3, LSR #26 @ Cache level value (naturally aligned)
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beq Finished2
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mov R10, #0
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Loop4:
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add R2, R10, R10, LSR #1 @ Work out 3xcachelevel
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mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level
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and R12, R12, #7 @ get those 3 bits alone
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cmp R12, #2
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blt Skip2 @ no cache or only instruction cache at this level
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mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
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isb @ isb to sync the change to the CacheSizeID reg
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mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)
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and R2, R12, #0x7 @ extract the line length field
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add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes)
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ldr R4, =0x3FF
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ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned)
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clz R5, R4 @ R5 is the bit position of the way size increment
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ldr R7, =0x00007FFF
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ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned)
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Loop5:
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mov R9, R4 @ R9 working copy of the max way size (right aligned)
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Loop6:
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orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11
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orr R0, R0, R7, LSL R2 @ factor in the index number
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blx R1
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subs R9, R9, #1 @ decrement the way number
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bge Loop6
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subs R7, R7, #1 @ decrement the index
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bge Loop5
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Skip2:
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add R10, R10, #2 @ increment the cache number
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cmp R3, R10
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bgt Loop4
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Finished2:
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dsb
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ldmfd SP!, {r4-r12, lr}
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bx LR
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ASM_PFX(ArmDataMemoryBarrier):
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ASM_PFX(ArmDataMemoryBarrier):
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dmb
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dmb
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bx LR
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bx LR
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@ -35,7 +35,6 @@
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EXPORT ArmSetLowVectors
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EXPORT ArmSetLowVectors
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EXPORT ArmSetHighVectors
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EXPORT ArmSetHighVectors
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EXPORT ArmV7AllDataCachesOperation
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EXPORT ArmV7AllDataCachesOperation
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EXPORT ArmV7PerformPoUDataCacheOperation
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EXPORT ArmDataMemoryBarrier
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EXPORT ArmDataMemoryBarrier
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EXPORT ArmDataSynchronizationBarrier
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EXPORT ArmDataSynchronizationBarrier
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EXPORT ArmInstructionSynchronizationBarrier
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EXPORT ArmInstructionSynchronizationBarrier
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@ -262,55 +261,6 @@ Finished
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ldmfd SP!, {r4-r12, lr}
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ldmfd SP!, {r4-r12, lr}
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bx LR
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bx LR
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ArmV7PerformPoUDataCacheOperation
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stmfd SP!,{r4-r12, LR}
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mov R1, R0 ; Save Function call in R1
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mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR
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ands R3, R6, #&38000000 ; Mask out all but Level of Unification (LoU)
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mov R3, R3, LSR #26 ; Cache level value (naturally aligned)
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beq Finished2
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mov R10, #0
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Loop4
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add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
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mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
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and R12, R12, #7 ; get those 3 bits alone
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cmp R12, #2
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blt Skip2 ; no cache or only instruction cache at this level
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mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
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isb ; isb to sync the change to the CacheSizeID reg
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mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
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and R2, R12, #&7 ; extract the line length field
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add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
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ldr R4, =0x3FF
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ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
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clz R5, R4 ; R5 is the bit position of the way size increment
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ldr R7, =0x00007FFF
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ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
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Loop5
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mov R9, R4 ; R9 working copy of the max way size (right aligned)
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Loop6
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orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11
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orr R0, R0, R7, LSL R2 ; factor in the index number
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blx R1
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subs R9, R9, #1 ; decrement the way number
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bge Loop6
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subs R7, R7, #1 ; decrement the index
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bge Loop5
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Skip2
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add R10, R10, #2 ; increment the cache number
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cmp R3, R10
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bgt Loop4
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Finished2
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dsb
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ldmfd SP!, {r4-r12, lr}
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bx LR
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ArmDataMemoryBarrier
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ArmDataMemoryBarrier
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dmb
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dmb
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bx LR
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bx LR
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