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Do not access transfer ring when endpoint is isochronous type and control type. And when one Endpoint is a unknown type, do not ASSERT(0) and process next endpoint.

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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Elvin Li <elvin.li@intel.com>
Signed-off-by: Feng Tian <feng.tian@intel.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15876 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Elvin Li 2014-08-22 01:13:48 +00:00 committed by li-elvin
parent 5eadb80f09
commit acedecdd5e
1 changed files with 26 additions and 6 deletions
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32
MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
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@ -2606,7 +2606,12 @@ XhcInitializeEndpointContext (
InputContext->EP[Dci-1].CErr = 0; InputContext->EP[Dci-1].CErr = 0;
InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT; InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
} }
break; //
// Do not support isochronous transfer now.
//
DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
continue;
case USB_ENDPOINT_INTERRUPT: case USB_ENDPOINT_INTERRUPT:
if (Direction == EfiUsbDataIn) { if (Direction == EfiUsbDataIn) {
InputContext->EP[Dci-1].CErr = 3; InputContext->EP[Dci-1].CErr = 3;
@ -2648,9 +2653,14 @@ XhcInitializeEndpointContext (
break; break;
case USB_ENDPOINT_CONTROL: case USB_ENDPOINT_CONTROL:
//
// Do not support control transfer now.
//
DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unsupport Control EP found, Transfer ring is not allocated.\n"));
default: default:
ASSERT (0); DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unknown EP found, Transfer ring is not allocated.\n"));
break; EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
continue;
} }
PhyAddr = UsbHcGetPciAddrForHostAddr ( PhyAddr = UsbHcGetPciAddrForHostAddr (
@ -2759,7 +2769,12 @@ XhcInitializeEndpointContext64 (
InputContext->EP[Dci-1].CErr = 0; InputContext->EP[Dci-1].CErr = 0;
InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT; InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
} }
break; //
// Do not support isochronous transfer now.
//
DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
continue;
case USB_ENDPOINT_INTERRUPT: case USB_ENDPOINT_INTERRUPT:
if (Direction == EfiUsbDataIn) { if (Direction == EfiUsbDataIn) {
InputContext->EP[Dci-1].CErr = 3; InputContext->EP[Dci-1].CErr = 3;
@ -2801,9 +2816,14 @@ XhcInitializeEndpointContext64 (
break; break;
case USB_ENDPOINT_CONTROL: case USB_ENDPOINT_CONTROL:
//
// Do not support control transfer now.
//
DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unsupport Control EP found, Transfer ring is not allocated.\n"));
default: default:
ASSERT (0); DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unknown EP found, Transfer ring is not allocated.\n"));
break; EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
continue;
} }
PhyAddr = UsbHcGetPciAddrForHostAddr ( PhyAddr = UsbHcGetPciAddrForHostAddr (