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BaseTools: BaseTools changes for RISC-V platform.

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C code changes for building EDK2 RISC-V platform.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Co-authored-by: Daniel Helmut Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
This commit is contained in:
Abner Chang
2020-04-23 21:52:32 +08:00
committed by mergify[bot]
parent cdc3fa5418
commit ad1db975c0
8 changed files with 580 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
BaseTools/Source/C/Common/BasePeCoff.c
View File

@ -4,6 +4,7 @@
Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@ -59,6 +60,14 @@ PeCoffLoaderRelocateArmImage (
IN UINT64 Adjust
);
RETURN_STATUS
PeCoffLoaderRelocateRiscVImage (
IN UINT16 *Reloc,
IN OUT CHAR8 *Fixup,
IN OUT CHAR8 **FixupData,
IN UINT64 Adjust
);
STATIC
RETURN_STATUS
PeCoffLoaderGetPeHeader (
@ -174,7 +183,8 @@ Returns:
ImageContext->Machine != EFI_IMAGE_MACHINE_X64 && \
ImageContext->Machine != EFI_IMAGE_MACHINE_ARMT && \
ImageContext->Machine != EFI_IMAGE_MACHINE_EBC && \
ImageContext->Machine != EFI_IMAGE_MACHINE_AARCH64) {
ImageContext->Machine != EFI_IMAGE_MACHINE_AARCH64 && \
ImageContext->Machine != EFI_IMAGE_MACHINE_RISCV64) {
if (ImageContext->Machine == IMAGE_FILE_MACHINE_ARM) {
//
// There are two types of ARM images. Pure ARM and ARM/Thumb.
@ -802,6 +812,9 @@ Returns:
case EFI_IMAGE_MACHINE_ARMT:
Status = PeCoffLoaderRelocateArmImage (&Reloc, Fixup, &FixupData, Adjust);
break;
case EFI_IMAGE_MACHINE_RISCV64:
Status = PeCoffLoaderRelocateRiscVImage (Reloc, Fixup, &FixupData, Adjust);
break;
default:
Status = RETURN_UNSUPPORTED;
break;

9
BaseTools/Source/C/Common/PeCoffLib.h
View File

@ -2,6 +2,7 @@
Function prototypes and defines on Memory Only PE COFF loader
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
Portion Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@ -25,6 +26,14 @@
#define IMAGE_ERROR_FAILED_RELOCATION 9
#define IMAGE_ERROR_FAILED_ICACHE_FLUSH 10
//
// Macro definitions for RISC-V architecture.
//
#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1))
#define RISCV_IMM_BITS 12
#define RISCV_IMM_REACH (1LL<<RISCV_IMM_BITS)
#define RISCV_CONST_HIGH_PART(VALUE) \
(((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
//
// PE/COFF Loader Read Function passed in by caller

86
BaseTools/Source/C/Common/PeCoffLoaderEx.c
View File

@ -3,6 +3,7 @@ IA32 and X64 Specific relocation fixups
Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
--*/
@ -61,6 +62,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define IMM64_SIGN_INST_WORD_POS_X 27
#define IMM64_SIGN_VAL_POS_X 63
UINT32 *RiscVHi20Fixup = NULL;
RETURN_STATUS
PeCoffLoaderRelocateIa32Image (
IN UINT16 *Reloc,
@ -93,6 +96,89 @@ Returns:
return RETURN_UNSUPPORTED;
}
/*++
Routine Description:
Performs an RISC-V specific relocation fixup
Arguments:
Reloc - Pointer to the relocation record
Fixup - Pointer to the address to fix up
FixupData - Pointer to a buffer to log the fixups
Adjust - The offset to adjust the fixup
Returns:
Status code
--*/
RETURN_STATUS
PeCoffLoaderRelocateRiscVImage (
IN UINT16 *Reloc,
IN OUT CHAR8 *Fixup,
IN OUT CHAR8 **FixupData,
IN UINT64 Adjust
)
{
UINT32 Value;
UINT32 Value2;
UINT32 OrgValue;
OrgValue = *(UINT32 *) Fixup;
OrgValue = OrgValue;
switch ((*Reloc) >> 12) {
case EFI_IMAGE_REL_BASED_RISCV_HI20:
RiscVHi20Fixup = (UINT32 *) Fixup;
break;
case EFI_IMAGE_REL_BASED_RISCV_LOW12I:
if (RiscVHi20Fixup != NULL) {
Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 20, 12));
if (Value2 & (RISCV_IMM_REACH/2)) {
Value2 |= ~(RISCV_IMM_REACH-1);
}
Value += Value2;
Value += (UINT32)Adjust;
Value2 = RISCV_CONST_HIGH_PART (Value);
*(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) | \
(RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
*(UINT32 *)Fixup = (RV_X (Value, 0, 12) << 20) | \
(RV_X (*(UINT32 *)Fixup, 0, 20));
}
RiscVHi20Fixup = NULL;
break;
case EFI_IMAGE_REL_BASED_RISCV_LOW12S:
if (RiscVHi20Fixup != NULL) {
Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 7, 5) | (RV_X(*(UINT32 *)Fixup, 25, 7) << 5));
if (Value2 & (RISCV_IMM_REACH/2)) {
Value2 |= ~(RISCV_IMM_REACH-1);
}
Value += Value2;
Value += (UINT32)Adjust;
Value2 = RISCV_CONST_HIGH_PART (Value);
*(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) | \
(RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
Value2 = *(UINT32 *)Fixup & 0x01fff07f;
Value &= RISCV_IMM_REACH - 1;
*(UINT32 *)Fixup = Value2 | (UINT32)(((RV_X(Value, 0, 5) << 7) | (RV_X(Value, 5, 7) << 25)));
}
RiscVHi20Fixup = NULL;
break;
default:
return EFI_UNSUPPORTED;
}
return RETURN_SUCCESS;
}
/**
Pass in a pointer to an ARM MOVT or MOVW immediate instruction and