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UefiCpuPkg: ApicLib

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GetProcessorLocationByApicId ()
- Use max possible thread count to decode InitialApicId on AMD processor.
- Clean-up on C Coding standards.

Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
This commit is contained in:
Leo Duran 2017-08-02 03:35:13 +08:00 committed by Liming Gao
parent 302860bfc4
commit ae66c6f12c
2 changed files with 32 additions and 96 deletions
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46
UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
View File

@ -1000,7 +1000,6 @@ GetProcessorLocationByApicId (
CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx; CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx; CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx;
CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx; CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
UINT32 MaxStandardCpuIdIndex; UINT32 MaxStandardCpuIdIndex;
UINT32 MaxExtendedCpuIdIndex; UINT32 MaxExtendedCpuIdIndex;
@ -1008,11 +1007,6 @@ GetProcessorLocationByApicId (
UINTN LevelType; UINTN LevelType;
UINT32 MaxLogicProcessorsPerPackage; UINT32 MaxLogicProcessorsPerPackage;
UINT32 MaxCoresPerPackage; UINT32 MaxCoresPerPackage;
UINT32 MaxThreadPerPackageMask;
UINT32 ActualThreadPerPackageMask;
UINT32 MaxCoresPerNode;
UINT32 CorePerNodeMask;
UINT32 ApicIdShift;
UINTN ThreadBits; UINTN ThreadBits;
UINTN CoreBits; UINTN CoreBits;
@ -1118,43 +1112,17 @@ GetProcessorLocationByApicId (
if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) { if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL); AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) { if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32, //
&AmdProcessorTopologyEcx.Uint32, NULL); // Account for max possible thread count to decode ApicId
//
AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);
MaxLogicProcessorsPerPackage = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
// //
// Get cores per processor package // Get cores per processor package
// //
AsmCpuid (CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32, NULL, NULL);
MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1); MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
//
// Account for actual thread count (e.g., SMT disabled)
//
AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);
MaxThreadPerPackageMask = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
ActualThreadPerPackageMask = 1;
while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage) {
ActualThreadPerPackageMask <<= 1;
}
//
// Adjust APIC Id to report concatenation of Package|Core|Thread.
//
if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {
MaxCoresPerNode = MaxCoresPerPackage / (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);
CorePerNodeMask = 1;
while (CorePerNodeMask < MaxCoresPerNode) {
CorePerNodeMask <<= 1;
}
CorePerNodeMask -= 1;
ApicIdShift = 0;
do {
ApicIdShift += 1;
ActualThreadPerPackageMask <<= 1;
} while (ActualThreadPerPackageMask < MaxThreadPerPackageMask);
InitialApicId = ((InitialApicId & ~CorePerNodeMask) >> ApicIdShift) | (InitialApicId & CorePerNodeMask);
}
} }
} }
} }

46
UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
View File

@ -1095,7 +1095,6 @@ GetProcessorLocationByApicId (
CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx; CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx; CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx;
CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx; CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
UINT32 MaxStandardCpuIdIndex; UINT32 MaxStandardCpuIdIndex;
UINT32 MaxExtendedCpuIdIndex; UINT32 MaxExtendedCpuIdIndex;
@ -1103,11 +1102,6 @@ GetProcessorLocationByApicId (
UINTN LevelType; UINTN LevelType;
UINT32 MaxLogicProcessorsPerPackage; UINT32 MaxLogicProcessorsPerPackage;
UINT32 MaxCoresPerPackage; UINT32 MaxCoresPerPackage;
UINT32 MaxThreadPerPackageMask;
UINT32 ActualThreadPerPackageMask;
UINT32 MaxCoresPerNode;
UINT32 CorePerNodeMask;
UINT32 ApicIdShift;
UINTN ThreadBits; UINTN ThreadBits;
UINTN CoreBits; UINTN CoreBits;
@ -1213,43 +1207,17 @@ GetProcessorLocationByApicId (
if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) { if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL); AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) { if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32, //
&AmdProcessorTopologyEcx.Uint32, NULL); // Account for max possible thread count to decode ApicId
//
AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);
MaxLogicProcessorsPerPackage = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
// //
// Get cores per processor package // Get cores per processor package
// //
AsmCpuid (CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32, NULL, NULL);
MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1); MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
//
// Account for actual thread count (e.g., SMT disabled)
//
AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);
MaxThreadPerPackageMask = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
ActualThreadPerPackageMask = 1;
while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage) {
ActualThreadPerPackageMask <<= 1;
}
//
// Adjust APIC Id to report concatenation of Package|Core|Thread.
//
if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {
MaxCoresPerNode = MaxCoresPerPackage / (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);
CorePerNodeMask = 1;
while (CorePerNodeMask < MaxCoresPerNode) {
CorePerNodeMask <<= 1;
}
CorePerNodeMask -= 1;
ApicIdShift = 0;
do {
ApicIdShift += 1;
ActualThreadPerPackageMask <<= 1;
} while (ActualThreadPerPackageMask < MaxThreadPerPackageMask);
InitialApicId = ((InitialApicId & ~CorePerNodeMask) >> ApicIdShift) | (InitialApicId & CorePerNodeMask);
}
} }
} }
} }