IntelFsp2Pkg: TempRamInit API should preserve EBX/RBX register.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4395

FSP specification defines the TempRamInit API preserved register list
which including EBX/RBX, however current implementation unexpectedly
overriding EBX/RBX register that should be fixed.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
This commit is contained in:
Chasel Chiu
2023-03-31 00:09:27 -07:00
committed by mergify[bot]
parent fb89f62d27
commit af98f1fb03
2 changed files with 27 additions and 1 deletions

View File

@@ -157,6 +157,9 @@ NextAddress:
; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test
; whether the processor supports SSE instruction.
;
; Save EBX to MM2
;
movd mm2, ebx
mov eax, 1
cpuid
bt edx, 25
@@ -169,6 +172,10 @@ NextAddress:
bt ecx, 19
jnc SseError
%endif
;
; Restore EBX from MM2
;
movd ebx, mm2
;
; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)