IntelFsp2Pkg: TempRamInit API should preserve EBX/RBX register.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4395 FSP specification defines the TempRamInit API preserved register list which including EBX/RBX, however current implementation unexpectedly overriding EBX/RBX register that should be fixed. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
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@@ -157,6 +157,9 @@ NextAddress:
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; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test
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; whether the processor supports SSE instruction.
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;
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; Save EBX to MM2
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;
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movd mm2, ebx
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mov eax, 1
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cpuid
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bt edx, 25
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@@ -169,6 +172,10 @@ NextAddress:
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bt ecx, 19
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jnc SseError
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%endif
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;
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; Restore EBX from MM2
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;
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movd ebx, mm2
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;
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; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
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