MdeModulePkg/DxeIplPeim: Support GHCB pages when creating page tables
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 GHCB pages must be mapped as shared pages, so modify the process of creating identity mapped pagetable entries so that GHCB entries are created without the encryption bit set. The GHCB range consists of two pages per CPU, the first being the GHCB and the second being a per-CPU variable page. Only the GHCB page is mapped as shared. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Cc: Liming Gao <liming.gao@intel.com> Acked-by: Hao A Wu <hao.a.wu@intel.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
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mergify[bot]
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1c0eb91503
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@@ -35,6 +35,8 @@ HandOffToDxeCore (
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UINT32 Index;
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EFI_VECTOR_HANDOFF_INFO *VectorInfo;
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EFI_PEI_VECTOR_HANDOFF_INFO_PPI *VectorHandoffInfoPpi;
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VOID *GhcbBase;
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UINTN GhcbSize;
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//
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// Clear page 0 and mark it as allocated if NULL pointer detection is enabled.
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@@ -81,12 +83,19 @@ HandOffToDxeCore (
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TopOfStack = (VOID *) ((UINTN) BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT);
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TopOfStack = ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT);
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//
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// Get the address and size of the GHCB pages
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//
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GhcbBase = (VOID *) PcdGet64 (PcdGhcbBase);
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GhcbSize = PcdGet64 (PcdGhcbSize);
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PageTables = 0;
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if (FeaturePcdGet (PcdDxeIplBuildPageTables)) {
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//
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// Create page table and save PageMapLevel4 to CR3
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//
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PageTables = CreateIdentityMappingPageTables ((EFI_PHYSICAL_ADDRESS) (UINTN) BaseOfStack, STACK_SIZE);
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PageTables = CreateIdentityMappingPageTables ((EFI_PHYSICAL_ADDRESS) (UINTN) BaseOfStack, STACK_SIZE,
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(EFI_PHYSICAL_ADDRESS) (UINTN) GhcbBase, GhcbSize);
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} else {
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//
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// Set NX for stack feature also require PcdDxeIplBuildPageTables be TRUE
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