ArmPlatformPkg: Tidy Lcd code: Coding standard
There is no functional modification in this change As preparation for further work, the formatting is corrected to meet the EDKII coding standard. Of specific note, some invalid include guards were fixed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
This commit is contained in:
Girish Pathak
committed by
Leif Lindholm
Leif Lindholm
parent
e10c79145e
commit
b1b69d2606
@@ -1,6 +1,6 @@
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/** @file Lcd.c
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/** @file
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Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
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Copyright (c) 2011-2018, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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@@ -21,12 +21,9 @@
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#include "HdLcd.h"
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/**********************************************************************
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*
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* This file contains all the bits of the Lcd that are
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* platform independent.
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*
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**********************************************************************/
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/** This file contains all the bits of the Lcd that are
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platform independent.
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**/
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STATIC
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UINTN
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@@ -34,7 +31,7 @@ GetBytesPerPixel (
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IN LCD_BPP Bpp
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)
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{
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switch(Bpp) {
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switch (Bpp) {
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case LCD_BITS_PER_PIXEL_24:
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return 4;
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@@ -60,21 +57,27 @@ LcdInitialize (
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)
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{
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// Disable the controller
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MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE);
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MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE);
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// Disable all interrupts
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MmioWrite32(HDLCD_REG_INT_MASK, 0);
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MmioWrite32 (HDLCD_REG_INT_MASK, 0);
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// Define start of the VRAM. This never changes for any graphics mode
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MmioWrite32(HDLCD_REG_FB_BASE, (UINT32) VramBaseAddress);
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MmioWrite32 (HDLCD_REG_FB_BASE, (UINT32)VramBaseAddress);
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// Setup various registers that never change
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MmioWrite32(HDLCD_REG_BUS_OPTIONS, (4 << 8) | HDLCD_BURST_8);
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MmioWrite32(HDLCD_REG_POLARITIES, HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH | HDLCD_DATEN_HIGH | HDLCD_HSYNC_LOW | HDLCD_VSYNC_HIGH);
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MmioWrite32(HDLCD_REG_PIXEL_FORMAT, HDLCD_LITTLE_ENDIAN | HDLCD_4BYTES_PER_PIXEL);
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MmioWrite32(HDLCD_REG_RED_SELECT, (0 << 16 | 8 << 8 | 0));
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MmioWrite32(HDLCD_REG_GREEN_SELECT, (0 << 16 | 8 << 8 | 8));
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MmioWrite32(HDLCD_REG_BLUE_SELECT, (0 << 16 | 8 << 8 | 16));
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MmioWrite32 (HDLCD_REG_BUS_OPTIONS, (4 << 8) | HDLCD_BURST_8);
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MmioWrite32 (HDLCD_REG_POLARITIES, HDLCD_DEFAULT_POLARITIES);
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MmioWrite32 (
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HDLCD_REG_PIXEL_FORMAT,
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HDLCD_LITTLE_ENDIAN | HDLCD_4BYTES_PER_PIXEL
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);
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MmioWrite32 (HDLCD_REG_RED_SELECT, (0 << 16 | 8 << 8 | 0));
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MmioWrite32 (HDLCD_REG_GREEN_SELECT, (0 << 16 | 8 << 8 | 8));
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MmioWrite32 (HDLCD_REG_BLUE_SELECT, (0 << 16 | 8 << 8 | 16));
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return EFI_SUCCESS;
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}
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@@ -96,46 +99,53 @@ LcdSetMode (
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UINT32 BytesPerPixel;
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LCD_BPP LcdBpp;
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// Set the video mode timings and other relevant information
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Status = LcdPlatformGetTimings (ModeNumber,
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&HRes,&HSync,&HBackPorch,&HFrontPorch,
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&VRes,&VSync,&VBackPorch,&VFrontPorch);
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Status = LcdPlatformGetTimings (
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ModeNumber,
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&HRes,
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&HSync,
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&HBackPorch,
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&HFrontPorch,
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&VRes,
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&VSync,
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&VBackPorch,
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&VFrontPorch
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);
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ASSERT_EFI_ERROR (Status);
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if (EFI_ERROR( Status )) {
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if (EFI_ERROR (Status)) {
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return EFI_DEVICE_ERROR;
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}
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Status = LcdPlatformGetBpp (ModeNumber,&LcdBpp);
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Status = LcdPlatformGetBpp (ModeNumber, &LcdBpp);
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ASSERT_EFI_ERROR (Status);
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if (EFI_ERROR( Status )) {
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if (EFI_ERROR (Status)) {
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return EFI_DEVICE_ERROR;
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}
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BytesPerPixel = GetBytesPerPixel(LcdBpp);
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BytesPerPixel = GetBytesPerPixel (LcdBpp);
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// Disable the controller
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MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE);
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MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE);
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// Update the frame buffer information with the new settings
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MmioWrite32(HDLCD_REG_FB_LINE_LENGTH, HRes * BytesPerPixel);
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MmioWrite32(HDLCD_REG_FB_LINE_PITCH, HRes * BytesPerPixel);
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MmioWrite32(HDLCD_REG_FB_LINE_COUNT, VRes - 1);
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MmioWrite32 (HDLCD_REG_FB_LINE_LENGTH, HRes * BytesPerPixel);
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MmioWrite32 (HDLCD_REG_FB_LINE_PITCH, HRes * BytesPerPixel);
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MmioWrite32 (HDLCD_REG_FB_LINE_COUNT, VRes - 1);
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// Set the vertical timing information
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MmioWrite32(HDLCD_REG_V_SYNC, VSync);
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MmioWrite32(HDLCD_REG_V_BACK_PORCH, VBackPorch);
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MmioWrite32(HDLCD_REG_V_DATA, VRes - 1);
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MmioWrite32(HDLCD_REG_V_FRONT_PORCH, VFrontPorch);
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MmioWrite32 (HDLCD_REG_V_SYNC, VSync);
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MmioWrite32 (HDLCD_REG_V_BACK_PORCH, VBackPorch);
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MmioWrite32 (HDLCD_REG_V_DATA, VRes - 1);
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MmioWrite32 (HDLCD_REG_V_FRONT_PORCH, VFrontPorch);
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// Set the horizontal timing information
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MmioWrite32(HDLCD_REG_H_SYNC, HSync);
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MmioWrite32(HDLCD_REG_H_BACK_PORCH, HBackPorch);
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MmioWrite32(HDLCD_REG_H_DATA, HRes - 1);
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MmioWrite32(HDLCD_REG_H_FRONT_PORCH, HFrontPorch);
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MmioWrite32 (HDLCD_REG_H_SYNC, HSync);
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MmioWrite32 (HDLCD_REG_H_BACK_PORCH, HBackPorch);
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MmioWrite32 (HDLCD_REG_H_DATA, HRes - 1);
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MmioWrite32 (HDLCD_REG_H_FRONT_PORCH, HFrontPorch);
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// Enable the controller
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MmioWrite32(HDLCD_REG_COMMAND, HDLCD_ENABLE);
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MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_ENABLE);
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return EFI_SUCCESS;
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}
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@@ -1,6 +1,6 @@
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/** @file HDLcd.h
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/** @file
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Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
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Copyright (c) 2011-2018, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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@@ -12,13 +12,10 @@
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**/
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#ifndef _HDLCD_H_
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#define _HDLCD_H_
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#ifndef HDLCD_H_
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#define HDLCD_H_
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//
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// HDLCD Controller Register Offsets
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//
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#define HDLCD_REG_VERSION ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000)
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#define HDLCD_REG_INT_RAWSTAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010)
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#define HDLCD_REG_INT_CLEAR ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014)
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@@ -44,10 +41,7 @@
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#define HDLCD_REG_GREEN_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248)
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#define HDLCD_REG_BLUE_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C)
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//
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// HDLCD Values of registers
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//
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// HDLCD Interrupt mask, clear and status register
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#define HDLCD_DMA_END BIT0 /* DMA has finished reading a frame */
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@@ -79,6 +73,11 @@
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#define HDLCD_DATA_LOW 0
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#define HDLCD_PXCLK_LOW 0
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// Default polarities
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#define HDLCD_DEFAULT_POLARITIES (HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH | \
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HDLCD_DATEN_HIGH | HDLCD_HSYNC_LOW | \
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HDLCD_VSYNC_HIGH)
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// Pixel Format
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#define HDLCD_LITTLE_ENDIAN (0 << 31)
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#define HDLCD_BIG_ENDIAN (1 << 31)
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@@ -86,4 +85,4 @@
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// Number of bytes per pixel
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#define HDLCD_4BYTES_PER_PIXEL ((4 - 1) << 3)
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#endif /* _HDLCD_H_ */
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#endif /* HDLCD_H_ */
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