ArmPkg/ArmCpuLib: Replaced complex functions ArmCpuSynchronizeWait & ArmCpuSynchronizeSignal by sev & wfe
Previsouly the synchronization of MpCore was using the SGI (Software Generated Interrupt) to synchronize MpCore during the early boot. This commit replaced this mechanism by the more appropriate SEV/WFE instructions (Send/Wait Event instructions). That also eases the port to a new cpu/platform. Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13249 6f19259b-4bc3-4df7-8a09-765794883524
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@@ -1,5 +1,5 @@
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//
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// Copyright (c) 2011, ARM Limited. All rights reserved.
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// Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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@@ -18,24 +18,7 @@
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.text
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.align 3
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GCC_ASM_EXPORT(ArmCpuSynchronizeWait)
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GCC_ASM_EXPORT(ArmGetScuBaseAddress)
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GCC_ASM_IMPORT(CArmCpuSynchronizeWait)
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// VOID
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// ArmCpuSynchronizeWait (
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// IN ARM_CPU_SYNCHRONIZE_EVENT Event
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// );
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ASM_PFX(ArmCpuSynchronizeWait):
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cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
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// The SCU enabled is the event to tell us the Init Boot Memory is initialized
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beq ASM_PFX(ArmWaitScuEnabled)
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// Case when the stack has been set up
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push {r1,lr}
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LoadConstantToReg (ASM_PFX(CArmCpuSynchronizeWait), r1)
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blx r1
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pop {r1,lr}
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bx lr
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// IN None
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// OUT r0 = SCU Base Address
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@@ -45,14 +28,3 @@ ASM_PFX(ArmGetScuBaseAddress):
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// offset 0x0000 from the Private Memory Region.
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mrc p15, 4, r0, c15, c0, 0
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bx lr
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ASM_PFX(ArmWaitScuEnabled):
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// Read Configuration Base Address Register. ArmCBar cannot be called to get
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// the Configuration BAR as a stack is not necessary setup. The SCU is at the
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// offset 0x0000 from the Private Memory Region.
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mrc p15, 4, r0, c15, c0, 0
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add r0, r0, #A9_SCU_CONTROL_OFFSET
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ldr r0, [r0]
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cmp r0, #1
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bne ASM_PFX(ArmWaitScuEnabled)
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bx lr
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