ArmPkg/ArmCpuLib: Replaced complex functions ArmCpuSynchronizeWait & ArmCpuSynchronizeSignal by sev & wfe

Previsouly the synchronization of MpCore was using the SGI (Software
Generated Interrupt) to synchronize MpCore during the early boot.
This commit replaced this mechanism by the more appropriate SEV/WFE
instructions (Send/Wait Event instructions).
That also eases the port to a new cpu/platform.

Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13249 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
2012-05-02 19:55:32 +00:00
parent f463bb00ad
commit b1d41be7c9
19 changed files with 61 additions and 274 deletions

View File

@@ -1,5 +1,5 @@
//
// Copyright (c) 2011, ARM Limited. All rights reserved.
// Copyright (c) 2011-2012, ARM Limited. All rights reserved.
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
@@ -17,28 +17,11 @@
INCLUDE AsmMacroIoLib.inc
EXPORT ArmCpuSynchronizeWait
EXPORT ArmGetScuBaseAddress
IMPORT CArmCpuSynchronizeWait
PRESERVE8
AREA ArmCortexA9Helper, CODE, READONLY
// VOID
// ArmCpuSynchronizeWait (
// IN ARM_CPU_SYNCHRONIZE_EVENT Event
// );
ArmCpuSynchronizeWait
cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
// The SCU enabled is the event to tell us the Init Boot Memory is initialized
beq ArmWaitScuEnabled
// Case when the stack has been set up
push {r1,lr}
LoadConstantToReg (CArmCpuSynchronizeWait, r1)
blx r1
pop {r1,lr}
bx lr
// IN None
// OUT r0 = SCU Base Address
ArmGetScuBaseAddress
@@ -48,15 +31,4 @@ ArmGetScuBaseAddress
mrc p15, 4, r0, c15, c0, 0
bx lr
ArmWaitScuEnabled
// Read Configuration Base Address Register. ArmCBar cannot be called to get
// the Configuration BAR as a stack is not necessary setup. The SCU is at the
// offset 0x0000 from the Private Memory Region.
mrc p15, 4, r0, c15, c0, 0
add r0, r0, #A9_SCU_CONTROL_OFFSET
ldr r0, [r0]
cmp r0, #1
bne ArmWaitScuEnabled
bx lr
END