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MdePkg: Move API and implementation from UefiCpuLib to CpuLib

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There are two libraries: MdePkg/CpuLib and UefiCpuPkg/UefiCpuLib. This
patch merges UefiCpuPkg/UefiCpuLib to MdePkg/CpuLib.

Change-Id: Ic26f4c2614ed6bd9840f817d50e47ac1de4bd013
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Yu Pu <yu.pu@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
This commit is contained in:
Yu Pu
2022-03-29 11:28:32 +08:00
committed by mergify[bot]
parent bf0c14a562
commit b294633c68
8 changed files with 74 additions and 57 deletions
Download Patch File Download Diff File Expand all files Collapse all files

49
UefiCpuPkg/Include/Library/UefiCpuLib.h
View File

@@ -13,53 +13,4 @@
#ifndef __UEFI_CPU_LIB_H__
#define __UEFI_CPU_LIB_H__
/**
Initializes floating point units for requirement of UEFI specification.
This function initializes floating-point control word to 0x027F (all exceptions
masked,double-precision, round-to-nearest) and multimedia-extensions control word
(if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
for masked underflow).
**/
VOID
EFIAPI
InitializeFloatingPointUnits (
VOID
);
/**
Determine if the standard CPU signature is "AuthenticAMD".
@retval TRUE The CPU signature matches.
@retval FALSE The CPU signature does not match.
**/
BOOLEAN
EFIAPI
StandardSignatureIsAuthenticAMD (
VOID
);
/**
Return the 32bit CPU family and model value.
@return CPUID[01h].EAX with Processor Type and Stepping ID cleared.
**/
UINT32
EFIAPI
GetCpuFamilyModel (
VOID
);
/**
Return the CPU stepping ID.
@return CPU stepping ID value in CPUID[01h].EAX.
**/
UINT8
EFIAPI
GetCpuSteppingId (
VOID
);
#endif

81
UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c
View File

@@ -1,81 +0,0 @@
/** @file
This library defines some routines that are generic for IA32 family CPU.
The library routines are UEFI specification compliant.
Copyright (c) 2020, AMD Inc. All rights reserved.<BR>
Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Register/Intel/Cpuid.h>
#include <Register/Amd/Cpuid.h>
#include <Library/BaseLib.h>
#include <Library/UefiCpuLib.h>
/**
Determine if the standard CPU signature is "AuthenticAMD".
@retval TRUE The CPU signature matches.
@retval FALSE The CPU signature does not match.
**/
BOOLEAN
EFIAPI
StandardSignatureIsAuthenticAMD (
VOID
)
{
UINT32 RegEbx;
UINT32 RegEcx;
UINT32 RegEdx;
AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx);
return (RegEbx == CPUID_SIGNATURE_AUTHENTIC_AMD_EBX &&
RegEcx == CPUID_SIGNATURE_AUTHENTIC_AMD_ECX &&
RegEdx == CPUID_SIGNATURE_AUTHENTIC_AMD_EDX);
}
/**
Return the 32bit CPU family and model value.
@return CPUID[01h].EAX with Processor Type and Stepping ID cleared.
**/
UINT32
EFIAPI
GetCpuFamilyModel (
VOID
)
{
CPUID_VERSION_INFO_EAX Eax;
AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, NULL, NULL, NULL);
//
// Mask other fields than Family and Model.
//
Eax.Bits.SteppingId = 0;
Eax.Bits.ProcessorType = 0;
Eax.Bits.Reserved1 = 0;
Eax.Bits.Reserved2 = 0;
return Eax.Uint32;
}
/**
Return the CPU stepping ID.
@return CPU stepping ID value in CPUID[01h].EAX.
**/
UINT8
EFIAPI
GetCpuSteppingId (
VOID
)
{
CPUID_VERSION_INFO_EAX Eax;
AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, NULL, NULL, NULL);
return (UINT8)Eax.Bits.SteppingId;
}

8
UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
View File

@@ -24,14 +24,8 @@
# VALID_ARCHITECTURES = IA32 X64
#
[Sources.IA32]
Ia32/InitializeFpu.nasm
[Sources.X64]
X64/InitializeFpu.nasm
[Sources]
BaseUefiCpuLib.c
BaseUefiCpuLibNull.c
[Packages]
MdePkg/MdePkg.dec

18
UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLibNull.c Normal file
View File

@@ -0,0 +1,18 @@
/** @file
This library contains a dummy function to pass build.
Copyright (c) 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Base.h>
/**
Dummy function.
**/
VOID
Dummy (
VOID
)
{
}

68
UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.nasm
View File

@@ -1,68 +0,0 @@
;------------------------------------------------------------------------------
;*
;* Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
;* SPDX-License-Identifier: BSD-2-Clause-Patent
;*
;*
;------------------------------------------------------------------------------
SECTION .rodata
;
; Float control word initial value:
; all exceptions masked, double-precision, round-to-nearest
;
mFpuControlWord: DW 0x27F
;
; Multimedia-extensions control word:
; all exceptions masked, round-to-nearest, flush to zero for masked underflow
;
mMmxControlWord: DD 0x1F80
SECTION .text
;
; Initializes floating point units for requirement of UEFI specification.
;
; This function initializes floating-point control word to 0x027F (all exceptions
; masked,double-precision, round-to-nearest) and multimedia-extensions control word
; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
; for masked underflow).
;
global ASM_PFX(InitializeFloatingPointUnits)
ASM_PFX(InitializeFloatingPointUnits):
push ebx
;
; Initialize floating point units
;
finit
fldcw [mFpuControlWord]
;
; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
; whether the processor supports SSE instruction.
;
mov eax, 1
cpuid
bt edx, 25
jnc Done
;
; Set OSFXSR bit 9 in CR4
;
mov eax, cr4
or eax, BIT9
mov cr4, eax
;
; The processor should support SSE instruction and we can use
; ldmxcsr instruction
;
ldmxcsr [mMmxControlWord]
Done:
pop ebx
ret

51
UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.nasm
View File

@@ -1,51 +0,0 @@
;------------------------------------------------------------------------------
;*
;* Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
;* SPDX-License-Identifier: BSD-2-Clause-Patent
;*
;*
;------------------------------------------------------------------------------
SECTION .rodata
;
; Float control word initial value:
; all exceptions masked, double-extended-precision, round-to-nearest
;
mFpuControlWord: DW 0x37F
;
; Multimedia-extensions control word:
; all exceptions masked, round-to-nearest, flush to zero for masked underflow
;
mMmxControlWord: DD 0x1F80
DEFAULT REL
SECTION .text
;
; Initializes floating point units for requirement of UEFI specification.
;
; This function initializes floating-point control word to 0x027F (all exceptions
; masked,double-precision, round-to-nearest) and multimedia-extensions control word
; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
; for masked underflow).
;
global ASM_PFX(InitializeFloatingPointUnits)
ASM_PFX(InitializeFloatingPointUnits):
;
; Initialize floating point units
;
finit
fldcw [mFpuControlWord]
;
; Set OSFXSR bit 9 in CR4
;
mov rax, cr4
or rax, BIT9
mov cr4, rax
ldmxcsr [mMmxControlWord]
ret