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QuarkPlatformPkg: Add new package for Galileo boards

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Changes for V4
==============
1) Move delete of QuarkSocPkg\QuarkNorthCluster\Binary\QuarkMicrocode
   from QuarkPlatformPkg commit to QuarkSocPkg commit
2) Fix incorrect license header in PlatformSecLibModStrs.uni

Changes for V3
==============
1) Set PcdResetOnMemoryTypeInformationChange FALSE in QuarkMin.dsc
   This is required because QuarkMin.dsc uses the emulated variable
   driver that does not preserve any non-volatile UEFI variables
   across reset.  If the condition is met where the memory type
   information variable needs to be updated, then the system will reset
   every time the UEFI Shell is run.  By setting this PCD to FALSE,
   then reset action is disabled.
2) Move one binary file to QuarkSocBinPkg
3) Change RMU.bin FILE statements to INF statement in DSC FD region
   to be compatible with PACKAGES_PATH search for QuarkSocBinPkg

Changes for V2
==============
1) Use new generic PCI serial driver PciSioSerialDxe in MdeModulePkg
2) Configure PcdPciSerialParameters for PCI serial driver for Quark
3) Use new MtrrLib API to reduce time to set MTRRs for all DRAM
4) Convert all UNI files to utf-8
5) Replace tabs with spaces and remove trailing spaces
6) Add License.txt

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19287 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Michael Kinney
2015-12-15 19:23:57 +00:00
committed by mdkinney
parent 9b6bbcdbfd
commit b303605e1b
190 changed files with 39436 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

48
QuarkPlatformPkg/Acpi/AcpiTables/AcpiTables.inf Normal file
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## @file
# Component description file for PlatformAcpiTable module.
#
# Build acpi table data required by system boot.
# All .asi files tagged with "ToolCode="DUMMY"" in following
# file list are device description and are included by top
# level ASL file which will be dealed with by asl.exe application.
#
# Copyright (c) 2013-2015 Intel Corporation.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = AcpiTables
FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
MODULE_TYPE = USER_DEFINED
VERSION_STRING = 1.0
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
#
[Sources]
Facs/Facs.aslc
Fadt/Fadt2.0.aslc
Hpet/Hpet.aslc
Mcfg/Mcfg.aslc
Dsdt/Platform.asl
CpuPm/CpuPm.asl
Cpu0Cst/Cpu0Cst.asl
Cpu0Ist/Cpu0Ist.asl
Cpu0Tst/Cpu0Tst.asl
[Packages]
MdePkg/MdePkg.dec
QuarkPlatformPkg/QuarkPlatformPkg.dec
QuarkSocPkg/QuarkSocPkg.dec

405
QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Cst/Cpu0Cst.asl Normal file
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/** @file
CPU C State control methods
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
DefinitionBlock (
"Cpu0Cst.aml",
"SSDT",
0x01,
"SsgPmm",
"Cpu0Cst",
0x0011
)
{
External(\_PR.CPU0, DeviceObj)
External (PDC0, IntObj)
External (CFGD, FieldUnitObj)
Scope(\_PR.CPU0)
{
Method (_CST, 0)
{
// If CMP is supported, and OSPM is not capable of independent C1, P, T state
// support for each processor for multi-processor configuration, we will just report
// C1 halt
//
// PDCx[4] = Indicates whether OSPM is not capable of independent C1, P, T state
// support for each processor for multi-processor configuration.
//
If(LAnd(And(CFGD,0x01000000), LNot(And(PDC0,0x10))))
{
Return(Package() {
1,
Package()
{ // C1 halt
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
1,
157,
1000
}
})
}
//
// If MWAIT extensions is supported and OSPM is capable of performing
// native C state instructions for the C2/C3 in multi-processor configuration,
// we report every c state with MWAIT extensions.
//
// PDCx[9] = Indicates whether OSPM is capable of performing native C state instructions
// for the C2/C3 in multi-processor configuration
//
If(LAnd(And(CFGD, 0x200000), And(PDC0,0x200)))
{
//
// If C6 is supported, we report MWAIT C1,C2,C4,C6
//
If(And(CFGD,0x200))
{
Return( Package()
{
4,
Package()
{ // MWAIT C1, hardware coordinated with no bus master avoidance
ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},
1,
1,
1000
},
Package()
{ // MWAIT C2, hardware coordinated with no bus master avoidance
ResourceTemplate(){Register(FFixedHW, 1, 2, 0x10, 1)},
2,
20,
500
},
Package()
{ // MWAIT C4, hardware coordinated with bus master avoidance enabled
ResourceTemplate(){Register(FFixedHW, 1, 2, 0x30, 3)},
3,
100,
100
},
Package()
{ // MWAIT C6, hardware coordinated with bus master avoidance enabled
ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 3)},
3,
140,
10
}
})
}
//
// If C4 is supported, we report MWAIT C1,C2,C4
//
If(And(CFGD,0x080))
{
Return( Package()
{
3,
Package()
{ // MWAIT C1, hardware coordinated with no bus master avoidance
ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},
1,
1,
1000
},
Package()
{ // MWAIT C2, hardware coordinated with no bus master avoidance
ResourceTemplate(){Register(FFixedHW, 1, 2, 0x10, 1)},
2,
20,
500
},
Package()
{ // MWAIT C4, hardware coordinated with bus master avoidance enabled
ResourceTemplate(){Register(FFixedHW, 1, 2, 0x30, 3)},
3,
100,
100
}
})
}
//
// If C2 is supported, we report MWAIT C1,C2
//
If(And(CFGD,0x020))
{
Return( Package()
{
2,
Package()
{ // MWAIT C1, hardware coordinated with no bus master avoidance
ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},
1,
1,
1000
},
Package()
{ // MWAIT C2, hardware coordinated with no bus master avoidance
ResourceTemplate(){Register(FFixedHW, 1, 2, 0x10, 1)},
2,
20,
500
}
})
}
//
// Else we only report MWAIT C1.
//
Return(Package()
{
1,
Package()
{ // MWAIT C1, hardware coordinated with no bus master avoidance
ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},
1,
1,
1000
}
})
}
// If OSPM is only capable of performing native C state instructions for
// the C1 in multi-processor configuration, we report C1 with MWAIT, other
// C states with IO method.
//
// PDCx[8] = Indicates whether OSPM is capable of performing native C state instructions
// for the C1 in multi-processor configuration
//
If(LAnd(And(CFGD, 0x200000), And(PDC0,0x100)))
{
//
// If C6 is supported, we report MWAIT C1, IO C2,C4,C6
//
If(And(CFGD,0x200))
{
Return( Package()
{
4,
Package()
{ // MWAIT C1, hardware coordinated with no bus master avoidance
ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},
1,
1,
1000
},
Package()
{ // IO C2 ("PMBALVL2" will be updated at runtime)
ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},
2,
20,
500
},
Package()
{ // IO C4 ("PMBALVL4" will be updated at runtime)
ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)},
3,
100,
100
},
Package()
{ // IO C6 ("PMBALVL6" will be updated at runtime)
ResourceTemplate () {Register(SystemIO, 8, 0, 0x364C564C41424D50)},
3,
140,
10
}
})
}
//
// If C4 is supported, we report MWAIT C1, IO C2,C4
//
If(And(CFGD,0x080))
{
Return( Package()
{
3,
Package()
{ // MWAIT C1, hardware coordinated with no bus master avoidance
ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},
1,
1,
1000
},
Package()
{ // IO C2 ("PMBALVL2" will be updated at runtime)
ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},
2,
20,
500
},
Package()
{ // IO C4 ("PMBALVL4" will be updated at runtime)
ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)},
3,
100,
100
}
})
}
//
// If C2 is supported, we report MWAIT C1, IO C2
//
If(And(CFGD,0x020))
{
Return( Package()
{
2,
Package()
{ // MWAIT C1, hardware coordinated with no bus master avoidance
ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},
1,
1,
1000
},
Package()
{ // IO C2 ("PMBALVL2" will be updated at runtime)
ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},
2,
20,
500
}
})
}
//
// Else we only report MWAIT C1.
//
Return(Package()
{
1,
Package()
{ // MWAIT C1, hardware coordinated with no bus master avoidance
ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},
1,
1,
1000
}
})
}
//
// If MWAIT is not supported, we report all the c states with IO method
//
//
// If C6 is supported, we report C1 halt, IO C2,C4,C6
//
If(And(CFGD,0x200))
{
Return(Package()
{
4,
Package()
{ // C1 Halt
ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},
1,
1,
1000
},
Package()
{ // IO C2 ("PMBALVL2" will be updated at runtime)
ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},
2,
20,
500
},
Package()
{ // IO C4 ("PMBALVL4" will be updated at runtime)
ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)},
3,
100,
100
},
Package()
{ // IO C6 ("PMBALVL6" will be updated at runtime)
ResourceTemplate () {Register(SystemIO, 8, 0, 0x364C564C41424D50)},
3,
140,
10
}
})
}
//
// If C4 is supported, we report C1 halt, IO C2,C4
//
If(And(CFGD,0x080))
{
Return(Package()
{
3,
Package()
{ // C1 halt
ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},
1,
1,
1000
},
Package()
{ // IO C2 ("PMBALVL2" will be updated at runtime)
ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},
2,
20,
500
},
Package()
{ // IO C4 ("PMBALVL4" will be updated at runtime)
ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)},
3,
100,
100
}
})
}
//
// If C2 is supported, we report C1 halt, IO C2
//
If(And(CFGD,0x020))
{
Return(Package()
{
2,
Package()
{ // C1 halt
ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},
1,
1,
1000
},
Package()
{ // IO C2 ("PMBALVL2" will be updated at runtime)
ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},
2,
20,
500
}
})
}
//
// Else we only report C1 halt.
//
Return(Package()
{
1,
Package()
{ // C1 halt
ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},
1,
1,
1000
}
})
}
}
}

165
QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Ist/Cpu0Ist.asl Normal file
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/** @file
CPU EIST control methods
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
DefinitionBlock (
"CPU0IST.aml",
"SSDT",
0x01,
"SsgPmm",
"Cpu0Ist",
0x0012
)
{
External (PDC0, IntObj)
External (CFGD, FieldUnitObj)
External(\_PR.CPU0, DeviceObj)
Scope(\_PR.CPU0)
{
Method(_PPC,0)
{
Return(ZERO) // Return All States Available.
}
Method(_PCT,0)
{
//
// If GV3 is supported and OSPM is capable of direct access to
// performance state MSR, we use MSR method
//
//
// PDCx[0] = Indicates whether OSPM is capable of direct access to
// performance state MSR.
//
If(LAnd(And(CFGD,0x0001), And(PDC0,0x0001)))
{
Return(Package() // MSR Method
{
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
})
}
//
// Otherwise, we use smi method
//
Return(Package() // SMI Method
{
ResourceTemplate(){Register(SystemIO,16,0,0xB2)},
ResourceTemplate(){Register(SystemIO, 8,0,0xB3)}
})
}
Method(_PSS,0)
{
//
// If OSPM is capable of direct access to performance state MSR,
// we report NPSS, otherwise, we report SPSS.
If (And(PDC0,0x0001))
{
Return(NPSS)
}
Return(SPSS)
}
Name(SPSS,Package()
{
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}
})
Name(NPSS,Package()
{
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}
})
Method(_PSD,0)
{
//
// If CMP is suppored, we report the dependency with two processors
//
If(And(CFGD,0x1000000))
{
//
// If OSPM is capable of hardware coordination of P-states, we report
// the dependency with hardware coordination.
//
// PDCx[11] = Indicates whether OSPM is capable of hardware coordination of P-states
//
If(And(PDC0,0x0800))
{
Return(Package(){
Package(){
5, // # entries.
0, // Revision.
0, // Domain #.
0xFE, // Coord Type- HW_ALL.
2 // # processors.
}
})
}
//
// Otherwise, the dependency with OSPM coordination
//
Return(Package(){
Package(){
5, // # entries.
0, // Revision.
0, // Domain #.
0xFC, // Coord Type- SW_ALL.
2 // # processors.
}
})
}
//
// Otherwise, we report the dependency with one processor
//
Return(Package(){
Package(){
5, // # entries.
0, // Revision.
0, // Domain #.
0xFC, // Coord Type- SW_ALL.
1 // # processors.
}
})
}
}
}

139
QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Tst/Cpu0Tst.asl Normal file
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/** @file
CPU T-state control methods
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
DefinitionBlock (
"CPU0TST.aml",
"SSDT",
0x01,
"SsgPmm",
"Cpu0Tst",
0x0013
)
{
External (PDC0, IntObj)
External (CFGD, FieldUnitObj)
External(\_PR.CPU0, DeviceObj)
External(_PSS)
Scope(\_PR.CPU0)
{
Method(_TPC,0)
{
Return(ZERO) // Return All States Available.
}
Name(TPTC, ResourceTemplate()
{
Memory32Fixed(ReadOnly, 0, 0, FIX1) // IO APIC
})
//
// If OSPM is capable of direct access to on demand throttling MSR,
// we use MSR method;otherwise we use IO method.
//
//
// PDCx[2] = Indicates whether OSPM is capable of direct access to
// on demand throttling MSR.
//
Method(_PTC, 0)
{
If(And(PDC0, 0x0004))
{
Return(Package() // MSR Method
{
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
}
)
}
Return(Package() // IO Method
{
//
// PM IO base ("PMBALVL0" will be updated at runtime)
//
ResourceTemplate(){Register(SystemIO, 4, 1, 0x304C564C41424D50)},
ResourceTemplate(){Register(SystemIO, 4, 1, 0x304C564C41424D50)}
}
)
}
//
// _TSS returned package for IO Method
//
Name(TSSI, Package()
{
Package(){100, 1000, 0, 0x00, 0}
}
)
//
// _TSS returned package for MSR Method
//
Name(TSSM, Package()
{
Package(){100, 1000, 0, 0x00, 0}
}
)
Method(_TSS, 0)
{
//
// If OSPM is capable of direct access to on demand throttling MSR,
// we report TSSM;otherwise report TSSI.
//
If(And(PDC0, 0x0004))
{
Return(TSSM)
}
Return(TSSI)
}
Method(_TSD, 0)
{
//
// If CMP is suppored, we report the dependency with two processors
//
If(LAnd(And(CFGD, 0x1000000), LNot(And(PDC0, 4))))
{
Return(Package()
{
Package()
{
5, // # entries.
0, // Revision.
0, // Domain #.
0xFD, // Coord Type- SW_ANY
2 // # processors.
}
}
)
}
//
// Otherwise, we report the dependency with one processor
//
Return(Package()
{
Package()
{
5, // # entries.
0, // Revision.
0, // Domain #.
0xFC, // Coord Type- SW_ALL
1 // # processors.
}
}
)
}
}
}

79
QuarkPlatformPkg/Acpi/AcpiTables/CpuPm/CpuPm.asl Normal file
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/** @file
CPU power management control methods
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
DefinitionBlock (
"CPUPM.aml",
"SSDT",
0x01,
"SsgPmm",
"CpuPm",
0x0010
)
{
External(\_PR.CPU0, DeviceObj)
External(CFGD, FieldUnitObj)
Scope(\)
{
// Config DWord, modified during POST
// Bit definitions are the same as PPMFlags:
// CFGD[0] = PPM_GV3 = GV3
// CFGD[1] = PPM_TURBO = Turbo Mode
// CFGD[2] = PPM_SUPER_LFM = N/2 Ratio
// CFGD[4] = PPM_C1 = C1 Capable, Enabled
// CFGD[5] = PPM_C2 = C2 Capable, Enabled
// CFGD[6] = PPM_C3 = C3 Capable, Enabled
// CFGD[7] = PPM_C4 = C4 Capable, Enabled
// CFGD[8] = PPM_C5 = C5/Deep C4 Capable, Enabled
// CFGD[9] = PPM_C6 = C6 Capable, Enabled
// CFGD[10] = PPM_C1E = C1E Enabled
// CFGD[11] = PPM_C2E = C2E Enabled
// CFGD[12] = PPM_C3E = C3E Enabled
// CFGD[13] = PPM_C4E = C4E Enabled
// CFGD[14] = PPM_HARD_C4E = Hard C4E Capable, Enabled
// CFGD[16] = PPM_TM1 = Thermal Monitor 1
// CFGD[17] = PPM_TM2 = Thermal Monitor 2
// CFGD[19] = PPM_PHOT = Bi-directional ProcHot
// CFGD[21] = PPM_MWAIT_EXT = MWAIT extensions supported
// CFGD[24] = PPM_CMP = CMP supported, Enabled
// CFGD[28] = PPM_TSTATE = CPU T states supported
//
// Name(CFGD, 0x80000000)
// External Defined in GNVS
Name(PDC0,0x80000000) // CPU0 _PDC Flags.
// We load it in AcpiPlatform
//Name(SSDT,Package()
//{
// "CPU0IST ", 0x80000000, 0x80000000,
// "CPU1IST ", 0x80000000, 0x80000000,
// "CPU0CST ", 0x80000000, 0x80000000,
// "CPU1CST ", 0x80000000, 0x80000000,
//})
}
Scope(\_PR.CPU0)
{
Method(_PDC, 1)
{
//
// Store result of PDC.
//
CreateDWordField(Arg0,8,CAP0) // Point to 3rd DWORD.
Store(CAP0,PDC0) // Store It in PDC0.
}
}
}

44
QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/AD7298.asi Normal file
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/** @file
Analog devices AD7298 ADC.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
Device(ADC1)
{
Name(_HID, "INT3494") // Galileo Version 1 Low-Speed ADC.
Name(_CID, "INT3494")
Name(RBUF, ResourceTemplate()
{
// SPI0: mode 2, 4Mhz, 16-bit data length
SpiSerialBus (0x0000, PolarityLow, FourWireMode, 16, ControllerInitiated, 4000000, ClockPolarityHigh, ClockPhaseFirst, "\\_SB_.PCI0.SPI0",0x00, ResourceConsumer, ,)
// GPIO<0> is SPI0_CS_N
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {QUARK_GPIO0_MAPPING}
})
Method(_CRS, 0x0, NotSerialized)
{
Return(RBUF)
}
Method(_STA, 0x0, NotSerialized)
{
//
// Only Galileo platform has this device.
// EFI_PLATFORM_TYPE enum value Galileo = 6.
//
If(LNotEqual(PTYP, 6))
{
return (0)
}
Return(0xf)
}
}

39
QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/ADC108S102.asi Normal file
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/** @file
TI ADC108S102 ADC.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
Device(ADC2)
{
Name(_HID, "INT3495") // GalileoGen2 Low-Speed ADC.
Name(_CID, "INT3495")
Name(RBUF, ResourceTemplate()
{
SPISerialBus(0x0000, PolarityLow, ThreeWireMode, 0x10, ControllerInitiated, 0x1E8480, ClockPolarityLow, ClockPhaseFirst, "\\_SB.PCI0.SPI0", 0x00, ResourceConsumer, ,)
})
Method(_CRS, 0x0, NotSerialized)
{
Return(RBUF)
}
Method(_STA, 0x0, NotSerialized)
{
//
// Only Platform Type / Id 8 has this device.
//
If(LNotEqual(PTYP, 8))
{
return (0)
}
Return(0xf)
}
}

40
QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/CAT24C08.asi Normal file
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/** @file
ONSEMI CAT24C08 I2C 8KB EEPROM.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
Device(EEP2)
{
Name(_HID, "INT3499") // ONSEMI CAT24C08 I2C 8KB EEPROM.
Name(_CID, "INT3499")
Name(RBUF, ResourceTemplate()
{
I2CSerialBus(0x54, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )
})
Method(_CRS, 0x0, NotSerialized)
{
Return(RBUF)
}
Method(_STA, 0x0, NotSerialized)
{
//
// Only Platform Type / Id 8 has this device.
//
If(LNotEqual(PTYP, 8))
{
return (0)
}
Return(0xf)
}
}

53
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/** @file
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
CY8C9540A 40 Bit I/O Expander with EEPROM.
**/
Device(CY8C)
{
Name(_HID, "INT3490") // Cypress CY8C9540A Io Expander Function.
Name(_CID, "INT3490")
Name(RBUF, ResourceTemplate()
{
I2CSerialBus(0x20, ControllerInitiated, 100000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )
GpioInt (Level, ActiveLow, Exclusive, PullDefault, , "\\_SB.PCI0.GIP0.GPO", 0, ResourceConsumer, , ) {QUARK_GPIO5_MAPPING} /* GPIO<5> is INT_S0 */
})
Method(_CRS, 0x0, NotSerialized)
{
CreateByteField(RBUF, 16, OB1)
if (LEqual (ALTS, 0))
{
Store(0x20, OB1)
}
Else
{
Store(0x21, OB1)
}
Return(RBUF)
}
Method(_STA, 0x0, NotSerialized)
{
//
// Only Galileo platform has this device.
// EFI_PLATFORM_TYPE enum value Galileo = 6.
//
If(LNotEqual(PTYP, 6))
{
return (0)
}
Return(0xf)
}
}

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/** @file
Expose GPIO resources to usermode through client driver.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
Device(GPOT)
{
Name(_HID, "INT349A")
Name(_CID, "INT349A")
Method(_CRS, 0x0, NotSerialized)
{
Name(RBUF, ResourceTemplate()
{
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x1}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x2}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x3}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x4}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x5}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x6}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x7}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x8}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x9}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xa}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xb}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xc}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xd}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xe}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xf}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x2}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x3}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x4}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x5}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x6}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x7}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x8}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x9}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xa}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xb}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xc}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xd}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xe}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xf}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x10}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x11}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x12}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x13}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x14}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x15}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x16}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x17}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x18}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x19}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1a}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1b}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1c}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1d}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1e}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1f}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x20}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x21}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x22}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x23}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x24}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x25}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x26}
GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x27}
})
Return(RBUF)
}
Method(_STA, 0x0, NotSerialized)
{
//
// Only Galileo platform has this device.
// EFI_PLATFORM_TYPE enum value Galileo = 6.
//
If(LNotEqual(PTYP, 6))
{
return (0)
}
Return(0xf)
}
}

254
QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/LpcDev.asi Normal file
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/** @file
Legacy resource template
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef LPC_DEV_ASI
#define LPC_DEV_ASI
Device(RTC)
{
Name(_HID,EISAID("PNP0B00"))
Name(BUF0,ResourceTemplate() {
IO(Decode16,0x70,0x70,0x01,0x04)
IO(Decode16,0x74,0x74,0x01,0x04)
})
Name(BUF1,ResourceTemplate() {
IO(Decode16,0x70,0x70,0x01,0x04)
IO(Decode16,0x74,0x74,0x01,0x04)
IRQNoFlags(){8}
})
Method(_CRS,0,Serialized)
{
If (HPEA)
{
return (BUF0)
}
Else
{
return (BUF1)
}
}
}
Device(PIC)
{
Name(_HID,EISAID("PNP0000"))
Name(_CRS,ResourceTemplate() {
IO(Decode16,0x20,0x20,0x01,0x1E) // length of 1Eh includes all aliases
IO(Decode16,0xA0,0xA0,0x01,0x1E)
IO(Decode16,0x4D0,0x4D0,0x01,0x02)
})
}
Device(TMR)
{
Name(_HID,EISAID("PNP0100"))
Name(BUF0,ResourceTemplate() {
IO(Decode16,0x40,0x40,0x01,0x04)
IO(Decode16,0x50,0x50,0x01,0x04) // alias
})
Name(BUF1,ResourceTemplate() {
IO(Decode16,0x40,0x40,0x01,0x04)
IO(Decode16,0x50,0x50,0x01,0x04) // alias
IRQNoFlags(){0}
})
Method(_CRS,0,Serialized)
{
If (HPEA)
{
return (BUF0)
}
Else
{
return (BUF1)
}
}
}
Device(SPKR)
{
Name(_HID,EISAID("PNP0800"))
Name(_CRS,ResourceTemplate() {
IO(Decode16,0x61,0x61,0x01,0x01)
})
}
Device(XTRA) // all "PNP0C02" devices- pieces that don't fit anywhere else
{
Name(_HID,EISAID("PNP0C02")) // Generic motherboard devices
Name(CRS,
ResourceTemplate()
{
IO(Decode16,0x2E,0x2E,0x01,0x02)
IO(Decode16,0x4E,0x2E,0x01,0x02)
IO(Decode16,0x63,0x61,0x01,0x01)
IO(Decode16,0x65,0x61,0x01,0x01)
IO(Decode16,0x67,0x61,0x01,0x01)
IO(Decode16,0x80,0x80,0x01,0x01)
IO(Decode16,0x84,0x84,0x01,0x04)
IO(Decode16,0x88,0x88,0x01,0x01)
IO(Decode16,0x8c,0x8c,0x01,0x03)
IO(Decode16,0x92,0x92,0x01,0x01)
IO(
Decode16,
0,
0,
0x01,
0x10,
FIX1
)
IO(
Decode16,
0,
0,
0x01,
0x10,
FIX2
)
IO(
Decode16,
0,
0,
0x01,
0x40,
FIX3
)
IO(
Decode16,
0,
0,
0x01,
0x40,
FIX5
)
IO(
Decode16,
0,
0,
0x01,
0x40,
FIX6
)
}
)
Method (_CRS, 0, NotSerialized) {
CreateWordField (CRS, ^FIX1._MIN, MBR0)
Store(\P1BB, MBR0)
CreateWordField (CRS, ^FIX1._MAX, MBR1)
Store(\P1BB, MBR1)
CreateWordField (CRS, ^FIX2._MIN, MBR2)
Store(\PBAB, MBR2)
CreateWordField (CRS, ^FIX2._MAX, MBR3)
Store(\PBAB, MBR3)
CreateWordField (CRS, ^FIX3._MIN, MBR4)
Store(\GP0B, MBR4)
CreateWordField (CRS, ^FIX3._MAX, MBR5)
Store(\GP0B, MBR5)
CreateWordField (CRS, ^FIX5._MIN, MBR8)
Store(\SMBB, MBR8)
CreateWordField (CRS, ^FIX5._MAX, MBR9)
Store(\SMBB, MBR9)
CreateWordField (CRS, ^FIX6._MIN, MBRA)
Store(\WDTB, MBRA)
CreateWordField (CRS, ^FIX6._MAX, MBRB)
Store(\WDTB, MBRB)
return (CRS)
}
}
Device(LGIO) // Legacy GPIO.
{
Name(_HID, "INT3488")
Name(_CID, "INT3488")
Name(CRS,
ResourceTemplate()
{
IO(
Decode16,
0,
0,
0x01,
0x48,
FIX4
)
}
)
Method (_CRS, 0, NotSerialized) {
CreateWordField (CRS, ^FIX4._MIN, MBR6)
Store(\GPAB, MBR6)
CreateWordField (CRS, ^FIX4._MAX, MBR7)
Store(\GPAB, MBR7)
return (CRS)
}
}
Device(HPET) // High Performance Event Timer
{
Name(_HID,EISAID("PNP0103"))
Name(BUF0,ResourceTemplate()
{
IRQNoFlags() {0}
IRQNoFlags() {8}
Memory32Fixed(ReadOnly, 0, 0, FIX1)
})
Method(_STA,0)
{
// Show this Device only if the OS is WINXP or beyond.
If(LGreaterEqual(OSTP,WINDOWS_XP))
{
If(HPEA)
{
Return(0x000F) // Enabled, do Display.
}
}
Else
{
// OS = WIN98, WINME, or WIN2000.
If(HPEA)
{
Return(0x000B) // Enabled, don't Display.
}
}
Return(0x0000) // Return Nothing.
}
Method(_CRS,0,Serialized)
{
CreateDWordField (BUF0, ^FIX1._BAS, MBR0)
Store(\HPTB, MBR0)
CreateDWordField (BUF0, ^FIX1._LEN, MBR1)
Store(\HPTS, MBR1)
Return(BUF0)
}
}
#endif

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QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCA9685.asi Normal file
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/** @file
NXP PCA9685 i2c-accessible PWM/LED controller.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
Device(PWM1)
{
Name(_HID, "INT3492") // NXP PCA9685 i2c-accessible PWM/LED controller.
Name(_CID, "INT3492")
Name(RBUF, ResourceTemplate()
{
I2CSerialBus(0x47, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )
})
Method(_CRS, 0x0, NotSerialized)
{
Return(RBUF)
}
Method(_STA, 0x0, NotSerialized)
{
//
// Only Platform Type / Id 8 has this device.
//
If(LNotEqual(PTYP, 8))
{
return (0)
}
Return(0xf)
}
}

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QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCAL9555A.asi Normal file
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/** @file
NXP PCAL9555A i2c-accessible I/O expander.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
Device(NIO1)
{
Name(_HID, "INT3491") // NXP PCAL9555A i2c-accessible I/O expander.
Name(_CID, "INT3491")
Name(_UID, 1)
Name(RBUF, ResourceTemplate()
{
I2CSerialBus(0x25, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )
})
Method(_CRS, 0x0, NotSerialized)
{
Return(RBUF)
}
Method(_STA, 0x0, NotSerialized)
{
//
// Only Platform Type / Id 8 has this device.
//
If(LNotEqual(PTYP, 8))
{
return (0)
}
Return(0xf)
}
}
Device(NIO2)
{
Name(_HID, "INT3491") // NXP PCAL9555A i2c-accessible I/O expander.
Name(_CID, "INT3491")
Name(_UID, 2)
Name(RBUF, ResourceTemplate()
{
I2CSerialBus(0x26, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )
})
Method(_CRS, 0x0, NotSerialized)
{
Return(RBUF)
}
Method(_STA, 0x0, NotSerialized)
{
//
// Only Platform Type / Id 8 has this device.
//
If(LNotEqual(PTYP, 8))
{
return (0)
}
Return(0xf)
}
}
Device(NIO3)
{
Name(_HID, "INT3491") // NXP PCAL9555A i2c-accessible I/O expander.
Name(_CID, "INT3491")
Name(_UID, 3)
Name(RBUF, ResourceTemplate()
{
I2CSerialBus(0x27, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )
GpioInt (Level, ActiveLow, Exclusive, PullDefault, , "\\_SB.PCI0.GIP0.GPO", 0, ResourceConsumer, , ) {QUARK_GPIO1_MAPPING} /* GPIO<1> is EXP2_INT */
})
Method(_CRS, 0x0, NotSerialized)
{
Return(RBUF)
}
Method(_STA, 0x0, NotSerialized)
{
//
// Only Platform Type / Id 8 has this device.
//
If(LNotEqual(PTYP, 8))
{
return (0)
}
Return(0xf)
}
}

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QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PciHostBridge.asi Normal file
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/** @file
PCI Host Bridge Definitions
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
Name(PBRS, ResourceTemplate() {
WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
ResourceProducer, // bit 0 of general flags is 1
MinFixed, // Range is fixed
MaxFixed, // Range is fixed
PosDecode, // PosDecode
0x0000, // Granularity
0x0000, // Min
0x001f, // Max
0x0000, // Translation
0x0020 // Range Length = Max-Min+1
)
WORDIO( //Consumed-and-produced resource (all I/O below CF8)
ResourceProducer, // bit 0 of general flags is 0
MinFixed, // Range is fixed
MaxFixed, // Range is fixed
PosDecode,
EntireRange,
0x0000, // Granularity
0x0000, // Min
0x0cf7, // Max
0x0000, // Translation
0x0cf8 // Range Length
)
IO( //Consumed resource (CF8-CFF)
Decode16,
0x0cf8,
0xcf8,
1,
8
)
WORDIO( //Consumed-and-produced resource (all I/O above CFF)
ResourceProducer, // bit 0 of general flags is 0
MinFixed, // Range is fixed
MaxFixed, // Range is fixed
PosDecode,
EntireRange,
0x0000, // Granularity
0x0d00, // Min
0xffff, // Max
0x0000, // Translation
0xf300 // Range Length
)
DWORDMEMORY( // descriptor for dos area(0->0xa0000)
ResourceProducer, // bit 0 of general flags is 0
PosDecode,
MinFixed, // Range is fixed
MaxFixed, // Range is Fixed
Cacheable,
ReadWrite,
0x00000000, // Granularity
0x000a0000, // Min
0x000bffff, // Max
0x00000000, // Translation
0x00020000 // Range Length
)
DWORDMemory( // Consumed-and-produced resource for pci memory mapped memory
ResourceProducer, // bit 0 of general flags is 0
PosDecode, // positive Decode
MinFixed, // Range is fixed
MaxFixed, // Range is fixed
Cacheable,
ReadWrite,
0x00000000, // Granularity
0x00000000, // Min (calculated dynamically)
0xfebfffff, // Max = IO Apic base address - 1
0x00000000, // Translation
0xfec00000, // Range Length (calculated dynamically)
, // Optional field left blank
, // Optional field left blank
MEM1 // Name declaration for this descriptor
)
}) // end of CRES Buffer
Method(_CRS, 0x0, NotSerialized)
{
CreateDWordField(PBRS, \_SB.PCI0.MEM1._MIN, MMIN)
CreateDWordField(PBRS, \_SB.PCI0.MEM1._MAX, MMAX)
CreateDWordField(PBRS, \_SB.PCI0.MEM1._LEN, MLEN)
// HMBOUND is PCI memory base
And(MNRD(0x03, 0x08), 0xFFFFF000, MMIN)
Add(Subtract(MMAX, MMIN), 1, MLEN)
Return(PBRS)
}
// Message Nework Registers
OperationRegion(MNR, PCI_Config, 0xD0, 0x10)
Field(MNR, DWordAcc, NoLock, Preserve)
{
MCR, 32, // Message Control Register
MDR, 32 // Message Data Register
}
// Message Nework Read Method
// Arg0 = Port
// Arg1 = RegAddress
// return 32 bit register value
Method(MNRD, 2, Serialized)
{
Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0)
Or(Local0, 0x100000F0, Local0)
Store(Local0, MCR)
Return(MDR)
}
// Message Nework Write Method
// Arg0 = Port
// Arg1 = RegAddress
// Arg2 = 32 bit write value
Method(MNWR, 3, Serialized)
{
Store(Arg2, MDR)
Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0)
Or(Local0, 0x110000F0, Local0)
Store(Local0, MCR)
}
Method(_PRT, 0, NotSerialized)
{
If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing
{
Return (
Package()
{
// Bus 0, Device 20 - IOSFAHB Bridge
Package() {0x0014ffff, 0, \_SB.PCI0.LPC.LNKA, 0}, // INTA
Package() {0x0014ffff, 1, \_SB.PCI0.LPC.LNKB, 0}, // INTB
Package() {0x0014ffff, 2, \_SB.PCI0.LPC.LNKC, 0}, // INTC
Package() {0x0014ffff, 3, \_SB.PCI0.LPC.LNKD, 0}, // INTD
// Bus 0, Device 21 - IOSFAHB Bridge
Package() {0x0015ffff, 0, \_SB.PCI0.LPC.LNKA, 0}, // INTA
Package() {0x0015ffff, 1, \_SB.PCI0.LPC.LNKB, 0}, // INTB
Package() {0x0015ffff, 2, \_SB.PCI0.LPC.LNKC, 0}, // INTC
Package() {0x0015ffff, 3, \_SB.PCI0.LPC.LNKD, 0}, // INTD
// Bus 0, Device 23 - PCIe port 0
Package() {0x0017ffff, 0, \_SB.PCI0.LPC.LNKE, 0}, // INTA
Package() {0x0017ffff, 1, \_SB.PCI0.LPC.LNKF, 0}, // INTB
Package() {0x0017ffff, 2, \_SB.PCI0.LPC.LNKG, 0}, // INTC
Package() {0x0017ffff, 3, \_SB.PCI0.LPC.LNKH, 0}, // INTD
// Bus 0, Device 31
Package() {0x001fffff, 0, \_SB.PCI0.LPC.LNKA, 0}, // LPC Bridge
}
)
}
else {
Return (
Package()
{
// Bus 0, Device 20 - IOSFAHB Bridge
Package() {0x0014ffff, 0, 0, 16}, // INTA
Package() {0x0014ffff, 1, 0, 17}, // INTB
Package() {0x0014ffff, 2, 0, 18}, // INTC
Package() {0x0014ffff, 3, 0, 19}, // INTD
// Bus 0, Device 21 - IOSFAHB Bridge
Package() {0x0015ffff, 0, 0, 16}, // INTA
Package() {0x0015ffff, 1, 0, 17}, // INTB
Package() {0x0015ffff, 2, 0, 18}, // INTC
Package() {0x0015ffff, 3, 0, 19}, // INTD
// Bus 0, Device 23 - PCIe port 0
Package() {0x0017ffff, 0, 0, 20}, // INTA
Package() {0x0017ffff, 1, 0, 21}, // INTB
Package() {0x0017ffff, 2, 0, 22}, // INTC
Package() {0x0017ffff, 3, 0, 23}, // INTD
// Bus 0, Device 31
Package() {0x001fffff, 0, 0, 16}, // LPC Bridge
}
)
}
}

558
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/** @file
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
// Interrupts can be DEB8=all except 13,8,6,2,1,0
#ifndef PCIIRQ_ASI
#define PCIIRQ_ASI
OperationRegion(PRR0, PCI_Config, 0x60, 0x08)
Field(PRR0, ANYACC, NOLOCK, PRESERVE)
{
PIRA, 8,
PIRB, 8,
PIRC, 8,
PIRD, 8,
PIRE, 8,
PIRF, 8,
PIRG, 8,
PIRH, 8
}
Device(LNKA) // PCI IRQ link A
{
Name(_HID,EISAID("PNP0C0F"))
Name(_UID, 1)
Method(_STA,0,NotSerialized)
{
If(And(PIRA, 0x80))
{
Return(0x9)
}
Else
{
Return(0xB)
} // Don't display
}
Method(_DIS,0,NotSerialized)
{
Or(PIRA, 0x80, PIRA)
}
Method(_CRS,0,Serialized)
{
Name(BUF0,
ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){0}})
// Define references to buffer elements
CreateWordField (BUF0, 0x01, IRQW) // IRQ low
// Write current settings into IRQ descriptor
If (And(PIRA, 0x80))
{
Store(Zero, Local0)
}
Else
{
Store(One,Local0)
}
// Shift 1 by value in register 70
ShiftLeft(Local0,And(PIRA,0x0F),IRQW) // Save in buffer
Return(BUF0) // Return Buf0
} // End of _CRS method
Name(_PRS,
ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})
Method(_SRS,1,NotSerialized)
{
CreateWordField (ARG0, 0x01, IRQW) // IRQ low
FindSetRightBit(IRQW,Local0) // Set IRQ
If (LNotEqual(IRQW,Zero))
{
And(Local0, 0x7F,Local0)
Decrement(Local0)
}
Else
{
Or(Local0, 0x80,Local0)
}
store(Local0, PIRA)
} // End of _SRS Method
}
Device(LNKB) // PCI IRQ link B
{
Name(_HID,EISAID("PNP0C0F"))
Name(_UID, 2)
Method(_STA,0,NotSerialized)
{
If(And(PIRB, 0x80))
{
Return(0x9)
}
Else
{
Return(0xB)
} // Don't display
}
Method(_DIS,0,NotSerialized)
{
Or(PIRB, 0x80,PIRB)
}
Method(_CRS,0,Serialized)
{
Name(BUF0,
ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){0}})
// Define references to buffer elements
CreateWordField (BUF0, 0x01, IRQW) // IRQ low
// Write current settings into IRQ descriptor
If (And(PIRB, 0x80))
{
Store(Zero, Local0)
}
Else
{
Store(One,Local0)
}
// Shift 1 by value in register 70
ShiftLeft(Local0,And(PIRB,0x0F),IRQW) // Save in buffer
Return(BUF0) // Return Buf0
} // End of _CRS method
Name(_PRS,
ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})
Method(_SRS,1,NotSerialized)
{
CreateWordField (ARG0, 0x01, IRQW) // IRQ low
FindSetRightBit(IRQW,Local0) // Set IRQ
If (LNotEqual(IRQW,Zero))
{
And(Local0, 0x7F,Local0)
Decrement(Local0)
}
Else
{
Or(Local0, 0x80,Local0)
}
Store(Local0, PIRB)
} // End of _SRS Method
}
Device(LNKC) // PCI IRQ link C
{
Name(_HID,EISAID("PNP0C0F"))
Name(_UID, 3)
Method(_STA,0,NotSerialized)
{
If(And(PIRC, 0x80))
{
Return(0x9)
}
Else
{
Return(0xB)
} // Don't display
}
Method(_DIS,0,NotSerialized)
{
Or(PIRC, 0x80,PIRC)
}
Method(_CRS,0,Serialized)
{
Name(BUF0,
ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){0}})
// Define references to buffer elements
CreateWordField (BUF0, 0x01, IRQW) // IRQ low
// Write current settings into IRQ descriptor
If (And(PIRC, 0x80))
{
Store(Zero, Local0)
}
Else
{
Store(One,Local0)
} // Shift 1 by value in register 70
ShiftLeft(Local0,And(PIRC,0x0F),IRQW) // Save in buffer
Return(BUF0) // Return Buf0
} // End of _CRS method
Name(_PRS,
ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})
Method(_SRS,1,NotSerialized)
{
CreateWordField (ARG0, 0x01, IRQW) // IRQ low
FindSetRightBit(IRQW,Local0) // Set IRQ
If (LNotEqual(IRQW,Zero))
{
And(Local0, 0x7F,Local0)
Decrement(Local0)
}
Else {
Or(Local0, 0x80,Local0)
}
Store(Local0, PIRC)
} // End of _SRS Method
}
Device(LNKD) // PCI IRQ link D
{
Name(_HID,EISAID("PNP0C0F"))
Name(_UID, 4)
Method(_STA,0,NotSerialized)
{
If(And(PIRD, 0x80))
{
Return(0x9)
}
Else
{
Return(0xB)
} // Don't display
}
Method(_DIS,0,NotSerialized)
{
Or(PIRD, 0x80,PIRD)
}
Method(_CRS,0,Serialized)
{
Name(BUF0,
ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){0}})
// Define references to buffer elements
CreateWordField (BUF0, 0x01, IRQW) // IRQ low
// Write current settings into IRQ descriptor
If (And(PIRD, 0x80))
{
Store(Zero, Local0)
}
Else
{
Store(One,Local0)
} // Shift 1 by value in register 70
ShiftLeft(Local0,And(PIRD,0x0F),IRQW) // Save in buffer
Return(BUF0) // Return Buf0
} // End of _CRS method
Name(_PRS,
ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})
Method(_SRS,1,NotSerialized)
{
CreateWordField (ARG0, 0x01, IRQW) // IRQ low
FindSetRightBit(IRQW,Local0)// Set IRQ
If (LNotEqual(IRQW,Zero))
{
And(Local0, 0x7F,Local0)
Decrement(Local0)
}
Else
{
Or(Local0, 0x80,Local0)
}
Store(Local0, PIRD)
} // End of _SRS Method
}
Device(LNKE) // PCI IRQ link E
{
Name(_HID,EISAID("PNP0C0F"))
Name(_UID, 5)
Method(_STA,0,NotSerialized)
{
If(And(PIRE, 0x80))
{
Return(0x9)
}
Else
{
Return(0xB)
} // Don't display
}
Method(_DIS,0,NotSerialized)
{
Or(PIRE, 0x80, PIRE)
}
Method(_CRS,0,Serialized)
{
Name(BUF0,
ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){0}})
// Define references to buffer elements
CreateWordField (BUF0, 0x01, IRQW) // IRQ low
// Write current settings into IRQ descriptor
If (And(PIRE, 0x80))
{
Store(Zero, Local0)
}
Else
{
Store(One,Local0)
}
// Shift 1 by value in register 70
ShiftLeft(Local0,And(PIRE,0x0F),IRQW) // Save in buffer
Return(BUF0) // Return Buf0
} // End of _CRS method
Name(_PRS,
ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})
Method(_SRS,1,NotSerialized)
{
CreateWordField (ARG0, 0x01, IRQW) // IRQ low
FindSetRightBit(IRQW,Local0) // Set IRQ
If (LNotEqual(IRQW,Zero))
{
And(Local0, 0x7F,Local0)
Decrement(Local0)
}
Else
{
Or(Local0, 0x80,Local0)
}
store(Local0, PIRE)
} // End of _SRS Method
}
Device(LNKF) // PCI IRQ link F
{
Name(_HID,EISAID("PNP0C0F"))
Name(_UID, 6)
Method(_STA,0,NotSerialized)
{
If(And(PIRF, 0x80))
{
Return(0x9)
}
Else
{
Return(0xB)
} // Don't display
}
Method(_DIS,0,NotSerialized)
{
Or(PIRB, 0x80,PIRF)
}
Method(_CRS,0,Serialized)
{
Name(BUF0,
ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){0}})
// Define references to buffer elements
CreateWordField (BUF0, 0x01, IRQW) // IRQ low
// Write current settings into IRQ descriptor
If (And(PIRF, 0x80))
{
Store(Zero, Local0)
}
Else
{
Store(One,Local0)
}
// Shift 1 by value in register 70
ShiftLeft(Local0,And(PIRF,0x0F),IRQW) // Save in buffer
Return(BUF0) // Return Buf0
} // End of _CRS method
Name(_PRS,
ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})
Method(_SRS,1,NotSerialized)
{
CreateWordField (ARG0, 0x01, IRQW) // IRQ low
FindSetRightBit(IRQW,Local0) // Set IRQ
If (LNotEqual(IRQW,Zero))
{
And(Local0, 0x7F,Local0)
Decrement(Local0)
}
Else
{
Or(Local0, 0x80,Local0)
}
Store(Local0, PIRF)
} // End of _SRS Method
}
Device(LNKG) // PCI IRQ link G
{
Name(_HID,EISAID("PNP0C0F"))
Name(_UID, 7)
Method(_STA,0,NotSerialized)
{
If(And(PIRG, 0x80))
{
Return(0x9)
}
Else
{
Return(0xB)
} // Don't display
}
Method(_DIS,0,NotSerialized)
{
Or(PIRG, 0x80,PIRG)
}
Method(_CRS,0,Serialized)
{
Name(BUF0,
ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){0}})
// Define references to buffer elements
CreateWordField (BUF0, 0x01, IRQW) // IRQ low
// Write current settings into IRQ descriptor
If (And(PIRG, 0x80))
{
Store(Zero, Local0)
}
Else
{
Store(One,Local0)
} // Shift 1 by value in register 70
ShiftLeft(Local0,And(PIRG,0x0F),IRQW) // Save in buffer
Return(BUF0) // Return Buf0
} // End of _CRS method
Name(_PRS,
ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})
Method(_SRS,1,NotSerialized)
{
CreateWordField (ARG0, 0x01, IRQW) // IRQ low
FindSetRightBit(IRQW,Local0) // Set IRQ
If (LNotEqual(IRQW,Zero))
{
And(Local0, 0x7F,Local0)
Decrement(Local0)
}
Else {
Or(Local0, 0x80,Local0)
}
Store(Local0, PIRG)
} // End of _SRS Method
}
Device(LNKH) // PCI IRQ link H
{
Name(_HID,EISAID("PNP0C0F"))
Name(_UID, 8)
Method(_STA,0,NotSerialized)
{
If(And(PIRH, 0x80))
{
Return(0x9)
}
Else
{
Return(0xB)
} // Don't display
}
Method(_DIS,0,NotSerialized)
{
Or(PIRH, 0x80,PIRH)
}
Method(_CRS,0,Serialized)
{
Name(BUF0,
ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){0}})
// Define references to buffer elements
CreateWordField (BUF0, 0x01, IRQW) // IRQ low
// Write current settings into IRQ descriptor
If (And(PIRH, 0x80))
{
Store(Zero, Local0)
}
Else
{
Store(One,Local0)
} // Shift 1 by value in register 70
ShiftLeft(Local0,And(PIRH,0x0F),IRQW) // Save in buffer
Return(BUF0) // Return Buf0
} // End of _CRS method
Name(_PRS,
ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})
Method(_SRS,1,NotSerialized)
{
CreateWordField (ARG0, 0x01, IRQW) // IRQ low
FindSetRightBit(IRQW,Local0)// Set IRQ
If (LNotEqual(IRQW,Zero))
{
And(Local0, 0x7F,Local0)
Decrement(Local0)
}
Else
{
Or(Local0, 0x80,Local0)
}
Store(Local0, PIRH)
} // End of _SRS Method
}
#endif

133
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/** @file
PCI express expansion ports
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef PcieExpansionPrt_asi
#define PcieExpansionPrt_asi
Device (PEX0) // PCI express bus bridged from [Bus 0, Device 23, Function 0]
{
Name(_ADR,0x00170000) // Device (HI WORD)=23, Func (LO WORD)=0
Name(_PRW,Package(){0x11,0x03}) // GPE pin 0x11, Wake from S3 -- PCI PME#
OperationRegion (PES0,PCI_Config,0x40,0xA0)
Field (PES0, AnyAcc, NoLock, Preserve)
{
Offset(0x1A), // SLSTS - Slot Status Register
ABP0, 1, // Bit 0, Attention Button Pressed
, 2,
PDC0, 1, // Bit 3, Presence Detect Changed
, 2,
PDS0, 1, // Bit 6, Presence Detect State
, 1,
LSC0, 1, // Bit 8, Link Active State Changed
offset (0x20),
, 16,
PMS0, 1, // Bit 16, PME Status
offset (0x98),
, 30,
HPE0, 1, // Bit 30, Hot Plug SCI Enable
PCE0, 1, // Bit 31, Power Management SCI Enable.
, 30,
HPS0, 1, // Bit 30, Hot Plug SCI Status
PCS0, 1, // Bit 31, Power Management SCI Status.
}
Method(_PRT,0,NotSerialized) {
If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing
{
Return (
Package()
{
// Port 0: INTA->PIRQE,INTB->PIRQF,INTC->PIRQG,INTD->PIRQH
Package() {0x0000ffff, 0, \_SB_.PCI0.LPC.LNKE, 0}, // PCI Slot 1
Package() {0x0000ffff, 1, \_SB_.PCI0.LPC.LNKF, 0},
Package() {0x0000ffff, 2, \_SB_.PCI0.LPC.LNKG, 0},
Package() {0x0000ffff, 3, \_SB_.PCI0.LPC.LNKH, 0},
}
)
}
else // IOAPIC Routing
{
Return (
Package()
{
// Port 0: INTA->PIRQE,INTB->PIRQF,INTC->PIRQG,INTD->PIRQH
Package() {0x0000ffff, 0, 0, 20}, // PCI Slot 1
Package() {0x0000ffff, 1, 0, 21},
Package() {0x0000ffff, 2, 0, 22},
Package() {0x0000ffff, 3, 0, 23},
}
)
}
}
}
Device (PEX1) // PCI express bus bridged from [Bus 0, Device 23, Function 1]
{
Name(_ADR,0x00170001) // Device (HI WORD)=23, Func (LO WORD)=1
Name(_PRW,Package(){0x11,0x03}) // GPE pin 0x11, Wake from S3 -- PCI PME#
OperationRegion (PES1,PCI_Config,0x40,0xA0)
Field (PES1, AnyAcc, NoLock, Preserve)
{
Offset(0x1A), // SLSTS - Slot Status Register
ABP1, 1, // Bit 0, Attention Button Pressed
, 2,
PDC1, 1, // Bit 3, Presence Detect Changed
, 2,
PDS1, 1, // Bit 6, Presence Detect State
, 1,
LSC1, 1, // Bit 8, Link Active State Changed
offset (0x20),
, 16,
PMS1, 1, // Bit 16, PME Status
offset (0x98),
, 30,
HPE1, 1, // Bit 30, Hot Plug SCI Enable
PCE1, 1, // Bit 31, Power Management SCI Enable.
, 30,
HPS1, 1, // Bit 30, Hot Plug SCI Status
PCS1, 1, // Bit 31, Power Management SCI Status.
}
Method(_PRT,0,NotSerialized) {
If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing
{
Return (
Package()
{
// Port 1: INTA->PIRQF,INTB->PIRQG,INTC->PIRQH,INTD->PIRQE
Package() {0x0000ffff, 0, \_SB_.PCI0.LPC.LNKF, 0},
Package() {0x0000ffff, 1, \_SB_.PCI0.LPC.LNKG, 0},
Package() {0x0000ffff, 2, \_SB_.PCI0.LPC.LNKH, 0},
Package() {0x0000ffff, 3, \_SB_.PCI0.LPC.LNKE, 0},
}
)
}
else // IOAPIC Routing
{
Return (
Package()
{
// Port 1: INTA->PIRQF,INTB->PIRQG,INTC->PIRQH,INTD->PIRQE
Package() {0x0000ffff, 0, 0, 21},
Package() {0x0000ffff, 1, 0, 22},
Package() {0x0000ffff, 2, 0, 23},
Package() {0x0000ffff, 3, 0, 20},
}
)
}
}
}
#endif

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/** @file
Contains root level name space objects for the platform
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// OS TYPE DEFINITION
//
#define WINDOWS_XP 0x01
#define WINDOWS_XP_SP1 0x02
#define WINDOWS_XP_SP2 0x04
#define WINDOWS_2003 0x08
#define WINDOWS_Vista 0x10
#define WINDOWS_WIN7 0x11
#define WINDOWS_WIN8 0x12
#define WINDOWS_WIN8_1 0x13
#define LINUX 0xF0
//
// GPIO Interrupt Connection Resource Descriptor (GpioInt) usage.
// GpioInt() descriptors maybe used in this file and included .asi files.
//
// The mapping below was provided by the first OS user that requested
// GpioInt() support.
// Other OS users that need GpioInt() support must use the following mapping.
//
#define QUARK_GPIO8_MAPPING 0x00
#define QUARK_GPIO9_MAPPING 0x01
#define QUARK_GPIO_SUS0_MAPPING 0x02
#define QUARK_GPIO_SUS1_MAPPING 0x03
#define QUARK_GPIO_SUS2_MAPPING 0x04
#define QUARK_GPIO_SUS3_MAPPING 0x05
#define QUARK_GPIO_SUS4_MAPPING 0x06
#define QUARK_GPIO_SUS5_MAPPING 0x07
#define QUARK_GPIO0_MAPPING 0x08
#define QUARK_GPIO1_MAPPING 0x09
#define QUARK_GPIO2_MAPPING 0x0A
#define QUARK_GPIO3_MAPPING 0x0B
#define QUARK_GPIO4_MAPPING 0x0C
#define QUARK_GPIO5_MAPPING 0x0D
#define QUARK_GPIO6_MAPPING 0x0E
#define QUARK_GPIO7_MAPPING 0x0F
DefinitionBlock (
"Platform.aml",
"DSDT",
1,
"INTEL ",
"QuarkNcSocId",
3)
{
//
// Global Variables
//
Name(\GPIC, 0x0)
//
// Port 80
//
OperationRegion (DBG0, SystemIO, 0x80, 1)
Field (DBG0, ByteAcc, NoLock, Preserve)
{ IO80,8 }
//
// Access CMOS range
//
OperationRegion (ACMS, SystemIO, 0x72, 2)
Field (ACMS, ByteAcc, NoLock, Preserve)
{ INDX, 8, DATA, 8 }
//
// Global NVS Memory Block
//
OperationRegion (MNVS, SystemMemory, 0xFFFF0000, 512)
Field (MNVS, ByteAcc, NoLock, Preserve)
{
OSTP, 32,
CFGD, 32,
HPEA, 32, // HPET Enabled ?
P1BB, 32, // Pm1blkIoBaseAddress;
PBAB, 32, // PmbaIoBaseAddress;
GP0B, 32, // Gpe0blkIoBaseAddress;
GPAB, 32, // GbaIoBaseAddress;
SMBB, 32, // SmbaIoBaseAddress;
NRV1, 32, // GNVS reserved field 1.
WDTB, 32, // WdtbaIoBaseAddress;
HPTB, 32, // HpetBaseAddress;
HPTS, 32, // HpetSize;
PEXB, 32, // PciExpressBaseAddress;
PEXS, 32, // PciExpressSize;
RCBB, 32, // RcbaMmioBaseAddress;
RCBS, 32, // RcbaMmioSize;
APCB, 32, // IoApicBaseAddress;
APCS, 32, // IoApicSize;
TPMP, 32, // TpmPresent ?
DBGP, 32, // DBG2 Present?
PTYP, 32, // Set to one of EFI_PLATFORM_TYPE enums.
ALTS, 32, // Use alternate I2c SLA addresses.
}
OperationRegion (GPEB, SystemIO, 0x1100, 0x40) //GPE Block
Field (GPEB, AnyAcc, NoLock, Preserve)
{
Offset(0x10),
SMIE, 32, // SMI Enable
SMIS, 32, // SMI Status
}
//
// Processor Objects
//
Scope(\_PR) {
//
// IO base will be updated at runtime with search key "PRIO"
//
Processor (CPU0, 0x01, 0x4F495250, 0x06) {}
}
//
// System Sleep States
//
Name (\_S0,Package (){0,0,0,0})
Name (\_S3,Package (){5,0,0,0})
Name (\_S4,Package (){6,0,0,0})
Name (\_S5,Package (){7,0,0,0})
//
// General Purpose Event
//
Scope(\_GPE)
{
//
// EGPE generated GPE
//
Method(_L0D, 0x0, NotSerialized)
{
//
// Check EGPE for this wake event
//
Notify (\_SB.SLPB, 0x02)
}
//
// GPIO generated GPE
//
Method(_L0E, 0x0, NotSerialized)
{
//
// Check GPIO for this wake event
//
Notify (\_SB.PWRB, 0x02)
}
//
// SCLT generated GPE
//
Method(_L0F, 0x0, NotSerialized)
{
//
// Check SCLT for this wake event
//
Notify (\_SB.PCI0.SDIO, 0x02)
Notify (\_SB.PCI0.URT0, 0x02)
Notify (\_SB.PCI0.USBD, 0x02)
Notify (\_SB.PCI0.EHCI, 0x02)
Notify (\_SB.PCI0.OHCI, 0x02)
Notify (\_SB.PCI0.URT1, 0x02)
Notify (\_SB.PCI0.ENT0, 0x02)
Notify (\_SB.PCI0.ENT1, 0x02)
Notify (\_SB.PCI0.SPI0, 0x02)
Notify (\_SB.PCI0.SPI1, 0x02)
Notify (\_SB.PCI0.GIP0, 0x02)
}
//
// Remote Management Unit generated GPE
//
Method(_L10, 0x0, NotSerialized)
{
//
// Check Remote Management Unit for this wake event.
//
}
//
// PCIE generated GPE
//
Method(_L11, 0x0, NotSerialized)
{
//
// Check PCIE for this wake event
//
Notify (\_SB.PCI0.PEX0, 0x02)
Notify (\_SB.PCI0.PEX1, 0x02)
}
}
//
// define Sleeping button as mentioned in ACPI spec 2.0
//
Device (\_SB.SLPB)
{
Name (_HID, EISAID ("PNP0C0E"))
Method (_PRW, 0, NotSerialized)
{
Return (Package (0x02) {0x0D,0x04})
}
}
//
// define Power Button
//
Device (\_SB.PWRB)
{
Name (_HID, EISAID ("PNP0C0C"))
Method (_PRW, 0, NotSerialized)
{
Return (Package (0x02) {0x0E,0x04})
}
}
//
// System Wake up
//
Method(_WAK, 1, Serialized)
{
// Do nothing here
Return (0)
}
//
// System sleep down
//
Method (_PTS, 1, NotSerialized)
{
// Get ready for S3 sleep
if (Lequal(Arg0,3))
{
Store(0xffffffff,SMIS) // clear SMI status
Store(SMIE, Local0) // SMI Enable
Or(Local0,0x4,SMIE) // Generate SMI on sleep
}
}
//
// Determing PIC mode
//
Method(\_PIC, 1, NotSerialized)
{
Store(Arg0,\GPIC)
}
//
// System Bus
//
Scope(\_SB)
{
Device(PCI0)
{
Name(_HID,EISAID ("PNP0A08")) // PCI Express Root Bridge
Name(_CID,EISAID ("PNP0A03")) // Compatible PCI Root Bridge
Name(_ADR,0x00000000) // Device (HI WORD)=0, Func (LO WORD)=0
Method (_INI)
{
Store(LINUX, OSTP) // Set the default os is Linux
If (CondRefOf (_OSI, local0))
{
//
//_OSI is supported, so it is WinXp or Win2003Server
//
If (\_OSI("Windows 2001"))
{
Store (WINDOWS_XP, OSTP)
}
If (\_OSI("Windows 2001 SP1"))
{
Store (WINDOWS_XP_SP1, OSTP)
}
If (\_OSI("Windows 2001 SP2"))
{
Store (WINDOWS_XP_SP2, OSTP)
}
If (\_OSI("Windows 2001.1"))
{
Store (WINDOWS_2003, OSTP)
}
If (\_OSI("Windows 2006"))
{
Store (WINDOWS_Vista, OSTP)
}
If (\_OSI("Windows 2009"))
{
Store (WINDOWS_WIN7, OSTP)
}
If (\_OSI("Windows 2012"))
{
Store (WINDOWS_WIN8, OSTP)
}
If (\_OSI("Windows 2013"))
{
Store (WINDOWS_WIN8_1, OSTP)
}
If (\_OSI("Linux"))
{
Store (LINUX, OSTP)
}
}
}
Include ("PciHostBridge.asi") // PCI0 Host bridge
Include ("QNC.asi") // QNC miscellaneous
Include ("PcieExpansionPrt.asi") // PCIe expansion bridges/devices
Include ("QuarkSouthCluster.asi") // Quark South Cluster devices
Include ("QNCLpc.asi") // LPC bridge device
Include ("QNCApic.asi") // QNC I/O Apic device
}
//
// Include asi files for I2C and SPI onboard devices.
// Devices placed here instead of below relevant controllers.
// Hardware topology information is maintained by the
// ResourceSource arg to the I2CSerialBus/SPISerialBus macros
// within the device asi files.
//
Include ("Tpm.asi") // TPM device.
Include ("CY8C9540A.asi") // CY8C9540A 40Bit I/O Expander & EEPROM
Include ("PCAL9555A.asi") // NXP PCAL9555A I/O expander.
Include ("PCA9685.asi") // NXP PCA9685 PWM/LED controller.
Include ("CAT24C08.asi") // ONSEMI CAT24C08 I2C 8KB EEPROM.
Include ("AD7298.asi") // Analog devices AD7298 ADC.
Include ("ADC108S102.asi") // TI ADC108S102 ADC.
Include ("GpioClient.asi") // Software device to expose GPIO
}
}

55
QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNC.asi Normal file
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/** @file
QNC devices
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef QNC_ASI
#define QNC_ASI
Device(IOCM) // I/O controller miscellaneous
{
Name(_HID,EISAID("PNP0C02")) // System board resources device node ID
Name(CRS, ResourceTemplate()
{
// PCIEXBAR memory range
Memory32Fixed(ReadOnly, 0, 0, FIX1)
// RCRB memory range
Memory32Fixed(ReadOnly, 0, 0, FIX2)
// Option ROM shadow memory range
Memory32Fixed(ReadOnly, 0x000C0000, 0x20000)
// BIOS ROM shadow memory range
Memory32Fixed(ReadOnly, 0x000E0000, 0x20000)
// BIOS Firmware just below 4GByte of memory 8MBytes
Memory32Fixed(ReadOnly, 0xFF800000, 0x800000)
}
)
Method (_CRS, 0, NotSerialized) {
CreateDWordField (CRS, ^FIX1._BAS, MBR0)
Store(\PEXB, MBR0)
CreateDWordField (CRS, ^FIX1._LEN, MBR1)
Store(\PEXS, MBR1)
CreateDWordField (CRS, ^FIX2._BAS, MBR2)
Store(\RCBB, MBR2)
CreateDWordField (CRS, ^FIX2._LEN, MBR3)
Store(\RCBS, MBR3)
Return (CRS)
}
}
#endif

38
QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNCApic.asi Normal file
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/** @file
QNC I/O Apic devices
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef QNC_APIC_ASI
#define QNC_APIC_ASI
Device(APIC)
{
Name(_HID,EISAID("PNP0003")) // APIC resources
Name(CRS, ResourceTemplate()
{
Memory32Fixed(ReadOnly, 0, 0, FIX1) // IO APIC
}
)
Method (_CRS, 0, NotSerialized) {
CreateDWordField (CRS, ^FIX1._BAS, MBR0)
Store(\APCB, MBR0)
CreateDWordField (CRS, ^FIX1._LEN, MBR1)
Store(\APCS, MBR1)
Return (CRS)
}
}
#endif

29
QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNCLpc.asi Normal file
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/** @file
Lpc devices and control methods
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef QNC_LPC_ASI
#define QNC_LPC_ASI
Device(LPC)
{
Name(_ADR,0x001f0000) // Device (HI WORD)=31, Func (LO WORD)=0
Include ("PciIrq.asi") // PCI routing control methods
Include ("LpcDev.asi") // Static Lpc device resource declaration
}
#endif

116
QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QuarkSouthCluster.asi Normal file
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/** @file
Quark South Cluster Devices.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef QuarkSouthCluster_asi
#define QuarkSouthCluster_asi
Device (SDIO) // SDIO [Bus 0, Device 20, Function 0]
{
Name(_ADR,0x00140000) // Device (HI WORD)=20, Func (LO WORD)=0
Name(_STA,0xF) // Enabled, do Display
Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#
}
Device (URT0) // UART0 [Bus 0, Device 20, Function 1]
{
Name(_ADR,0x00140001) // Device (HI WORD)=20, Func (LO WORD)=1
Name(_STA,0xF) // Enabled, do Display
Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#
}
Device (USBD) // USB Device [Bus 0, Device 20, Function 2]
{
Name(_ADR,0x00140002) // Device (HI WORD)=20, Func (LO WORD)=2
Name(_STA,0xF) // Enabled, do Display
Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#
}
Device (EHCI) // EHCI [Bus 0, Device 20, Function 3]
{
Name(_ADR,0x00140003) // Device (HI WORD)=20, Func (LO WORD)=3
Name(_STA,0xF) // Enabled, do Display
Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#
}
Device (OHCI) // OHCI [Bus 0, Device 20, Function 4]
{
Name(_ADR,0x00140004) // Device (HI WORD)=20, Func (LO WORD)=4
Name(_STA,0xF) // Enabled, do Display
Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#
}
Device (URT1) // UART1 [Bus 0, Device 20, Function 5]
{
Name(_ADR,0x00140005) // Device (HI WORD)=20, Func (LO WORD)=5
Name(_STA,0xF) // Enabled, do Display
Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#
}
Device (ENT0) // Ethernet0 [Bus 0, Device 20, Function 6]
{
Name(_ADR,0x00140006) // Device (HI WORD)=20, Func (LO WORD)=6
Name(_STA,0xF) // Enabled, do Display
Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#
}
Device (ENT1) // Ethernet1 [Bus 0, Device 20, Function 7]
{
Name(_ADR,0x00140007) // Device (HI WORD)=20, Func (LO WORD)=7
Name(_STA,0xF) // Enabled, do Display
Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#
}
Device (SPI0) // SPI0 [Bus 0, Device 21, Function 0]
{
Name(_ADR,0x00150000) // Device (HI WORD)=21, Func (LO WORD)=0
Name(_STA,0xF) // Enabled, do Display
Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#
}
Device (SPI1) // SPI1 [Bus 0, Device 21, Function 1]
{
Name(_ADR,0x00150001) // Device (HI WORD)=21, Func (LO WORD)=1
Name(_STA,0xF) // Enabled, do Display
Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#
}
Device (GIP0) // I2C/GPIO [Bus 0, Device 21, Function 2]
{
Name(_ADR,0x00150002) // Device (HI WORD)=21, Func (LO WORD)=2
Name(_STA,0xF) // Enabled, do Display
Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#
Device(GPO_) // GPIO Virtual Child Device- for BAR0 resources
{
Name(_ADR, 0)
Name(_STA, 0xf)
Name(_PRW, Package(0x2)
{
0xf,
0x3
})
}
Device(I2C_) // I2C Controller Virtual Child Device- for BAR1 resources
{
Name(_ADR, 1)
Name(_STA, 0xf)
Name(_PRW, Package(0x2)
{
0xf,
0x3
})
}
}
#endif

51
QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Tpm.asi Normal file
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/** @file
The Infineon SLB9645 TPM ACPI definition block.
Provides TPM device info. and TPM presence check only.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
Device (TPM)
{
//
// Define _HID as Infineon TPM Device, _CID as "PNP0C31" (defined in
// "Secure Startup-FVE and TPM Admin BIOS and Platform Requirements").
//
Name(_HID ,EISAID("INT3493"))
Name(_CID, EISAID("PNP0C31"))
//
// Readable name of this device.
//
Name (_STR, Unicode ("Infineon TPM 1.2 Device (SLB9645TT1.2)"))
//
// Return the resource consumed by TPM device.
//
Name (_CRS, ResourceTemplate () {
I2cSerialBus (0x20, ControllerInitiated, 0x00061A80, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer,,)
})
//
// Check if TPM present.
//
Method (_STA, 0)
{
if (LEqual (TPMP, 0))
{
return (0)
}
Return (0x0f)
}
}

80
QuarkPlatformPkg/Acpi/AcpiTables/Facs/Facs.aslc Normal file
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/** @file
This file contains the FACS structure definition.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Statements that include other files
//
#include "Facs.h"
EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE FACS = {
EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE,
sizeof (EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE),
//
// Hardware Signature will be updated at runtime
//
0x00000000,
EFI_ACPI_FIRMWARE_WAKING_VECTOR,
EFI_ACPI_GLOBAL_LOCK,
EFI_ACPI_FIRMWARE_CONTROL_STRUCTURE_FLAGS,
EFI_ACPI_X_FIRMWARE_WAKING_VECTOR,
EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION,
{
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE
}
};
VOID*
ReferenceAcpiTable (
VOID
)
{
//
// Reference the table being generated to prevent the optimizer from removing the
// data structure from the exeutable
//
return (VOID*)&FACS;
}

35
QuarkPlatformPkg/Acpi/AcpiTables/Facs/Facs.h Normal file
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/** @file
This file describes the contents of the ACPI Firmware ACPI Control Structure (FACS)
. Some additional ACPI values are defined in Acpi10.h, Acpi20.h, and Acpi30.h
All changes to the FACS contents should be done in this file.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _FACS_H_
#define _FACS_H_
//
// Statements that include other files
//
#include <IndustryStandard/Acpi.h>
//
// FACS Definitions
//
#define EFI_ACPI_FIRMWARE_WAKING_VECTOR 0x00000000
#define EFI_ACPI_GLOBAL_LOCK 0x00000000
#define EFI_ACPI_FIRMWARE_CONTROL_STRUCTURE_FLAGS 0x00000000
#define EFI_ACPI_X_FIRMWARE_WAKING_VECTOR 0x0000000000000000
#endif

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QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.h Normal file
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/** @file
This file describes the contents of the ACPI Fixed ACPI Description Table (FADT)
. Some additional ACPI values are defined in Acpi10.h, Acpi20.h, and Acpi30.h
All changes to the FADT contents should be done in this file.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _FADT_H_
#define _FADT_H_
//
// Statements that include other files
//
#include <IndustryStandard/Acpi.h>
//
// ACPI table information used to initialize tables.
//
#define EFI_ACPI_OEM_ID 'I','N','T','E','L',' ' // OEMID 6 bytes long
#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('T','I','A','N','O',' ',' ',' ') // OEM table id 8 bytes long
#define EFI_ACPI_OEM_REVISION 0x00000004
#define EFI_ACPI_CREATOR_ID SIGNATURE_32('I','N','T','L')
#define EFI_ACPI_CREATOR_REVISION 0x0100000D
//
// FADT Definitions
//
#define PM_PROFILE 0x01
#define INT_MODEL 0x01
#define SCI_INT_VECTOR 0x0009
#define ACPI_ENABLE 0x0a0
#define ACPI_DISABLE 0x0a1
#define S4BIOS_REQ 0x00
#define PM1_EVT_LEN 0x04
#define PM1_CNT_LEN 0x02
#define PM2_CNT_LEN 0x00
#define PM_TM_LEN 0x04
#define GPE0_BLK_LEN 0x08
#define GPE1_BLK_LEN 0x00
#define GPE1_BASE 0x00
#define RESERVED 0x00
#define P_LVL2_LAT 0x0065
#define P_LVL3_LAT 0x03e9
#define FLUSH_SIZE 0x0400
#define FLUSH_STRIDE 0x0010
#define DUTY_OFFSET 0x01
#define DUTY_WIDTH 0x03
#define DAY_ALRM 0x00
#define MON_ALRM 0x00
#define CENTURY 0x00
#define IAPC_BOOT_ARCH EFI_ACPI_2_0_LEGACY_DEVICES
#define FLAG (EFI_ACPI_1_0_WBINVD | EFI_ACPI_1_0_PROC_C1 | EFI_ACPI_1_0_SLP_BUTTON | EFI_ACPI_1_0_RTC_S4)
#define FLAG2 (EFI_ACPI_2_0_WBINVD | EFI_ACPI_2_0_PROC_C1 | EFI_ACPI_2_0_PWR_BUTTON | EFI_ACPI_2_0_SLP_BUTTON | EFI_ACPI_2_0_RTC_S4 | EFI_ACPI_2_0_RESET_REG_SUP | EFI_ACPI_3_0_USE_PLATFORM_CLOCK)
#define RESET_REG_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO
#define RESET_REG_BIT_WIDTH 0x08
#define RESET_REG_BIT_OFFSET 0x00
#define RESET_REG_ADDRESS 0x0000000000000CF9
#define RESET_VALUE 0x02
#define ACPI_RUNTIME_UPDATE 0x00
#define PM1a_EVT_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO
#define PM1a_EVT_BLK_BIT_WIDTH 0x20
#define PM1a_EVT_BLK_BIT_OFFSET 0x00
#define PM1b_EVT_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO
#define PM1b_EVT_BLK_BIT_WIDTH 0x00
#define PM1b_EVT_BLK_BIT_OFFSET 0x00
#define PM1b_EVT_BLK_ADDRESS 0x0000000000000000
#define PM1a_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO
#define PM1a_CNT_BLK_BIT_WIDTH 0x10
#define PM1a_CNT_BLK_BIT_OFFSET 0x00
#define PM1b_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO
#define PM1b_CNT_BLK_BIT_WIDTH 0x00
#define PM1b_CNT_BLK_BIT_OFFSET 0x00
#define PM1b_CNT_BLK_ADDRESS 0x0000000000000000
#define PM2_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO
#define PM2_CNT_BLK_BIT_WIDTH 0x00
#define PM2_CNT_BLK_BIT_OFFSET 0x00
#define PM2_CNT_BLK_ADDRESS 0x0000000000000000
#define PM_TMR_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO
#define PM_TMR_BLK_BIT_WIDTH 0x20
#define PM_TMR_BLK_BIT_OFFSET 0x00
#define GPE0_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO
#define GPE0_BLK_BIT_WIDTH 0x40
#define GPE0_BLK_BIT_OFFSET 0x00
#define GPE1_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO
#define GPE1_BLK_BIT_WIDTH 0x00
#define GPE1_BLK_BIT_OFFSET 0x00
#define GPE1_BLK_ADDRESS 0x0000000000000000
#endif

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/** @file
This file describes the contents of the ACPI Fixed ACPI Description Table
(FADT). Some additional ACPI values are defined in Acpi1_0.h and Acpi2_0.h.
All changes to the FADT contents should be done in this file.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "Fadt.h"
EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE FADT = {
EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
sizeof (EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE),
EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
0, // to make sum of entire table == 0
EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field
EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long)
EFI_ACPI_OEM_REVISION, // OEM revision number
EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID
EFI_ACPI_CREATOR_REVISION, // ASL compiler revision number
0, // Physical addesss of FACS
0, // Physical address of DSDT
INT_MODEL, // System Interrupt Model
RESERVED, // reserved
SCI_INT_VECTOR, // System vector of SCI interrupt
SMI_CMD_IO_PORT, // Port address of SMI command port
ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI
ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI
S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state
RESERVED, // reserved - must be zero
PM1a_EVT_BLK_ADDRESS, // Port address of Power Mgt 1a Event Reg Blk
PM1b_EVT_BLK_ADDRESS, // Port address of Power Mgt 1b Event Reg Blk
PM1a_CNT_BLK_ADDRESS, // Port address of Power Mgt 1a Ctrl Reg Blk
PM1b_CNT_BLK_ADDRESS, // Port address of Power Mgt 1b Ctrl Reg Blk
PM2_CNT_BLK_ADDRESS, // Port address of Power Mgt 2 Ctrl Reg Blk
PM_TMR_BLK_ADDRESS, // Port address of Power Mgt Timer Ctrl Reg Blk
GPE0_BLK_ADDRESS, // Port addr of General Purpose Event 0 Reg Blk
GPE1_BLK_ADDRESS, // Port addr of General Purpose Event 1 Reg Blk
PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk
PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk
PM2_CNT_LEN, // Byte Length of ports at pm2_cnt_blk
PM_TM_LEN, // Byte Length of ports at pm_tm_blk
GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk
GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk
GPE1_BASE, // offset in gpe model where gpe1 events start
RESERVED, // reserved
P_LVL2_LAT, // worst case HW latency to enter/exit C2 state
P_LVL3_LAT, // worst case HW latency to enter/exit C3 state
FLUSH_SIZE, // Size of area read to flush caches
FLUSH_STRIDE, // Stride used in flushing caches
DUTY_OFFSET, // bit location of duty cycle field in p_cnt reg
DUTY_WIDTH, // bit width of duty cycle field in p_cnt reg
DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM
MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM
CENTURY, // index to century in RTC CMOS RAM
RESERVED, // reserved
RESERVED, // reserved
RESERVED, // reserved
FLAG
};
VOID*
ReferenceAcpiTable (
VOID
)
{
//
// Reference the table being generated to prevent the optimizer from removing the
// data structure from the exeutable
//
return (VOID*)&FADT;
}

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/** @file
This file describes the contents of the ACPI Fixed ACPI Description Table
(FADT). Some additional ACPI values are defined in Acpi1_0.h and Acpi2_0.h.
All changes to the FADT contents should be done in this file.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "Fadt.h"
EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE FADT = {
{
EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
sizeof (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE),
EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
0, // to make sum of entire table == 0
{EFI_ACPI_OEM_ID}, // OEMID is a 6 bytes long field
EFI_ACPI_OEM_TABLE_ID,// OEM table identification(8 bytes long)
EFI_ACPI_OEM_REVISION,// OEM revision number
EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID
EFI_ACPI_CREATOR_REVISION // ASL compiler revision number
},
0, // Physical addesss of FACS
0, // Physical address of DSDT
RESERVED, // reserved
PM_PROFILE, // Preferred powermanagement profile
SCI_INT_VECTOR, // System vector of SCI interrupt
ACPI_RUNTIME_UPDATE, // Port address of SMI command port
ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI
ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI
S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state
RESERVED, // reserved - must be zero
ACPI_RUNTIME_UPDATE, // Port address of Power Mgt 1a Event Reg Blk
PM1b_EVT_BLK_ADDRESS, // Port address of Power Mgt 1b Event Reg Blk
ACPI_RUNTIME_UPDATE, // Port address of Power Mgt 1a Ctrl Reg Blk
PM1b_CNT_BLK_ADDRESS, // Port address of Power Mgt 1b Ctrl Reg Blk
ACPI_RUNTIME_UPDATE, // Port address of Power Mgt 2 Ctrl Reg Blk
ACPI_RUNTIME_UPDATE, // Port address of Power Mgt Timer Ctrl Reg Blk
ACPI_RUNTIME_UPDATE, // Port addr of General Purpose Event 0 Reg Blk
GPE1_BLK_ADDRESS, // Port addr of General Purpose Event 1 Reg Blk
PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk
PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk
PM2_CNT_LEN, // Byte Length of ports at pm2_cnt_blk
PM_TM_LEN, // Byte Length of ports at pm_tm_blk
GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk
GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk
GPE1_BASE, // offset in gpe model where gpe1 events start
RESERVED, // reserved
P_LVL2_LAT, // worst case HW latency to enter/exit C2 state
P_LVL3_LAT, // worst case HW latency to enter/exit C3 state
FLUSH_SIZE, // Size of area read to flush caches
FLUSH_STRIDE, // Stride used in flushing caches
DUTY_OFFSET, // bit location of duty cycle field in p_cnt reg
DUTY_WIDTH, // bit width of duty cycle field in p_cnt reg
DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM
MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM
CENTURY, // index to century in RTC CMOS RAM
IAPC_BOOT_ARCH, // IA-PC Boot Architecture Flags
RESERVED, // reserved
FLAG2, // Fixed feature flags
{
RESET_REG_ADDRESS_SPACE_ID, // Address of the reset register
RESET_REG_BIT_WIDTH,
RESET_REG_BIT_OFFSET,
RESERVED,
RESET_REG_ADDRESS
},
RESET_VALUE, // Value to write to the RESET_REG port
{
RESERVED,
RESERVED,
RESERVED
},
0, // 64Bit physical addesss of FACS
0, // 64Bit physical address of DSDT
{
PM1a_EVT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1a Event Reg Blk
PM1a_EVT_BLK_BIT_WIDTH,
PM1a_EVT_BLK_BIT_OFFSET,
RESERVED,
ACPI_RUNTIME_UPDATE
},
{
PM1b_EVT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1b Event Reg Blk
PM1b_EVT_BLK_BIT_WIDTH,
PM1b_EVT_BLK_BIT_OFFSET,
RESERVED,
PM1b_EVT_BLK_ADDRESS
},
{
PM1a_CNT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1a Ctrl Reg Blk
PM1a_CNT_BLK_BIT_WIDTH,
PM1a_CNT_BLK_BIT_OFFSET,
RESERVED,
ACPI_RUNTIME_UPDATE
},
{
PM1b_CNT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1b Ctrl Reg Blk
PM1b_CNT_BLK_BIT_WIDTH,
PM1b_CNT_BLK_BIT_OFFSET,
RESERVED,
PM1b_CNT_BLK_ADDRESS
},
{
PM2_CNT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 2 Ctrl Reg Blk
PM2_CNT_BLK_BIT_WIDTH,
PM2_CNT_BLK_BIT_OFFSET,
RESERVED,
ACPI_RUNTIME_UPDATE
},
{
PM_TMR_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt Timer Ctrl Reg Blk
PM_TMR_BLK_BIT_WIDTH,
PM_TMR_BLK_BIT_OFFSET,
RESERVED,
ACPI_RUNTIME_UPDATE
},
{
GPE0_BLK_ADDRESS_SPACE_ID, // Extended Port address of General Purpose Event 0 Reg Blk
GPE0_BLK_BIT_WIDTH,
GPE0_BLK_BIT_OFFSET,
RESERVED,
ACPI_RUNTIME_UPDATE
},
{
GPE1_BLK_ADDRESS_SPACE_ID, // Extended Port address of General Purpose Event 1 Reg Blk
GPE1_BLK_BIT_WIDTH,
GPE1_BLK_BIT_OFFSET,
RESERVED,
GPE1_BLK_ADDRESS
}
};
VOID*
ReferenceAcpiTable (
VOID
)
{
//
// Reference the table being generated to prevent the optimizer from removing the
// data structure from the exeutable
//
return (VOID*)&FADT;
}

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/** @file
This file contains a structure definition for the ACPI 1.0 High Precision Event Timer
Description Table (HPET). The contents of this file should only be modified
for bug fixes, no porting is required. The table layout is defined in
HighPrecisionEventTimerTable.h and the table contents are defined in Acpi1.0.h and Hpet.h.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Statements that include other files
//
#include "Hpet.h"
//
// High Precision Event Timer Table
// Please modify all values in Hpet.h only.
//
EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER Hpet = {
{
EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE,
sizeof (EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER),
EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_REVISION,
//
// Checksum will be updated at runtime
//
0x00,
//
// It is expected that these values will be updated at runtime
//
{' ', ' ', ' ', ' ', ' ', ' '},
0,
EFI_ACPI_OEM_HPET_REVISION,
0,
0
},
EFI_ACPI_EVENT_TIMER_BLOCK_ID,
{
EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS_SPACE_ID,
EFI_ACPI_EVENT_TIMER_BLOCK_BIT_WIDTH,
EFI_ACPI_EVENT_TIMER_BLOCK_BIT_OFFSET,
EFI_ACPI_EVENT_TIMER_ACCESS_SIZE,
ACPI_RUNTIME_UPDATE
},
EFI_ACPI_HPET_NUMBER,
EFI_ACPI_MIN_CLOCK_TICK,
EFI_ACPI_HPET_ATTRIBUTES
};
VOID*
ReferenceAcpiTable (
VOID
)
{
//
// Reference the table being generated to prevent the optimizer from removing the
// data structure from the exeutable
//
return (VOID*)&Hpet;
}

51
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/** @file
This file describes the contents of the ACPI High Precision Event Timer Description Table
(HPET). Some additional ACPI values are defined in Acpi10.h, Acpi20.h, and Acpi30.h
All changes to the HPET contents should be done in this file.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _HPET_H_
#define _HPET_H_
//
// Statements that include other files
//
#include <IndustryStandard/Acpi.h>
#include <IndustryStandard/HighPrecisionEventTimerTable.h>
//
// HPET Definitions
//
#define EFI_ACPI_OEM_HPET_REVISION 0x00000001
#define EFI_ACPI_EVENT_TIMER_BLOCK_ID 0x8086A201
#define ACPI_RUNTIME_UPDATE 0x00
//
// Event Timer Block Base Address Information
//
#define EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS_SPACE_ID EFI_ACPI_3_0_SYSTEM_MEMORY
#define EFI_ACPI_EVENT_TIMER_BLOCK_BIT_WIDTH 0x00
#define EFI_ACPI_EVENT_TIMER_BLOCK_BIT_OFFSET 0x00
#define EFI_ACPI_EVENT_TIMER_ACCESS_SIZE 0x00
#define EFI_ACPI_HPET_NUMBER 0x00
#define EFI_ACPI_MIN_CLOCK_TICK 0x0080
#define EFI_ACPI_HPET_ATTRIBUTES 0x00
#endif

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/** @file
This file contains a structure definition for the ACPI Memory Mapped Configuration
Address Space table (MCFG). Any changes to the number of entries in the table require
updating the structure count in Mcfg.h and then adding the structure to the
MCFG defined in this file. The table layout is defined in Mcfg.h and the
table contents are defined in the MemoryMappedConfigurationSpaceAccessTable.h.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Statements that include other files
//
#include "Mcfg.h"
//
// Multiple APIC Description Table
//
EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = {
{
EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
sizeof (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE),
EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION,
//
// Checksum will be updated at runtime
//
0x00,
//
// It is expected that these values will be programmed at runtime
//
{' ', ' ', ' ', ' ', ' ', ' '},
0,
EFI_ACPI_OEM_MCFG_REVISION,
0,
0
},
//
// Reserved
//
0x0000000000000000,
//
// MCFG specific fields
//
{
{
0x00000000, // BaseAddress (will be updated at runtime)
0x0000, // PciSegmentGroupNumber
0x00, // StartBusNumber
0x1F, // EndBusNumber
0x00000000 // Reserved
}
}
};
VOID*
ReferenceAcpiTable (
VOID
)
{
//
// Reference the table being generated to prevent the optimizer from removing the
// data structure from the exeutable
//
return (VOID*)&Mcfg;
}

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/** @file
This file describes the contents of the ACPI Memory Mapped Configuration
Space Access Table (MCFG). Some additional ACPI values are defined in Acpi10.h,
Acpi20.h, and Acpi30.h.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _MCFG_H_
#define _MCFG_H_
//
// Statements that include other files
//
#include <IndustryStandard/Acpi.h>
#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
//
// MCFG Definitions
//
#define EFI_ACPI_OEM_MCFG_REVISION 0x00000001
//
// Define the number of allocation structures so that we can build the table structure.
//
#define EFI_ACPI_ALLOCATION_STRUCTURE_COUNT 1
//
// MCFG structure
//
//
// Ensure proper structure formats
//
#pragma pack (1)
//
// MCFG Table structure
//
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT64 Reserved;
#if EFI_ACPI_ALLOCATION_STRUCTURE_COUNT > 0
EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE AllocationStructure[EFI_ACPI_ALLOCATION_STRUCTURE_COUNT];
#endif
} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE;
#pragma pack ()
#endif

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322
QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPciUpdate.h Normal file
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/** @file
Update the _PRT and _PRW method for pci devices
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _ACPI_PCI_UPDATE_H_
#define _ACPI_PCI_UPDATE_H_
//
// Primary OpCode
//
#define AML_ZERO_OP 0x00
#define AML_ONE_OP 0x01
#define AML_ALIAS_OP 0x06
#define AML_NAME_OP 0x08
#define AML_BYTE_PREFIX 0x0a
#define AML_WORD_PREFIX 0x0b
#define AML_DWORD_PREFIX 0x0c
#define AML_STRING_PREFIX 0x0d
#define AML_QWORD_PREFIX 0x0e
#define AML_SCOPE_OP 0x10
#define AML_BUFFER_OP 0x11
#define AML_PACKAGE_OP 0x12
#define AML_VAR_PACKAGE_OP 0x13
#define AML_METHOD_OP 0x14
#define AML_DUAL_NAME_PREFIX 0x2e
#define AML_MULTI_NAME_PREFIX 0x2f
#define AML_NAME_CHAR_A 0x41
#define AML_NAME_CHAR_B 0x42
#define AML_NAME_CHAR_C 0x43
#define AML_NAME_CHAR_D 0x44
#define AML_NAME_CHAR_E 0x45
#define AML_NAME_CHAR_F 0x46
#define AML_NAME_CHAR_G 0x47
#define AML_NAME_CHAR_H 0x48
#define AML_NAME_CHAR_I 0x49
#define AML_NAME_CHAR_J 0x4a
#define AML_NAME_CHAR_K 0x4b
#define AML_NAME_CHAR_L 0x4c
#define AML_NAME_CHAR_M 0x4d
#define AML_NAME_CHAR_N 0x4e
#define AML_NAME_CHAR_O 0x4f
#define AML_NAME_CHAR_P 0x50
#define AML_NAME_CHAR_Q 0x51
#define AML_NAME_CHAR_R 0x52
#define AML_NAME_CHAR_S 0x53
#define AML_NAME_CHAR_T 0x54
#define AML_NAME_CHAR_U 0x55
#define AML_NAME_CHAR_V 0x56
#define AML_NAME_CHAR_W 0x57
#define AML_NAME_CHAR_X 0x58
#define AML_NAME_CHAR_Y 0x59
#define AML_NAME_CHAR_Z 0x5a
#define AML_ROOT_CHAR 0x5c
#define AML_PARENT_PREFIX_CHAR 0x5e
#define AML_NAME_CHAR__ 0x5f
#define AML_LOCAL0 0x60
#define AML_LOCAL1 0x61
#define AML_LOCAL2 0x62
#define AML_LOCAL3 0x63
#define AML_LOCAL4 0x64
#define AML_LOCAL5 0x65
#define AML_LOCAL6 0x66
#define AML_LOCAL7 0x67
#define AML_ARG0 0x68
#define AML_ARG1 0x69
#define AML_ARG2 0x6a
#define AML_ARG3 0x6b
#define AML_ARG4 0x6c
#define AML_ARG5 0x6d
#define AML_ARG6 0x6e
#define AML_STORE_OP 0x70
#define AML_REF_OF_OP 0x71
#define AML_ADD_OP 0x72
#define AML_CONCAT_OP 0x73
#define AML_SUBTRACT_OP 0x74
#define AML_INCREMENT_OP 0x75
#define AML_DECREMENT_OP 0x76
#define AML_MULTIPLY_OP 0x77
#define AML_DIVIDE_OP 0x78
#define AML_SHIFT_LEFT_OP 0x79
#define AML_SHIFT_RIGHT_OP 0x7a
#define AML_AND_OP 0x7b
#define AML_NAND_OP 0x7c
#define AML_OR_OP 0x7d
#define AML_NOR_OP 0x7e
#define AML_XOR_OP 0x7f
#define AML_NOT_OP 0x80
#define AML_FIND_SET_LEFT_BIT_OP 0x81
#define AML_FIND_SET_RIGHT_BIT_OP 0x82
#define AML_DEREF_OF_OP 0x83
#define AML_CONCAT_RES_OP 0x84
#define AML_MOD_OP 0x85
#define AML_NOTIFY_OP 0x86
#define AML_SIZE_OF_OP 0x87
#define AML_INDEX_OP 0x88
#define AML_MATCH_OP 0x89
#define AML_CREATE_DWORD_FIELD_OP 0x8a
#define AML_CREATE_WORD_FIELD_OP 0x8b
#define AML_CREATE_BYTE_FIELD_OP 0x8c
#define AML_CREATE_BIT_FIELD_OP 0x8d
#define AML_OBJECT_TYPE_OP 0x8e
#define AML_CREATE_QWORD_FIELD_OP 0x8f
#define AML_LAND_OP 0x90
#define AML_LOR_OP 0x91
#define AML_LNOT_OP 0x92
#define AML_LEQUAL_OP 0x93
#define AML_LGREATER_OP 0x94
#define AML_LLESS_OP 0x95
#define AML_TO_BUFFER_OP 0x96
#define AML_TO_DEC_STRING_OP 0x97
#define AML_TO_HEX_STRING_OP 0x98
#define AML_TO_INTEGER_OP 0x99
#define AML_TO_STRING_OP 0x9c
#define AML_COPY_OBJECT_OP 0x9d
#define AML_MID_OP 0x9e
#define AML_CONTINUE_OP 0x9f
#define AML_IF_OP 0xa0
#define AML_ELSE_OP 0xa1
#define AML_WHILE_OP 0xa2
#define AML_NOOP_OP 0xa3
#define AML_RETURN_OP 0xa4
#define AML_BREAK_OP 0xa5
#define AML_BREAK_POINT_OP 0xcc
#define AML_ONES_OP 0xff
//
// Extended OpCode
//
#define AML_EXT_OP 0x5b
#define AML_EXT_MUTEX_OP 0x01
#define AML_EXT_EVENT_OP 0x02
#define AML_EXT_COND_REF_OF_OP 0x12
#define AML_EXT_CREATE_FIELD_OP 0x13
#define AML_EXT_LOAD_TABLE_OP 0x1f
#define AML_EXT_LOAD_OP 0x20
#define AML_EXT_STALL_OP 0x21
#define AML_EXT_SLEEP_OP 0x22
#define AML_EXT_ACQUIRE_OP 0x23
#define AML_EXT_SIGNAL_OP 0x24
#define AML_EXT_WAIT_OP 0x25
#define AML_EXT_RESET_OP 0x26
#define AML_EXT_RELEASE_OP 0x27
#define AML_EXT_FROM_BCD_OP 0x28
#define AML_EXT_TO_BCD_OP 0x29
#define AML_EXT_UNLOAD_OP 0x2a
#define AML_EXT_REVISION_OP 0x30
#define AML_EXT_DEBUG_OP 0x31
#define AML_EXT_FATAL_OP 0x32
#define AML_EXT_TIMER_OP 0x33
#define AML_EXT_REGION_OP 0x80
#define AML_EXT_FIELD_OP 0x81
#define AML_EXT_DEVICE_OP 0x82
#define AML_EXT_PROCESSOR_OP 0x83
#define AML_EXT_POWER_RES_OP 0x84
#define AML_EXT_THERMAL_ZONE_OP 0x85
#define AML_EXT_INDEX_FIELD_OP 0x86
#define AML_EXT_BANK_FIELD_OP 0x87
#define AML_EXT_DATA_REGION_OP 0x88
#pragma pack(1)
typedef struct {
UINT32 BridgeAddress;
UINT32 DeviceAddress;
UINT8 INTA[2]; // the first member record the 8259 link, the second member record the io apic irq number
UINT8 INTB[2];
UINT8 INTC[2];
UINT8 INTD[2];
UINT8 GPEPin;
UINT8 SxNum;
} PCI_DEVICE_INFO;
#pragma pack()
#define PCI_DEVICE_INFO_MAX_NUM 50
#define CURRENT_PCI_DEVICE_NUM 13
#define PIRQ_LINKA 1
#define PIRQ_LINKB 2
#define PIRQ_LINKC 3
#define PIRQ_LINKD 4
#define PIRQ_LINKE 5
#define PIRQ_LINKF 6
#define PIRQ_LINKG 7
#define PIRQ_LINKH 8
#define PIRQ_INVALID 0xFF
typedef struct _PCI_DEVICE_SETTING{
UINT8 PciDeviceInfoNumber;
PCI_DEVICE_INFO PciDeviceInfo[PCI_DEVICE_INFO_MAX_NUM];
}PCI_DEVICE_SETTING;
typedef struct _AML_BYTE_ENCODING AML_BYTE_ENCODING;
//
// AML Handle Entry definition.
//
// Signature must be set to EFI_AML_HANDLE_SIGNATURE or EFI_AML_ROOT_HANDLE_SIGNATURE
// Buffer is the ACPI node buffer pointer, the first/second bytes are opcode.
// This buffer should not be freed.
// Size is the total size of this ACPI node buffer.
//
typedef struct {
UINT32 Signature;
UINT8 *Buffer;
UINTN Size;
AML_BYTE_ENCODING *AmlByteEncoding;
BOOLEAN Modified;
} EFI_AML_HANDLE;
typedef UINT32 AML_OP_PARSE_INDEX;
typedef UINT32 AML_OP_PARSE_FORMAT;
typedef UINT32 AML_OP_ATTRIBUTE;
struct _AML_BYTE_ENCODING {
UINT8 OpCode;
UINT8 SubOpCode;
AML_OP_PARSE_INDEX MaxIndex;
AML_OP_PARSE_FORMAT Format[6];
AML_OP_ATTRIBUTE Attribute;
};
//
// Check device info fucntion prototype
//
typedef
BOOLEAN
(* CHECK_HANDLE_INFO) (
IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,
IN EFI_ACPI_HANDLE CheckHandle,
IN VOID *Context
);
extern EFI_ACPI_HANDLE mDsdtHandle;
extern EFI_ACPI_SDT_PROTOCOL *mAcpiSdt;
/**
Init Pci Device Structure
@param mConfigData - Pointer of Pci Device information Structure
**/
VOID
InitPciDeviceInfoStructure (
PCI_DEVICE_SETTING *mConfigData
);
/**
update pci routing information in acpi table based on pcd settings
@param AcpiSdt Pointer to Acpi SDT protocol
@param DsdtHandle ACPI root handle
@param PciDeviceInfo Pointer to PCI_DEVICE_INFO
**/
EFI_STATUS
SdtUpdatePciRouting (
IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,
IN EFI_ACPI_HANDLE DsdtHandle,
IN PCI_DEVICE_INFO *PciDeviceInfo
);
/**
update power resource wake up information in acpi table based on pcd settings
@param AcpiSdt Pointer to Acpi SDT protocol
@param DsdtHandle ACPI root handle
@param PciDeviceInfo Pointer to PCI_DEVICE_INFO
**/
EFI_STATUS
SdtUpdatePowerWake (
IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,
IN EFI_ACPI_HANDLE DsdtHandle,
IN PCI_DEVICE_INFO *PciDeviceInfo
);
/**
Get the root bridge handle by scanning the acpi table
@param AcpiSdt Pointer to Acpi SDT protocol
@param DsdtHandle ACPI root handle
@retval EFI_ACPI_HANDLE the handle of the root bridge
**/
EFI_ACPI_HANDLE
SdtGetRootBridgeHandle (
IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,
IN EFI_ACPI_HANDLE DsdtHandle
);
/**
Check input Pci device info is changed from the default values
@param PciDeviceInfo Pointer to PCI_DEVICE_INFO
@param UpdatePRT Pointer to BOOLEAN
@param UpdatePRW Pointer to BOOLEAN
**/
VOID
SdtCheckPciDeviceInfoChanged (
IN PCI_DEVICE_INFO *PciDeviceInfo,
IN BOOLEAN *UpdatePRT,
IN BOOLEAN *UpdatePRW
);
#endif

815
QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.c Normal file
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@@ -0,0 +1,815 @@
/** @file
ACPI Platform Driver
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Protocol/AcpiTable.h>
#include <IndustryStandard/Pci22.h>
#include "AcpiPlatform.h"
//
// Global Variable
//
EFI_GLOBAL_NVS_AREA_PROTOCOL mGlobalNvsArea;
EFI_ACPI_SDT_PROTOCOL *mAcpiSdt;
EFI_ACPI_HANDLE mDsdtHandle = NULL;
EFI_STATUS
LocateSupportProtocol (
IN EFI_GUID *Protocol,
OUT VOID **Instance,
IN UINT32 Type
)
/*++
Routine Description:
Locate the first instance of a protocol. If the protocol requested is an
FV protocol, then it will return the first FV that contains the ACPI table
storage file.
Arguments:
Protocol The protocol to find.
Instance Return pointer to the first instance of the protocol
Returns:
EFI_SUCCESS The function completed successfully.
EFI_NOT_FOUND The protocol could not be located.
EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol.
--*/
{
EFI_STATUS Status;
EFI_HANDLE *HandleBuffer;
UINTN NumberOfHandles;
EFI_FV_FILETYPE FileType;
UINT32 FvStatus;
EFI_FV_FILE_ATTRIBUTES Attributes;
UINTN Size;
UINTN i;
FvStatus = 0;
//
// Locate protocol.
//
Status = gBS->LocateHandleBuffer (
ByProtocol,
Protocol,
NULL,
&NumberOfHandles,
&HandleBuffer
);
if (EFI_ERROR (Status)) {
//
// Defined errors at this time are not found and out of resources.
//
return Status;
}
//
// Looking for FV with ACPI storage file
//
for (i = 0; i < NumberOfHandles; i++) {
//
// Get the protocol on this handle
// This should not fail because of LocateHandleBuffer
//
Status = gBS->HandleProtocol (
HandleBuffer[i],
Protocol,
Instance
);
ASSERT_EFI_ERROR (Status);
if (!Type) {
//
// Not looking for the FV protocol, so find the first instance of the
// protocol. There should not be any errors because our handle buffer
// should always contain at least one or LocateHandleBuffer would have
// returned not found.
//
break;
}
//
// See if it has the ACPI storage file
//
Status = ((EFI_FIRMWARE_VOLUME2_PROTOCOL*) (*Instance))->ReadFile (*Instance,
(EFI_GUID*)PcdGetPtr (PcdAcpiTableStorageFile),
NULL,
&Size,
&FileType,
&Attributes,
&FvStatus
);
//
// If we found it, then we are done
//
if (Status == EFI_SUCCESS) {
break;
}
}
//
// Our exit status is determined by the success of the previous operations
// If the protocol was found, Instance already points to it.
//
//
// Free any allocated buffers
//
gBS->FreePool (HandleBuffer);
return Status;
}
VOID
DsdtTableUpdate (
IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader,
IN OUT EFI_ACPI_TABLE_VERSION *Version
)
/*++
Routine Description:
Update the DSDT table
Arguments:
Table - The table to be set
Version - Version to publish
Returns:
None
--*/
{
UINT8 *CurrPtr;
UINT8 *DsdtPointer;
UINT32 *Signature;
UINT8 *Operation;
UINT32 *Address;
UINT16 *Size;
//
// Loop through the ASL looking for values that we must fix up.
//
CurrPtr = (UINT8 *) TableHeader;
for (DsdtPointer = CurrPtr;
DsdtPointer <= (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length);
DsdtPointer++
)
{
Signature = (UINT32 *) DsdtPointer;
switch (*Signature) {
//
// MNVS operation region
//
case (SIGNATURE_32 ('M', 'N', 'V', 'S')):
//
// Conditional match. For Region Objects, the Operator will always be the
// byte immediately before the specific name. Therefore, subtract 1 to check
// the Operator.
//
Operation = DsdtPointer - 1;
if (*Operation == AML_OPREGION_OP) {
Address = (UINT32 *) (DsdtPointer + 6);
*Address = (UINT32) (UINTN) mGlobalNvsArea.Area;
Size = (UINT16 *) (DsdtPointer + 11);
*Size = sizeof (EFI_GLOBAL_NVS_AREA);
}
break;
//
// Update processor PBLK register I/O base address
//
case (SIGNATURE_32 ('P', 'R', 'I', 'O')):
//
// Conditional match. Update the following ASL code:
// Processor (CPU0, 0x01, 0x4F495250, 0x06) {}
// The 3rd parameter will be updated to the actual PBLK I/O base address.
// the Operator.
//
Operation = DsdtPointer - 8;
if ((*Operation == AML_EXT_OP) && (*(Operation + 1) == AML_EXT_PROCESSOR_OP)) {
*(UINT32 *)DsdtPointer = PcdGet16(PcdPmbaIoBaseAddress);
}
break;
default:
break;
}
}
}
VOID
ApicTableUpdate (
IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader,
IN OUT EFI_ACPI_TABLE_VERSION *Version
)
/*++
Routine Description:
Update the processors information in the APIC table
Arguments:
Table - The table to be set
Version - Version to publish
Returns:
None
--*/
{
EFI_STATUS Status;
EFI_MP_SERVICES_PROTOCOL *MpService;
UINT8 *CurrPtr;
UINT8 *EndPtr;
UINT8 CurrIoApic;
UINT8 CurrProcessor;
UINTN NumberOfCPUs;
UINTN NumberOfEnabledCPUs;
UINTN BufferSize;
EFI_PROCESSOR_INFORMATION MpContext;
ACPI_APIC_STRUCTURE_PTR *ApicPtr;
CurrIoApic = 0;
CurrProcessor = 0;
//
// Find the MP Protocol. This is an MP platform, so MP protocol must be
// there.
//
Status = gBS->LocateProtocol (
&gEfiMpServiceProtocolGuid,
NULL,
(VOID**)&MpService
);
if (EFI_ERROR (Status)) {
//
// Failed to get MP information, doesn't publish the invalid table
//
*Version = EFI_ACPI_TABLE_VERSION_NONE;
return;
}
//
// Determine the number of processors
//
MpService->GetNumberOfProcessors (
MpService,
&NumberOfCPUs,
&NumberOfEnabledCPUs
);
CurrPtr = (UINT8*) &(TableHeader[1]);
CurrPtr = CurrPtr + 8; // Size of Local APIC Address & Flag
EndPtr = (UINT8*) TableHeader;
EndPtr = EndPtr + TableHeader->Length;
while (CurrPtr < EndPtr) {
ApicPtr = (ACPI_APIC_STRUCTURE_PTR*) CurrPtr;
switch (ApicPtr->AcpiApicCommon.Type) {
case EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC:
BufferSize = sizeof (EFI_PROCESSOR_INFORMATION);
ApicPtr->AcpiLocalApic.Flags = 0;
ApicPtr->AcpiLocalApic.ApicId = 0;
Status = MpService->GetProcessorInfo (
MpService,
CurrProcessor,
&MpContext
);
if (!EFI_ERROR (Status)) {
if (MpContext.StatusFlag & PROCESSOR_ENABLED_BIT) {
ApicPtr->AcpiLocalApic.Flags = EFI_ACPI_3_0_LOCAL_APIC_ENABLED;
}
ApicPtr->AcpiLocalApic.ApicId = (UINT8)MpContext.ProcessorId;
}
CurrProcessor++;
break;
case EFI_ACPI_1_0_IO_APIC:
//
// IO APIC entries can be patched here
//
if (CurrIoApic == 0) {
//
// Update SOC internel IOAPIC base
//
ApicPtr->AcpiIoApic.IoApicId = PcdGet8 (PcdIoApicSettingIoApicId);
ApicPtr->AcpiIoApic.IoApicAddress = (UINT32)PcdGet64(PcdIoApicBaseAddress);
ApicPtr->AcpiIoApic.GlobalSystemInterruptBase = 0;
} else {
//
// Porting is required to update other IOAPIC entries if available
//
ASSERT (0);
}
CurrIoApic++;
break;
default:
break;
};
CurrPtr = CurrPtr + ApicPtr->AcpiApicCommon.Length;
}
}
VOID
AcpiUpdateTable (
IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader,
IN OUT EFI_ACPI_TABLE_VERSION *Version
)
/*++
Routine Description:
Set the correct table revision upon the setup value
Arguments:
Table - The table to be set
Version - Version to publish
Returns:
None
--*/
{
EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE *FadtHeader1;
EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *FadtHeader2;
EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *FadtHeader3;
EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE *AllocationStructurePtr;
if (TableHeader != NULL && Version != NULL) {
*Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0;
//
// Here we use all 3.0 signature because all version use same signature if they supported
//
switch (TableHeader->Signature) {
//
// "APIC" Multiple APIC Description Table
//
case EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE:
ApicTableUpdate (TableHeader, Version);
break;
//
// "DSDT" Differentiated System Description Table
//
case EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:
DsdtTableUpdate (TableHeader, Version);
break;
//
// "FACP" Fixed ACPI Description Table (FADT)
//
case EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE:
*Version = EFI_ACPI_TABLE_VERSION_NONE;
if (TableHeader->Revision == EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
*Version = EFI_ACPI_TABLE_VERSION_1_0B;
FadtHeader1 = (EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE *) TableHeader;
FadtHeader1->SmiCmd = PcdGet16(PcdSmmActivationPort);
FadtHeader1->Pm1aEvtBlk = PcdGet16(PcdPm1blkIoBaseAddress);
FadtHeader1->Pm1aCntBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C;
FadtHeader1->PmTmrBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1T;
FadtHeader1->Gpe0Blk = PcdGet16(PcdGpe0blkIoBaseAddress);
} else if (TableHeader->Revision == EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
*Version = EFI_ACPI_TABLE_VERSION_2_0;
FadtHeader2 = (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *) TableHeader;
FadtHeader2->SmiCmd = PcdGet16(PcdSmmActivationPort);
FadtHeader2->Pm1aEvtBlk = PcdGet16(PcdPm1blkIoBaseAddress);
FadtHeader2->Pm1aCntBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C;
FadtHeader2->PmTmrBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1T;
FadtHeader2->Gpe0Blk = PcdGet16(PcdGpe0blkIoBaseAddress);
FadtHeader2->XPm1aEvtBlk.Address = FadtHeader2->Pm1aEvtBlk;
FadtHeader2->XPm1aCntBlk.Address = FadtHeader2->Pm1aCntBlk;
FadtHeader2->XPmTmrBlk.Address = FadtHeader2->PmTmrBlk;
FadtHeader2->XGpe0Blk.Address = FadtHeader2->Gpe0Blk;
} else if (TableHeader->Revision == EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
*Version = EFI_ACPI_TABLE_VERSION_3_0;
FadtHeader3 = (EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *) TableHeader;
FadtHeader3->SmiCmd = PcdGet16(PcdSmmActivationPort);
FadtHeader3->Pm1aEvtBlk = PcdGet16(PcdPm1blkIoBaseAddress);
FadtHeader3->Pm1aCntBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C;
FadtHeader3->PmTmrBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1T;
FadtHeader3->Gpe0Blk = PcdGet16(PcdGpe0blkIoBaseAddress);
FadtHeader3->XPm1aEvtBlk.Address = FadtHeader3->Pm1aEvtBlk;
FadtHeader3->XPm1aCntBlk.Address = FadtHeader3->Pm1aCntBlk;
FadtHeader3->XPmTmrBlk.Address = FadtHeader3->PmTmrBlk;
FadtHeader3->XGpe0Blk.Address = FadtHeader3->Gpe0Blk;
}
break;
//
// "FACS" Firmware ACPI Control Structure
//
case EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE:
break;
//
// "SSDT" Secondary System Description Table
//
case EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:
break;
//
// "HPET" IA-PC High Precision Event Timer Table
//
case EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE:
//
// If HPET is disabled in setup, don't publish the table.
//
if (mGlobalNvsArea.Area->HpetEnable == 0) {
*Version = EFI_ACPI_TABLE_VERSION_NONE;
}
((EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER *) TableHeader)->BaseAddressLower32Bit.Address
= PcdGet64 (PcdHpetBaseAddress);
break;
//
// "SPCR" Serial Port Concole Redirection Table
//
case EFI_ACPI_3_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE:
break;
//
// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
//
case EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE:
AllocationStructurePtr = (EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE *)
((UINT8 *)TableHeader + sizeof(EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER));
AllocationStructurePtr->BaseAddress = PcdGet64(PcdPciExpressBaseAddress);
break;
// Lakeport platform doesn't support the following table
/*
//
// "ECDT" Embedded Controller Boot Resources Table
//
case EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE:
break;
//
// "PSDT" Persistent System Description Table
//
case EFI_ACPI_3_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:
break;
//
// "SBST" Smart Battery Specification Table
//
case EFI_ACPI_3_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE:
break;
//
// "SLIT" System Locality Information Table
//
case EFI_ACPI_3_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE:
break;
//
// "SRAT" Static Resource Affinity Table
//
case EFI_ACPI_3_0_STATIC_RESOURCE_AFFINITY_TABLE_SIGNATURE:
break;
//
// "XSDT" Extended System Description Table
//
case EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:
break;
//
// "BOOT" MS Simple Boot Spec
//
case EFI_ACPI_3_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE:
break;
//
// "CPEP" Corrected Platform Error Polling Table
//
case EFI_ACPI_3_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE:
break;
//
// "DBGP" MS Debug Port Spec
//
case EFI_ACPI_3_0_DEBUG_PORT_TABLE_SIGNATURE:
break;
//
// "ETDT" Event Timer Description Table
//
case EFI_ACPI_3_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE:
break;
//
// "SPMI" Server Platform Management Interface Table
//
case EFI_ACPI_3_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE:
break;
//
// "TCPA" Trusted Computing Platform Alliance Capabilities Table
//
case EFI_ACPI_3_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE:
break;
*/
default:
break;
}
}
}
//
// Description:
// Entrypoint of Acpi Platform driver
// In:
// ImageHandle
// SystemTable
// Out:
// EFI_SUCCESS
// EFI_LOAD_ERROR
// EFI_OUT_OF_RESOURCES
//
EFI_STATUS
AcpiPlatformEntryPoint (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
INTN Instance;
EFI_ACPI_COMMON_HEADER *CurrentTable;
UINTN TableHandle;
UINT32 FvStatus;
UINTN Size;
EFI_ACPI_TABLE_VERSION Version;
QNC_DEVICE_ENABLES QNCDeviceEnables;
EFI_HANDLE Handle;
UINTN Index;
PCI_DEVICE_INFO *PciDeviceInfo;
EFI_ACPI_HANDLE PciRootHandle;
BOOLEAN UpdatePRT;
BOOLEAN UpdatePRW;
PCI_DEVICE_SETTING *mConfigData;
DEBUG((DEBUG_INFO, "ACPI Platform start...\n"));
Instance = 0;
TableHandle = 0;
CurrentTable = NULL;
mConfigData = NULL;
QNCDeviceEnables.Uint32 = PcdGet32 (PcdDeviceEnables);
//
// Initialize the EFI Driver Library
//
ASSERT (sizeof (EFI_GLOBAL_NVS_AREA) == 512);
Status = gBS->AllocatePool (
EfiACPIMemoryNVS,
sizeof (EFI_GLOBAL_NVS_AREA),
(VOID**)&mGlobalNvsArea.Area
);
Handle = NULL;
Status = gBS->InstallProtocolInterface (
&Handle,
&gEfiGlobalNvsAreaProtocolGuid,
EFI_NATIVE_INTERFACE,
&mGlobalNvsArea
);
ASSERT_EFI_ERROR (Status);
if (!EFI_ERROR (Status)) {
SetMem (
mGlobalNvsArea.Area,
sizeof (EFI_GLOBAL_NVS_AREA),
0
);
}
//
// Initialize the data. Eventually, this will be controlled by setup options.
//
mGlobalNvsArea.Area->HpetEnable = PcdGetBool (PcdHpetEnable);
mGlobalNvsArea.Area->Pm1blkIoBaseAddress = PcdGet16(PcdPm1blkIoBaseAddress);
mGlobalNvsArea.Area->PmbaIoBaseAddress = PcdGet16(PcdPmbaIoBaseAddress);
mGlobalNvsArea.Area->Gpe0blkIoBaseAddress = PcdGet16(PcdGpe0blkIoBaseAddress);
mGlobalNvsArea.Area->GbaIoBaseAddress = PcdGet16(PcdGbaIoBaseAddress);
mGlobalNvsArea.Area->SmbaIoBaseAddress = PcdGet16(PcdSmbaIoBaseAddress);
mGlobalNvsArea.Area->WdtbaIoBaseAddress = PcdGet16(PcdWdtbaIoBaseAddress);
mGlobalNvsArea.Area->HpetBaseAddress = (UINT32)PcdGet64(PcdHpetBaseAddress);
mGlobalNvsArea.Area->HpetSize = (UINT32)PcdGet64(PcdHpetSize);
mGlobalNvsArea.Area->PciExpressBaseAddress= (UINT32)PcdGet64(PcdPciExpressBaseAddress);
mGlobalNvsArea.Area->PciExpressSize = (UINT32)PcdGet64(PcdPciExpressSize);
mGlobalNvsArea.Area->RcbaMmioBaseAddress = (UINT32)PcdGet64(PcdRcbaMmioBaseAddress);
mGlobalNvsArea.Area->RcbaMmioSize = (UINT32)PcdGet64(PcdRcbaMmioSize);
mGlobalNvsArea.Area->IoApicBaseAddress = (UINT32)PcdGet64(PcdIoApicBaseAddress);
mGlobalNvsArea.Area->IoApicSize = (UINT32)PcdGet64(PcdIoApicSize);
mGlobalNvsArea.Area->TpmPresent = (UINT32)(FALSE);
mGlobalNvsArea.Area->DBG2Present = (UINT32)(FALSE);
mGlobalNvsArea.Area->PlatformType = (UINT32)PcdGet16 (PcdPlatformType);
//
// Configure platform IO expander I2C Slave Address.
//
if (mGlobalNvsArea.Area->PlatformType == Galileo) {
if (PlatformLegacyGpioGetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO)) {
mGlobalNvsArea.Area->AlternateSla = FALSE;
} else {
mGlobalNvsArea.Area->AlternateSla = TRUE;
}
}
//
// Find the AcpiTable protocol
//
Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID**)&AcpiTable);
if (EFI_ERROR (Status)) {
return EFI_ABORTED;
}
//
// Initialize MADT table
//
Status = MadtTableInitialize (&CurrentTable, &Size);
ASSERT_EFI_ERROR (Status);
//
// Perform any table specific updates.
//
AcpiUpdateTable ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable, &Version);
//
// Update the check sum
// It needs to be zeroed before the checksum calculation
//
((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum = 0;
((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum =
CalculateCheckSum8 ((VOID *)CurrentTable, CurrentTable->Length);
//
// Add the table
//
TableHandle = 0;
Status = AcpiTable->InstallAcpiTable (
AcpiTable,
CurrentTable,
CurrentTable->Length,
&TableHandle
);
ASSERT_EFI_ERROR (Status);
CurrentTable = NULL;
//
// Init Pci Device PRT PRW information structure from PCD
//
mConfigData = (PCI_DEVICE_SETTING *)AllocateZeroPool (sizeof (PCI_DEVICE_SETTING));
ASSERT_EFI_ERROR (mConfigData);
InitPciDeviceInfoStructure (mConfigData);
//
// Get the Acpi SDT protocol for manipulation on acpi table
//
Status = gBS->LocateProtocol (&gEfiAcpiSdtProtocolGuid, NULL, (VOID **)&mAcpiSdt);
ASSERT_EFI_ERROR (Status);
//
// Locate the firmware volume protocol
//
Status = LocateSupportProtocol (&gEfiFirmwareVolume2ProtocolGuid, (VOID**)&FwVol, 1);
if (EFI_ERROR (Status)) {
return EFI_ABORTED;
}
//
// Read tables from the storage file.
//
while (Status == EFI_SUCCESS) {
Status = FwVol->ReadSection (
FwVol,
(EFI_GUID*)PcdGetPtr (PcdAcpiTableStorageFile),
EFI_SECTION_RAW,
Instance,
(VOID**)&CurrentTable,
&Size,
&FvStatus
);
if (!EFI_ERROR(Status)) {
//
// Perform any table specific updates.
//
AcpiUpdateTable ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable, &Version);
//
// Update the check sum
// It needs to be zeroed before the checksum calculation
//
((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum = 0;
((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum =
CalculateCheckSum8 ((VOID *)CurrentTable, CurrentTable->Length);
//
// Add the table
//
TableHandle = 0;
Status = AcpiTable->InstallAcpiTable (
AcpiTable,
CurrentTable,
((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable)->Length,
&TableHandle
);
if (EFI_ERROR(Status)) {
return EFI_ABORTED;
}
//
// If this table is the DSDT table, then update the _PRT and _PRW based on
// the settings from pcds
//
if (CurrentTable->Signature == EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) {
//
// Create the root handle for DSDT table
//
Status = mAcpiSdt->OpenSdt (TableHandle, &mDsdtHandle);
ASSERT_EFI_ERROR (Status);
PciRootHandle = NULL;
PciRootHandle = SdtGetRootBridgeHandle (mAcpiSdt, mDsdtHandle);
ASSERT (PciRootHandle != NULL);
PciDeviceInfo = NULL;
for (Index = 0; Index < mConfigData->PciDeviceInfoNumber; Index++) {
PciDeviceInfo = &(mConfigData->PciDeviceInfo[Index]);
//
// Check whether this is a valid item
//
if ((PciDeviceInfo->BridgeAddress != 0xFFFFFFFF) && (PciDeviceInfo->DeviceAddress != 0xFFFFFFFF)) {
//DEBUG ((EFI_D_ERROR, "Valid pci info structure: bridge address:0x%x, device address:0x%x\n", PciDeviceInfo->BridgeAddress, PciDeviceInfo->DeviceAddress));
UpdatePRT = FALSE;
UpdatePRW = FALSE;
SdtCheckPciDeviceInfoChanged (PciDeviceInfo, &UpdatePRT, &UpdatePRW);
//
// Check whether there is any valid pci routing item
//
if (UpdatePRT) {
//
// Update the pci routing information
//
//DEBUG ((EFI_D_ERROR, "Update _PRT\n"));
SdtUpdatePciRouting (mAcpiSdt, PciRootHandle, PciDeviceInfo);
}
//
// Check whether there is any valid pci routing item
//
if (UpdatePRW) {
//
// Update the pci wakeup information
//
//DEBUG ((EFI_D_ERROR, "Update _PRW\n"));
SdtUpdatePowerWake (mAcpiSdt, PciRootHandle, PciDeviceInfo);
}
}
}
Status = mAcpiSdt->Close (PciRootHandle);
ASSERT_EFI_ERROR (Status);
//
// Mark the root handle as modified , let SDT protocol recaculate the checksum
//
((EFI_AML_HANDLE *)mDsdtHandle)->Modified = TRUE;
Status = mAcpiSdt->Close (mDsdtHandle);
ASSERT_EFI_ERROR (Status);
}
//
// Increment the instance
//
Instance++;
CurrentTable = NULL;
}
}
gBS->FreePool (mConfigData);
return EFI_SUCCESS;
}

126
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/** @file
This is an implementation of the ACPI platform driver. Requirements for
this driver are defined in the Tiano ACPI External Product Specification,
revision 0.3.6.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _ACPI_PLATFORM_H_
#define _ACPI_PLATFORM_H_
//
// Statements that include other header files
//
#include <PiDxe.h>
#include <IntelQNCDxe.h>
#include <Platform.h>
#include <PlatformBoards.h>
#include <Ioh.h>
#include <QNCCommonDefinitions.h>
#include <Protocol/GlobalNvsArea.h>
#include <Protocol/MpService.h>
#include <Protocol/AcpiSystemDescriptionTable.h>
#include <Protocol/FirmwareVolume2.h>
#include <Library/UefiDriverEntryPoint.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/UefiLib.h>
#include <Library/DxeServicesLib.h>
#include <Library/DevicePathLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/QNCAccessLib.h>
#include <Library/PlatformHelperLib.h>
#include <IndustryStandard/Acpi.h>
#include <IndustryStandard/HighPrecisionEventTimerTable.h>
#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
#include "Madt.h"
#include "AcpiPciUpdate.h"
#pragma pack(1)
typedef struct {
UINT8 StartByte;
UINT32 NameStr;
UINT8 OpCode;
UINT16 Size; // Hardcode to 16bit width because the table we use is fixed size
UINT8 NumEntries;
} EFI_ACPI_NAME_COMMAND;
typedef struct {
UINT8 PackageOp;
UINT8 PkgLeadByte;
UINT8 NumEntries;
UINT8 DwordPrefix0;
UINT32 CoreFreq;
UINT8 DwordPrefix1;
UINT32 Power;
UINT8 DwordPrefix2;
UINT32 TransLatency;
UINT8 DwordPrefix3;
UINT32 BMLatency;
UINT8 DwordPrefix4;
UINT32 Control;
UINT8 DwordPrefix5;
UINT32 Status;
} EFI_PSS_PACKAGE;
#pragma pack()
#define AML_NAME_OP 0x08
#define AML_METHOD_OP 0x14
#define AML_OPREGION_OP 0x80
#define AML_PACKAGE_OP 0x12 // Package operator.
//
// ACPI table information used to initialize tables.
//
#define EFI_ACPI_OEM_ID "INTEL "
#define EFI_ACPI_OEM_TABLE_ID 0x2020204F4E414954ULL // "TIANO "
#define EFI_ACPI_OEM_REVISION 0x00000002
#define EFI_ACPI_CREATOR_ID 0x5446534D // "MSFT"
#define EFI_ACPI_CREATOR_REVISION 0x01000013
#define ACPI_COMPATIBLE_1_0 0
#define ACPI_COMPATIBLE_2_0 1
#define ACPI_COMPATIBLE_3_0 2
//
// Private Driver Data
//
//
// Define Union of IO APIC & Local APIC structure;
//
typedef union {
EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE AcpiLocalApic;
EFI_ACPI_2_0_IO_APIC_STRUCTURE AcpiIoApic;
struct {
UINT8 Type;
UINT8 Length;
} AcpiApicCommon;
} ACPI_APIC_STRUCTURE_PTR;
#endif

202
QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.inf Normal file
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@@ -0,0 +1,202 @@
## @file
# Component description file for AcpiPlatform module.
#
# This is an implementation of the ACPI platform driver,
# whose requirements are from ACPI External Product Specification.
# Copyright (c) 2013-2015 Intel Corporation.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = AcpiPlatform
FILE_GUID = 368B3649-F204-4cd0-89A8-091077C070FA
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = AcpiPlatformEntryPoint
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
#
[Sources]
AcpiPlatform.c
AcpiPlatform.h
MadtPlatform.c
Madt.h
AcpiPciUpdate.c
AcpiPciUpdate.h
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
UefiCpuPkg/UefiCpuPkg.dec
QuarkSocPkg/QuarkSocPkg.dec
QuarkPlatformPkg/QuarkPlatformPkg.dec
[LibraryClasses]
UefiLib
DxeServicesLib
PcdLib
IoLib
BaseMemoryLib
DebugLib
UefiRuntimeServicesTableLib
UefiBootServicesTableLib
UefiDriverEntryPoint
DevicePathLib
PlatformHelperLib
[Protocols]
gEfiGlobalNvsAreaProtocolGuid # PROTOCOL ALWAYS_CONSUMED
gEfiMpServiceProtocolGuid # PROTOCOL SOMETIMES_CONSUMED
gEfiAcpiSdtProtocolGuid # PROTOCOL ALWAYS_CONSUMED
gEfiAcpiTableProtocolGuid # PROTOCOL ALWAYS_CONSUMED
[Pcd]
gQuarkPlatformTokenSpaceGuid.PcdPlatformType
gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15GlobalIrq
gEfiQuarkNcSocIdTokenSpaceGuid.PcdIoApicBaseAddress
gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingIoApicAddress
gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingGlobalInterruptBase
gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingIoApicId
gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingNmiEnable
gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingNmiSource
gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingPolarity
gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingTrigerMode
gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingNmiEnabelApicIdMask
gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingAddressOverrideEnable
gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingPolarity
gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingTrigerMode
gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingLocalApicLint
gQuarkPlatformTokenSpaceGuid.PcdLocalApicAddressOverride
gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmmActivationPort
gEfiQuarkNcSocIdTokenSpaceGuid.PcdPm1blkIoBaseAddress
gEfiQuarkNcSocIdTokenSpaceGuid.PcdGpe0blkIoBaseAddress
gEfiQuarkNcSocIdTokenSpaceGuid.PcdPmbaIoBaseAddress
gEfiQuarkNcSocIdTokenSpaceGuid.PcdGbaIoBaseAddress
gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmbaIoBaseAddress
gEfiQuarkNcSocIdTokenSpaceGuid.PcdHpetBaseAddress
gEfiQuarkNcSocIdTokenSpaceGuid.PcdHpetSize
gEfiQuarkNcSocIdTokenSpaceGuid.PcdIoApicBaseAddress
gEfiQuarkNcSocIdTokenSpaceGuid.PcdIoApicSize
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciExpressSize
gEfiQuarkNcSocIdTokenSpaceGuid.PcdRcbaMmioBaseAddress
gEfiQuarkNcSocIdTokenSpaceGuid.PcdRcbaMmioSize
gEfiQuarkNcSocIdTokenSpaceGuid.PcdWdtbaIoBaseAddress
gQuarkPlatformTokenSpaceGuid.PcdHpetEnable
gEfiQuarkNcSocIdTokenSpaceGuid.PcdDeviceEnables
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile
[Depex]
gEfiMpServiceProtocolGuid AND gEfiAcpiTableProtocolGuid

213
QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/Madt.h Normal file
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/** @file
This file describes the contents of the ACPI Multiple APIC Description
Table (MADT). Some additional ACPI values are defined in Acpi10.h and
Acpi20.h.
To make changes to the MADT, it is necessary to update the count for the
APIC structure being updated, and to modify table found in Madt.c.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _MADT_H
#define _MADT_H
//
// Statements that include other files
//
#include <IndustryStandard/Acpi.h>
#include <Library/PcdLib.h>
//
// MADT Definitions
//
#define EFI_ACPI_OEM_MADT_REVISION 0x00000001
//
// Local APIC address
//
#define EFI_ACPI_LOCAL_APIC_ADDRESS 0xFEE00000
//
// Multiple APIC Flags are defined in AcpiX.0.h
//
#define EFI_ACPI_1_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_1_0_PCAT_COMPAT)
#define EFI_ACPI_2_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_2_0_PCAT_COMPAT)
//
// Define the number of each table type.
// This is where the table layout is modified.
//
#define EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT 2
#define EFI_ACPI_IO_APIC_COUNT 1
#define EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT 2
#define EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT 0
#define EFI_ACPI_LOCAL_APIC_NMI_COUNT 2
#define EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT 0
#define EFI_ACPI_IO_SAPIC_COUNT 0
#define EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT 0
#define EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT 0
#define EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT_MAX 16
//
// MADT structure
//
//
// Ensure proper structure formats
//
#pragma pack (1)
//
// ACPI 1.0 Table structure
//
typedef struct {
EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0
EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT];
#endif
#if EFI_ACPI_IO_APIC_COUNT > 0
EFI_ACPI_1_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT];
#endif
#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0
EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];
#endif
#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0
EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT];
#endif
#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0
EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT];
#endif
#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0
EFI_ACPI_1_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_OVERRIDE_COUNT];
#endif
} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
//
// ACPI 2.0 Table structure
//
typedef struct {
EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0
EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT];
#endif
#if EFI_ACPI_IO_APIC_COUNT > 0
EFI_ACPI_2_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT];
#endif
#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0
EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];
#endif
#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0
EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT];
#endif
#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0
EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT];
#endif
#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0
EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT];
#endif
#if EFI_ACPI_IO_SAPIC_COUNT > 0
EFI_ACPI_2_0_IO_SAPIC_STRUCTURE IoSapic[EFI_ACPI_IO_SAPIC_COUNT];
#endif
#if EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT > 0
EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE LocalSapic[EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT];
#endif
#if EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT > 0
EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE PlatformInterruptSources[EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT];
#endif
} EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
#define _PcdIntSettingTblEnable(x) PcdGet8 (PcdInterruptOverrideSettingTable##x##Enable)
#define PcdIntSettingTblEnable(x) _PcdIntSettingTblEnable(x)
#define _PcdIntSettingTblSourceIrq(x) PcdGet8 (PcdInterruptOverrideSettingTable##x##Enable)
#define PcdIntSettingTblSourceIrq(x) _PcdIntSettingTblSourceIrq(x)
#define _PcdIntSettingTblPolarity(x) PcdGet8 (PcdInterruptOverrideSettingTable##x##Polarity)
#define PcdIntSettingTblPolarity(x) _PcdIntSettingTblPolarity(x)
#define _PcdIntSettingTableTrigerMode(x) PcdGet8 (PcdInterruptOverrideSettingTable##x##TrigerMode)
#define PcdIntSettingTableTrigerMode(x) _PcdIntSettingTableTrigerMode(x)
#define _PcdIntSettingTableGlobalIrq(x) PcdGet32 (PcdInterruptOverrideSettingTable##x##GlobalIrq)
#define PcdIntSettingTableGlobalIrq(x) _PcdIntSettingTableGlobalIrq(x)
typedef struct {
UINT8 Enable;
UINT8 SourceIrq;
UINT8 Polarity;
UINT8 TrigerMode;
UINT32 GlobalIrq;
} INTERRUPT_OVERRIDE_SETTING;
typedef struct {
UINT32 IoApicAddress;
UINT32 GlobalInterruptBase;
UINT8 IoApicId;
UINT8 NmiEnable;
UINT8 NmiSource;
UINT8 Polarity;
UINT8 TrigerMode;
} IO_APIC_SETTING;
typedef struct {
UINT8 NmiEnabelApicIdMask;
UINT8 AddressOverrideEnable;
UINT8 Polarity;
UINT8 TrigerMode;
UINT8 LocalApicLint;
UINT8 Reserve[3];
UINT32 LocalApicAddress;
UINT64 LocalApicAddressOverride;
} LOCAL_APIC_SETTING;
typedef struct _MADT_CONFIG_DATA {
INTERRUPT_OVERRIDE_SETTING MadtInterruptSetting[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT_MAX];
IO_APIC_SETTING MadtIoApicSetting;
LOCAL_APIC_SETTING MadtLocalApicSetting;
}MADT_CONFIG_DATA;
#pragma pack ()
EFI_STATUS
EFIAPI
MadtTableInitialize (
OUT EFI_ACPI_COMMON_HEADER **MadtTable,
OUT UINTN *Size
);
#endif

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/** @file
This file contains Madt Talbe initialized work.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Statements that include other files
//
#include "AcpiPlatform.h"
VOID
InitMadtConfigData (MADT_CONFIG_DATA *mConfigData)
{
mConfigData->MadtInterruptSetting[0].Enable = PcdGet8 (PcdInterruptOverrideSettingTable0Enable);
mConfigData->MadtInterruptSetting[0].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable0SourceIrq);
mConfigData->MadtInterruptSetting[0].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable0Polarity);
mConfigData->MadtInterruptSetting[0].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable0TrigerMode);
mConfigData->MadtInterruptSetting[0].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable0GlobalIrq);
mConfigData->MadtInterruptSetting[1].Enable = PcdGet8 (PcdInterruptOverrideSettingTable1Enable);
mConfigData->MadtInterruptSetting[1].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable1SourceIrq);
mConfigData->MadtInterruptSetting[1].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable1Polarity);
mConfigData->MadtInterruptSetting[1].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable1TrigerMode);
mConfigData->MadtInterruptSetting[1].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable1GlobalIrq);
mConfigData->MadtInterruptSetting[2].Enable = PcdGet8 (PcdInterruptOverrideSettingTable2Enable);
mConfigData->MadtInterruptSetting[2].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable2SourceIrq);
mConfigData->MadtInterruptSetting[2].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable2Polarity);
mConfigData->MadtInterruptSetting[2].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable2TrigerMode);
mConfigData->MadtInterruptSetting[2].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable2GlobalIrq);
mConfigData->MadtInterruptSetting[3].Enable = PcdGet8 (PcdInterruptOverrideSettingTable3Enable);
mConfigData->MadtInterruptSetting[3].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable3SourceIrq);
mConfigData->MadtInterruptSetting[3].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable3Polarity);
mConfigData->MadtInterruptSetting[3].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable3TrigerMode);
mConfigData->MadtInterruptSetting[3].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable3GlobalIrq);
mConfigData->MadtInterruptSetting[4].Enable = PcdGet8 (PcdInterruptOverrideSettingTable4Enable);
mConfigData->MadtInterruptSetting[4].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable4SourceIrq);
mConfigData->MadtInterruptSetting[4].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable4Polarity);
mConfigData->MadtInterruptSetting[4].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable4TrigerMode);
mConfigData->MadtInterruptSetting[4].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable4GlobalIrq);
mConfigData->MadtInterruptSetting[5].Enable = PcdGet8 (PcdInterruptOverrideSettingTable5Enable);
mConfigData->MadtInterruptSetting[5].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable5SourceIrq);
mConfigData->MadtInterruptSetting[5].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable5Polarity);
mConfigData->MadtInterruptSetting[5].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable5TrigerMode);
mConfigData->MadtInterruptSetting[5].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable5GlobalIrq);
mConfigData->MadtInterruptSetting[6].Enable = PcdGet8 (PcdInterruptOverrideSettingTable6Enable);
mConfigData->MadtInterruptSetting[6].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable6SourceIrq);
mConfigData->MadtInterruptSetting[6].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable6Polarity);
mConfigData->MadtInterruptSetting[6].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable6TrigerMode);
mConfigData->MadtInterruptSetting[6].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable6GlobalIrq);
mConfigData->MadtInterruptSetting[7].Enable = PcdGet8 (PcdInterruptOverrideSettingTable7Enable);
mConfigData->MadtInterruptSetting[7].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable7SourceIrq);
mConfigData->MadtInterruptSetting[7].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable7Polarity);
mConfigData->MadtInterruptSetting[7].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable7TrigerMode);
mConfigData->MadtInterruptSetting[7].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable7GlobalIrq);
mConfigData->MadtInterruptSetting[8].Enable = PcdGet8 (PcdInterruptOverrideSettingTable8Enable);
mConfigData->MadtInterruptSetting[8].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable8SourceIrq);
mConfigData->MadtInterruptSetting[8].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable8Polarity);
mConfigData->MadtInterruptSetting[8].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable8TrigerMode);
mConfigData->MadtInterruptSetting[8].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable8GlobalIrq);
mConfigData->MadtInterruptSetting[9].Enable = PcdGet8 (PcdInterruptOverrideSettingTable9Enable);
mConfigData->MadtInterruptSetting[9].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable9SourceIrq);
mConfigData->MadtInterruptSetting[9].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable9Polarity);
mConfigData->MadtInterruptSetting[9].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable9TrigerMode);
mConfigData->MadtInterruptSetting[9].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable9GlobalIrq);
mConfigData->MadtInterruptSetting[10].Enable = PcdGet8 (PcdInterruptOverrideSettingTable10Enable);
mConfigData->MadtInterruptSetting[10].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable10SourceIrq);
mConfigData->MadtInterruptSetting[10].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable10Polarity);
mConfigData->MadtInterruptSetting[10].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable10TrigerMode);
mConfigData->MadtInterruptSetting[10].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable10GlobalIrq);
mConfigData->MadtInterruptSetting[11].Enable = PcdGet8 (PcdInterruptOverrideSettingTable11Enable);
mConfigData->MadtInterruptSetting[11].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable11SourceIrq);
mConfigData->MadtInterruptSetting[11].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable11Polarity);
mConfigData->MadtInterruptSetting[11].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable11TrigerMode);
mConfigData->MadtInterruptSetting[11].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable11GlobalIrq);
mConfigData->MadtInterruptSetting[12].Enable = PcdGet8 (PcdInterruptOverrideSettingTable12Enable);
mConfigData->MadtInterruptSetting[12].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable12SourceIrq);
mConfigData->MadtInterruptSetting[12].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable12Polarity);
mConfigData->MadtInterruptSetting[12].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable12TrigerMode);
mConfigData->MadtInterruptSetting[12].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable12GlobalIrq);
mConfigData->MadtInterruptSetting[13].Enable = PcdGet8 (PcdInterruptOverrideSettingTable13Enable);
mConfigData->MadtInterruptSetting[13].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable13SourceIrq);
mConfigData->MadtInterruptSetting[13].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable13Polarity);
mConfigData->MadtInterruptSetting[13].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable13TrigerMode);
mConfigData->MadtInterruptSetting[13].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable13GlobalIrq);
mConfigData->MadtInterruptSetting[14].Enable = PcdGet8 (PcdInterruptOverrideSettingTable14Enable);
mConfigData->MadtInterruptSetting[14].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable14SourceIrq);
mConfigData->MadtInterruptSetting[14].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable14Polarity);
mConfigData->MadtInterruptSetting[14].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable14TrigerMode);
mConfigData->MadtInterruptSetting[14].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable14GlobalIrq);
mConfigData->MadtInterruptSetting[15].Enable = PcdGet8 (PcdInterruptOverrideSettingTable15Enable);
mConfigData->MadtInterruptSetting[15].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable15SourceIrq);
mConfigData->MadtInterruptSetting[15].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable15Polarity);
mConfigData->MadtInterruptSetting[15].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable15TrigerMode);
mConfigData->MadtInterruptSetting[15].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable15GlobalIrq);
mConfigData->MadtIoApicSetting.IoApicAddress = (UINT32)PcdGet64(PcdIoApicBaseAddress);
mConfigData->MadtIoApicSetting.GlobalInterruptBase = PcdGet32 (PcdIoApicSettingGlobalInterruptBase);
mConfigData->MadtIoApicSetting.IoApicId = PcdGet8 (PcdIoApicSettingIoApicId);
mConfigData->MadtIoApicSetting.NmiEnable = PcdGet8 (PcdIoApicSettingNmiEnable);
mConfigData->MadtIoApicSetting.NmiSource = PcdGet8 (PcdIoApicSettingNmiSource);
mConfigData->MadtIoApicSetting.Polarity = PcdGet8 (PcdIoApicSettingPolarity);
mConfigData->MadtIoApicSetting.TrigerMode = PcdGet8 (PcdIoApicSettingTrigerMode);
mConfigData->MadtLocalApicSetting.NmiEnabelApicIdMask = PcdGet8 (PcdLocalApicSettingNmiEnabelApicIdMask);
mConfigData->MadtLocalApicSetting.AddressOverrideEnable = PcdGet8 (PcdLocalApicSettingAddressOverrideEnable);
mConfigData->MadtLocalApicSetting.Polarity = PcdGet8 (PcdLocalApicSettingPolarity);
mConfigData->MadtLocalApicSetting.TrigerMode = PcdGet8 (PcdLocalApicSettingTrigerMode);
mConfigData->MadtLocalApicSetting.LocalApicLint = PcdGet8 (PcdLocalApicSettingLocalApicLint);
mConfigData->MadtLocalApicSetting.LocalApicAddressOverride = PcdGet64 (PcdLocalApicAddressOverride);
mConfigData->MadtLocalApicSetting.LocalApicAddress = PcdGet32 (PcdCpuLocalApicBaseAddress);
}
UINT32
GetAcutalMadtTableSize (
IN MADT_CONFIG_DATA * MadtConfigData,
IN INTN NumberOfCPUs
)
{
UINT32 MadtSize;
UINT8 Index;
MadtSize = (UINT32)(sizeof (EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER) +
sizeof (EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE) * NumberOfCPUs +
sizeof (EFI_ACPI_2_0_IO_APIC_STRUCTURE) +
sizeof (EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE) * (MadtConfigData->MadtLocalApicSetting.AddressOverrideEnable != 0?1:0)
);
for (Index = 0; Index < EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT_MAX; Index ++ ) {
if (MadtConfigData->MadtInterruptSetting[Index].Enable != 0) {
MadtSize += sizeof (EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE);
}
}
for (Index = 0; Index < NumberOfCPUs; Index ++ ) {
if (0 != (MadtConfigData->MadtLocalApicSetting.NmiEnabelApicIdMask & (1 << Index))) {
MadtSize += sizeof (EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE);
}
}
if (0 != MadtConfigData->MadtIoApicSetting.NmiEnable) {
MadtSize += sizeof (EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE);
}
return MadtSize;
}
//
// Init Multiple APIC Description Table
//
EFI_STATUS
MadtTableInitialize (
OUT EFI_ACPI_COMMON_HEADER **MadtTable,
OUT UINTN *Size
)
{
EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *Madt;
EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE *ProcLocalApic;
EFI_ACPI_2_0_IO_APIC_STRUCTURE *IoApic;
EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE *InterruptSourceOverride;
EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE *IoApicNmiSource;
EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE *LocalApicNmiSource;
EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE *LocalApicAddressOverride;
EFI_MP_SERVICES_PROTOCOL *MpService;
UINTN NumberOfCPUs;
UINTN NumberOfEnabledCPUs;
MADT_CONFIG_DATA MadtConfigData;
UINT32 MadtSize;
UINTN Index;
EFI_STATUS Status;
ASSERT (NULL != MadtTable);
ASSERT (NULL != Size);
//
// Init Madt table data
//
InitMadtConfigData (&MadtConfigData);
//
// Find the MP Protocol. This is an MP platform, so MP protocol must be
// there.
//
Status = gBS->LocateProtocol (
&gEfiMpServiceProtocolGuid,
NULL,
(VOID **)&MpService
);
ASSERT_EFI_ERROR (Status);
//
// Determine the number of processors
//
MpService->GetNumberOfProcessors (
MpService,
&NumberOfCPUs,
&NumberOfEnabledCPUs
);
//ASSERT (NumberOfCPUs <= 2 && NumberOfCPUs > 0);
MadtSize = GetAcutalMadtTableSize (&MadtConfigData, NumberOfCPUs);
Madt = (EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *)AllocateZeroPool (MadtSize);
ASSERT_EFI_ERROR (Madt);
//
// Initialize MADT Header information
//
Madt->Header.Signature = EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE;
Madt->Header.Length = MadtSize;
Madt->Header.Revision = EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION;
Madt->Header.OemTableId = EFI_ACPI_OEM_TABLE_ID;
Madt->Header.OemRevision = EFI_ACPI_OEM_MADT_REVISION;
Madt->Header.CreatorId = EFI_ACPI_CREATOR_ID;
Madt->LocalApicAddress = MadtConfigData.MadtLocalApicSetting.LocalApicAddress;
Madt->Flags = EFI_ACPI_2_0_MULTIPLE_APIC_FLAGS;
CopyMem (Madt->Header.OemId, EFI_ACPI_OEM_ID, 6);
ProcLocalApic = (EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE *) (Madt + 1);
//
// Initialization of Processor's local APICs
//
for (Index = 0;Index < NumberOfCPUs; Index++) {
ProcLocalApic[Index].Type = EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC;
ProcLocalApic[Index].Length = sizeof (EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE);
ProcLocalApic[Index].AcpiProcessorId = (UINT8)(Index + 1);
ProcLocalApic[Index].ApicId = 0xff;
ProcLocalApic[Index].Flags = 0;
}
//
// Initialization of IO APIC.
// Note: Here assumes that there must be one and only one IO APIC in platform.
//
IoApic = (EFI_ACPI_2_0_IO_APIC_STRUCTURE *) (&ProcLocalApic[Index]);
IoApic->Type = EFI_ACPI_2_0_IO_APIC;
IoApic->Length = sizeof (EFI_ACPI_2_0_IO_APIC_STRUCTURE);
IoApic->IoApicId = MadtConfigData.MadtIoApicSetting.IoApicId;
IoApic->IoApicAddress = MadtConfigData.MadtIoApicSetting.IoApicAddress;
IoApic->GlobalSystemInterruptBase = MadtConfigData.MadtIoApicSetting.GlobalInterruptBase;
InterruptSourceOverride = (EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE *) (IoApic + 1);
for (Index = 0;Index < EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT_MAX; Index++ ){
if (MadtConfigData.MadtInterruptSetting[Index].Enable) {
InterruptSourceOverride->Type = EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE;
InterruptSourceOverride->Length = sizeof (EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE);
InterruptSourceOverride->Bus = 0;
InterruptSourceOverride->Source = MadtConfigData.MadtInterruptSetting[Index].SourceIrq;
InterruptSourceOverride->Flags = ((MadtConfigData.MadtInterruptSetting[Index].TrigerMode & 0x03) << 2) | (MadtConfigData.MadtInterruptSetting[Index].Polarity & 0x03);
InterruptSourceOverride->GlobalSystemInterrupt = MadtConfigData.MadtInterruptSetting[Index].GlobalIrq;
InterruptSourceOverride++;
}
}
//
// support NMI source configuration.
//
IoApicNmiSource = (EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE *) InterruptSourceOverride;
if ((BOOLEAN) MadtConfigData.MadtIoApicSetting.NmiEnable) {
IoApicNmiSource->Type = EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE;
IoApicNmiSource->Length = sizeof (EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE);
IoApicNmiSource->Flags = ((MadtConfigData.MadtIoApicSetting.TrigerMode & 0x03) << 2) | (MadtConfigData.MadtIoApicSetting.Polarity & 0x03);
IoApicNmiSource->GlobalSystemInterrupt = MadtConfigData.MadtIoApicSetting.NmiSource;
IoApicNmiSource ++;
}
//
// Assume each processor has same NMI interrupt source.
//
LocalApicNmiSource = (EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE *) IoApicNmiSource;
for (Index = 0;Index < NumberOfCPUs; Index++) {
if (0 != (MadtConfigData.MadtLocalApicSetting.NmiEnabelApicIdMask & (1 << Index))){
LocalApicNmiSource->Type = EFI_ACPI_2_0_LOCAL_APIC_NMI;
LocalApicNmiSource->Length = sizeof (EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE);
LocalApicNmiSource->LocalApicLint = MadtConfigData.MadtLocalApicSetting.LocalApicLint;
LocalApicNmiSource->Flags = ((MadtConfigData.MadtLocalApicSetting.TrigerMode & 0x03) << 2) | (MadtConfigData.MadtLocalApicSetting.Polarity & 0x03);
LocalApicNmiSource->AcpiProcessorId = (UINT8)(Index + 1);
LocalApicNmiSource++;
}
}
LocalApicAddressOverride = (EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE *) LocalApicNmiSource;
if ((BOOLEAN) MadtConfigData.MadtLocalApicSetting.AddressOverrideEnable) {
LocalApicAddressOverride->Type = EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE;
LocalApicAddressOverride->Length = sizeof (EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE);
LocalApicAddressOverride->LocalApicAddress = MadtConfigData.MadtLocalApicSetting.LocalApicAddressOverride;
LocalApicAddressOverride++;
}
*Size = MadtSize;
*MadtTable = (EFI_ACPI_COMMON_HEADER *) Madt;
return EFI_SUCCESS;
}

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## @file
# Boot Script Executor Module
#
# This is a standalone Boot Script Executor. Standalone means it does not
# depends on any PEI or DXE service.
#
# Copyright (c) 2013-2015 Intel Corporation.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BootScriptExecutorDxe
FILE_GUID = FA20568B-548B-4b2b-81EF-1BA08D4A3CEC
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = BootScriptExecutorEntryPoint
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64
#
[Sources]
ScriptExecute.h
ScriptExecute.c
[Sources.Ia32]
IA32/SetIdtEntry.c
IA32/S3Asm.asm
IA32/S3Asm.S
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
QuarkPlatformPkg/QuarkPlatformPkg.dec
QuarkSocPkg/QuarkSocPkg.dec
[LibraryClasses]
TimerLib
PcdLib
BaseMemoryLib
SmbusLib
UefiDriverEntryPoint
BaseLib
PciLib
IoLib
S3BootScriptLib
PeCoffLib
DxeServicesLib
UefiBootServicesTableLib
UefiRuntimeServicesTableLib
CacheMaintenanceLib
UefiLib
DebugAgentLib
LockBoxLib
IntelQNCLib
QNCAccessLib
[Guids]
gEfiBootScriptExecutorVariableGuid
gEfiBootScriptExecutorContextGuid
gPerformanceProtocolGuid
gEfiEventExitBootServicesGuid
[FeaturePcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable
[Depex]
gEfiLockBoxProtocolGuid

50
QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/IA32/S3Asm.S Normal file
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## @file
#
# Copyright (c) 2013-2015 Intel Corporation.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#-----------------------------------------
#VOID
#AsmTransferControl (
# IN UINT32 S3WakingVector,
# IN UINT32 AcpiLowMemoryBase
# );
#-----------------------------------------
ASM_GLOBAL ASM_PFX(AsmTransferControl)
ASM_PFX(AsmTransferControl):
# S3WakingVector :DWORD
# AcpiLowMemoryBase :DWORD
pushl %ebp
movl %esp,%ebp
leal LABLE, %eax
pushl $0x28 # CS
pushl %eax
movl 8(%ebp),%ecx
shrdl $20,%ecx,%ebx
andl $0xf,%ecx
movw %cx,%bx
movl %ebx, jmp_addr
lret
LABLE:
.byte 0xb8,0x30,0 # mov ax, 30h as selector
movw %ax,%ds
movw %ax,%es
movw %ax,%fs
movw %ax,%gs
movw %ax,%ss
movl %cr0, %eax # Get control register 0
.byte 0x66
.byte 0x83,0xe0,0xfe # and eax, 0fffffffeh ; Clear PE bit (bit #0)
.byte 0xf,0x22,0xc0 # mov cr0, eax ; Activate real mode
.byte 0xea # jmp far @jmp_addr
jmp_addr:
.long 0

57
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;; @file
; This is the assembly code for transferring to control to OS S3 waking vector
; for IA32 platform
;
; Copyright (c) 2013-2015 Intel Corporation.
;
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
.586P
.model flat,C
.code
;-----------------------------------------
;VOID
;AsmTransferControl (
; IN UINT32 S3WakingVector,
; IN UINT32 AcpiLowMemoryBase
; );
;-----------------------------------------
AsmTransferControl PROC
; S3WakingVector :DWORD
; AcpiLowMemoryBase :DWORD
push ebp
mov ebp, esp
lea eax, @F
push 28h ; CS
push eax
mov ecx, [ebp + 8]
shrd ebx, ecx, 20
and ecx, 0fh
mov bx, cx
mov @jmp_addr, ebx
retf
@@:
DB 0b8h, 30h, 0 ; mov ax, 30h as selector
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
mov ss, ax
mov eax, cr0 ; Get control register 0
DB 66h
DB 83h, 0e0h, 0feh ; and eax, 0fffffffeh ; Clear PE bit (bit #0)
DB 0fh, 22h, 0c0h ; mov cr0, eax ; Activate real mode
DB 0eah ; jmp far @jmp_addr
@jmp_addr DD ?
AsmTransferControl ENDP
END

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QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/IA32/SetIdtEntry.c Normal file
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/** @file
Set a IDT entry for debug purpose
Set a IDT entry for interrupt vector 3 for debug purpose for IA32 platform
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "ScriptExecute.h"
//
// INTERRUPT_GATE_DESCRIPTOR and SetIdtEntry () are used to setup IDT to do debug
//
#pragma pack(1)
typedef struct {
UINT16 OffsetLow;
UINT16 SegmentSelector;
UINT16 Attributes;
UINT16 OffsetHigh;
} INTERRUPT_GATE_DESCRIPTOR;
#define INTERRUPT_GATE_ATTRIBUTE 0x8e00
#pragma pack()
/**
Set a IDT entry for interrupt vector 3 for debug purpose.
@param AcpiS3Context a pointer to a structure of ACPI_S3_CONTEXT
**/
VOID
SetIdtEntry (
IN ACPI_S3_CONTEXT *AcpiS3Context
)
{
INTERRUPT_GATE_DESCRIPTOR *IdtEntry;
IA32_DESCRIPTOR *IdtDescriptor;
UINTN S3DebugBuffer;
//
// Restore IDT for debug
//
IdtDescriptor = (IA32_DESCRIPTOR *) (UINTN) (AcpiS3Context->IdtrProfile);
IdtEntry = (INTERRUPT_GATE_DESCRIPTOR *)(IdtDescriptor->Base + (3 * sizeof (INTERRUPT_GATE_DESCRIPTOR)));
S3DebugBuffer = (UINTN) (AcpiS3Context->S3DebugBufferAddress);
IdtEntry->OffsetLow = (UINT16)S3DebugBuffer;
IdtEntry->SegmentSelector = (UINT16)AsmReadCs ();
IdtEntry->Attributes = (UINT16)INTERRUPT_GATE_ATTRIBUTE;
IdtEntry->OffsetHigh = (UINT16)(S3DebugBuffer >> 16);
AsmWriteIdtr (IdtDescriptor);
}

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/** @file
This is the code for Boot Script Executer module.
This driver is dispatched by Dxe core and the driver will reload itself to ACPI NVS memory
in the entry point. The functionality is to interpret and restore the S3 boot script
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "ScriptExecute.h"
#pragma pack(1)
typedef union {
struct {
UINT32 LimitLow : 16;
UINT32 BaseLow : 16;
UINT32 BaseMid : 8;
UINT32 Type : 4;
UINT32 System : 1;
UINT32 Dpl : 2;
UINT32 Present : 1;
UINT32 LimitHigh : 4;
UINT32 Software : 1;
UINT32 Reserved : 1;
UINT32 DefaultSize : 1;
UINT32 Granularity : 1;
UINT32 BaseHigh : 8;
} Bits;
UINT64 Uint64;
} IA32_GDT;
#pragma pack()
EFI_GUID mBootScriptExecutorImageGuid = {
0x9a8d3433, 0x9fe8, 0x42b6, {0x87, 0xb, 0x1e, 0x31, 0xc8, 0x4e, 0xbe, 0x3b}
};
//
// Global Descriptor Table (GDT)
//
GLOBAL_REMOVE_IF_UNREFERENCED IA32_GDT mGdtEntries[] = {
/* selector { Global Segment Descriptor } */
/* 0x00 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
/* 0x08 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
/* 0x10 */ {{0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 0, 1, 1, 0}},
/* 0x18 */ {{0xFFFF, 0, 0, 0x3, 1, 0, 1, 0xF, 0, 0, 1, 1, 0}},
/* 0x20 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
/* 0x28 */ {{0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 0, 0, 1, 0}},
/* 0x30 */ {{0xFFFF, 0, 0, 0x3, 1, 0, 1, 0xF, 0, 0, 0, 1, 0}},
/* 0x38 */ {{0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 1, 0, 1, 0}},
/* 0x40 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
};
//
// IA32 Gdt register
//
GLOBAL_REMOVE_IF_UNREFERENCED CONST IA32_DESCRIPTOR mGdt = {
sizeof (mGdtEntries) - 1,
(UINTN) mGdtEntries
};
/**
Entry function of Boot script exector. This function will be executed in
S3 boot path.
This function should not return, because it is invoked by switch stack.
@param AcpiS3Context a pointer to a structure of ACPI_S3_CONTEXT
@param PeiS3ResumeState a pointer to a structure of PEI_S3_RESUME_STATE
@retval EFI_INVALID_PARAMETER - OS waking vector not found
@retval EFI_UNSUPPORTED - something wrong when we resume to OS
**/
EFI_STATUS
EFIAPI
S3BootScriptExecutorEntryFunction (
IN ACPI_S3_CONTEXT *AcpiS3Context,
IN PEI_S3_RESUME_STATE *PeiS3ResumeState
)
{
EFI_STATUS Status;
//
// Disable interrupt of Debug timer, since new IDT table cannot handle it.
//
SaveAndSetDebugTimerInterrupt (FALSE);
//
// Restore IDT for debug
//
SetIdtEntry (AcpiS3Context);
//
// Initialize Debug Agent to support source level debug in S3 path.
//
InitializeDebugAgent (DEBUG_AGENT_INIT_S3, NULL, NULL);
//
// Because not install BootScriptExecute PPI(used just in this module), So just pass NULL
// for that parameter.
//
Status = S3BootScriptExecute ();
AsmWbinvd ();
//
// We need turn back to S3Resume - install boot script done ppi and report status code on S3resume.
//
if (PeiS3ResumeState != 0) {
//
// Need report status back to S3ResumePeim.
// If boot script execution is failed, S3ResumePeim wil report the error status code.
//
PeiS3ResumeState->ReturnStatus = (UINT64)(UINTN)Status;
//
// IA32 S3 Resume
//
DEBUG ((EFI_D_INFO, "Call SwitchStack() to return to S3 Resume in PEI Phase\n"));
PeiS3ResumeState->AsmTransferControl = (EFI_PHYSICAL_ADDRESS)(UINTN)PlatformTransferControl16;
SwitchStack (
(SWITCH_STACK_ENTRY_POINT)(UINTN)PeiS3ResumeState->ReturnEntryPoint,
(VOID *)(UINTN)AcpiS3Context,
(VOID *)(UINTN)PeiS3ResumeState,
(VOID *)(UINTN)PeiS3ResumeState->ReturnStackPointer
);
//
// Never run to here
//
CpuDeadLoop();
return EFI_UNSUPPORTED;
}
//
// Never run to here
//
CpuDeadLoop();
return EFI_UNSUPPORTED;
}
/**
Entrypoint of Boot script exector driver, this function will be executed in
normal boot phase and invoked by DXE dispatch.
@param[in] ImageHandle The firmware allocated handle for the EFI image.
@param[in] SystemTable A pointer to the EFI System Table.
@retval EFI_SUCCESS The entry point is executed successfully.
@retval other Some error occurs when executing this entry point.
**/
EFI_STATUS
EFIAPI
BootScriptExecutorEntryPoint (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
UINT8 *Buffer;
UINTN BufferSize;
UINTN Pages;
EFI_PHYSICAL_ADDRESS FfsBuffer;
PE_COFF_LOADER_IMAGE_CONTEXT ImageContext;
BOOT_SCRIPT_EXECUTOR_VARIABLE *EfiBootScriptExecutorVariable;
EFI_PHYSICAL_ADDRESS BootScriptExecutorBuffer;
EFI_STATUS Status;
VOID *DevicePath;
EFI_HANDLE NewImageHandle;
//
// Test if the gEfiCallerIdGuid of this image is already installed. if not, the entry
// point is loaded by DXE code which is the first time loaded. or else, it is already
// be reloaded be itself.This is a work-around
//
Status = gBS->LocateProtocol (&gEfiCallerIdGuid, NULL, &DevicePath);
if (EFI_ERROR (Status)) {
//
// This is the first-time loaded by DXE core. reload itself to NVS mem
//
//
// A workarouond: Here we install a dummy handle
//
NewImageHandle = NULL;
Status = gBS->InstallProtocolInterface (
&NewImageHandle,
&gEfiCallerIdGuid,
EFI_NATIVE_INTERFACE,
NULL
);
Status = GetSectionFromAnyFv (
&gEfiCallerIdGuid,
EFI_SECTION_PE32,
0,
(VOID **) &Buffer,
&BufferSize
);
ImageContext.Handle = Buffer;
ImageContext.ImageRead = PeCoffLoaderImageReadFromMemory;
//
// Get information about the image being loaded
//
Status = PeCoffLoaderGetImageInfo (&ImageContext);
if (EFI_ERROR (Status)) {
return Status;
}
Pages = EFI_SIZE_TO_PAGES(BufferSize + ImageContext.SectionAlignment);
FfsBuffer = 0xFFFFFFFF;
Status = gBS->AllocatePages (
AllocateMaxAddress,
EfiACPIMemoryNVS,
Pages,
&FfsBuffer
);
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
ImageContext.ImageAddress = (PHYSICAL_ADDRESS)(UINTN)FfsBuffer;
//
// Align buffer on section boundry
//
ImageContext.ImageAddress += ImageContext.SectionAlignment - 1;
ImageContext.ImageAddress &= ~(ImageContext.SectionAlignment - 1);
//
// Load the image to our new buffer
//
Status = PeCoffLoaderLoadImage (&ImageContext);
if (EFI_ERROR (Status)) {
gBS->FreePages (FfsBuffer, Pages);
return Status;
}
//
// Relocate the image in our new buffer
//
Status = PeCoffLoaderRelocateImage (&ImageContext);
if (EFI_ERROR (Status)) {
PeCoffLoaderUnloadImage (&ImageContext);
gBS->FreePages (FfsBuffer, Pages);
return Status;
}
//
// Flush the instruction cache so the image data is written before we execute it
//
InvalidateInstructionCacheRange ((VOID *)(UINTN)ImageContext.ImageAddress, (UINTN)ImageContext.ImageSize);
Status = ((EFI_IMAGE_ENTRY_POINT)(UINTN)(ImageContext.EntryPoint)) (NewImageHandle, SystemTable);
if (EFI_ERROR (Status)) {
gBS->FreePages (FfsBuffer, Pages);
return Status;
}
//
// Additional step for BootScript integrity
// Save BootScriptExecutor image
//
Status = SaveLockBox (
&mBootScriptExecutorImageGuid,
(VOID *)(UINTN)ImageContext.ImageAddress,
(UINTN)ImageContext.ImageSize
);
ASSERT_EFI_ERROR (Status);
Status = SetLockBoxAttributes (&mBootScriptExecutorImageGuid, LOCK_BOX_ATTRIBUTE_RESTORE_IN_PLACE);
ASSERT_EFI_ERROR (Status);
} else {
//
// the entry point is invoked after reloading. following code only run in ACPI NVS
//
BufferSize = sizeof (BOOT_SCRIPT_EXECUTOR_VARIABLE);
BootScriptExecutorBuffer = 0xFFFFFFFF;
Pages = EFI_SIZE_TO_PAGES(BufferSize);
Status = gBS->AllocatePages (
AllocateMaxAddress,
EfiACPIMemoryNVS,
Pages,
&BootScriptExecutorBuffer
);
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
EfiBootScriptExecutorVariable = (BOOT_SCRIPT_EXECUTOR_VARIABLE *)(UINTN)BootScriptExecutorBuffer;
EfiBootScriptExecutorVariable->BootScriptExecutorEntrypoint = (UINTN) S3BootScriptExecutorEntryFunction ;
Status = SaveLockBox (
&gEfiBootScriptExecutorVariableGuid,
&BootScriptExecutorBuffer,
sizeof(BootScriptExecutorBuffer)
);
ASSERT_EFI_ERROR (Status);
//
// Additional step for BootScript integrity
// Save BootScriptExecutor context
//
Status = SaveLockBox (
&gEfiBootScriptExecutorContextGuid,
EfiBootScriptExecutorVariable,
sizeof(*EfiBootScriptExecutorVariable)
);
ASSERT_EFI_ERROR (Status);
Status = SetLockBoxAttributes (&gEfiBootScriptExecutorContextGuid, LOCK_BOX_ATTRIBUTE_RESTORE_IN_PLACE);
ASSERT_EFI_ERROR (Status);
}
return EFI_SUCCESS;
}
/**
Platform specific mechanism to transfer control to 16bit OS waking vector
@param[in] AcpiWakingVector The 16bit OS waking vector
@param[in] AcpiLowMemoryBase A buffer under 1M which could be used during the transfer
**/
VOID
PlatformTransferControl16 (
IN UINT32 AcpiWakingVector,
IN UINT32 AcpiLowMemoryBase
)
{
UINT32 NewValue;
UINT64 BaseAddress;
UINT64 SmramLength;
UINTN Index;
DEBUG (( EFI_D_INFO, "PlatformTransferControl - Entry\r\n"));
//
// Need to make sure the GDT is loaded with values that support long mode and real mode.
//
AsmWriteGdtr (&mGdt);
//
// Disable eSram block (this will also clear/zero eSRAM)
// We only use eSRAM in the PEI phase. Disable now that we are resuming the OS
//
NewValue = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK);
NewValue |= BLOCK_DISABLE_PG;
QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK, NewValue);
//
// Update HMBOUND to top of DDR3 memory and LOCK
// We disabled eSRAM so now we move HMBOUND down to top of DDR3
//
QNCGetTSEGMemoryRange (&BaseAddress, &SmramLength);
NewValue = (UINT32)(BaseAddress + SmramLength);
DEBUG ((EFI_D_INFO,"Locking HMBOUND at: = 0x%8x\n",NewValue));
QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_HMBOUND_REG, (NewValue | HMBOUND_LOCK));
//
// Lock all IMR regions now that HMBOUND is locked
//
for (Index = (QUARK_NC_MEMORY_MANAGER_IMR0+QUARK_NC_MEMORY_MANAGER_IMRXL); Index <= (QUARK_NC_MEMORY_MANAGER_IMR7+QUARK_NC_MEMORY_MANAGER_IMRXL); Index += 4) {
NewValue = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, Index);
NewValue |= IMR_LOCK;
QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, Index, NewValue);
}
//
// Call ASM routine to switch to real mode and jump to 16bit OS waking vector
//
AsmTransferControl(AcpiWakingVector, 0);
//
// Never run to here
//
CpuDeadLoop();
}

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/** @file
The header file for Boot Script Executer module.
This driver is dispatched by Dxe core and the driver will reload itself to ACPI NVS memory
in the entry point. The functionality is to interpret and restore the S3 boot script
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _SCRIPT_EXECUTE_H_
#define _SCRIPT_EXECUTE_H_
#include <PiDxe.h>
#include <Library/BaseLib.h>
#include <Library/UefiDriverEntryPoint.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/S3BootScriptLib.h>
#include <Library/PeCoffLib.h>
#include <Library/DxeServicesLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/PcdLib.h>
#include <Library/CacheMaintenanceLib.h>
#include <Library/TimerLib.h>
#include <Library/UefiLib.h>
#include <Library/DebugAgentLib.h>
#include <Library/LockBoxLib.h>
#include <Library/IntelQNCLib.h>
#include <Library/QNCAccessLib.h>
#include <Guid/AcpiS3Context.h>
#include <Guid/BootScriptExecutorVariable.h>
#include <Guid/EventGroup.h>
#include <IndustryStandard/Acpi.h>
/**
a ASM function to transfer control to OS.
@param S3WakingVector The S3 waking up vector saved in ACPI Facs table
@param AcpiLowMemoryBase a buffer under 1M which could be used during the transfer
**/
VOID
AsmTransferControl (
IN UINT32 S3WakingVector,
IN UINT32 AcpiLowMemoryBase
);
VOID
SetIdtEntry (
IN ACPI_S3_CONTEXT *AcpiS3Context
);
/**
Platform specific mechanism to transfer control to 16bit OS waking vector
@param[in] AcpiWakingVector The 16bit OS waking vector
@param[in] AcpiLowMemoryBase A buffer under 1M which could be used during the transfer
**/
VOID
PlatformTransferControl16 (
IN UINT32 AcpiWakingVector,
IN UINT32 AcpiLowMemoryBase
);
#endif //_SCRIPT_EXECUTE_H_

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QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.c Normal file
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QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.h Normal file
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/** @file
Header file for SMM S3 Handler Driver.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _ACPI_SMM_DRIVER_H
#define _ACPI_SMM_DRIVER_H
//
// Include files
//
//
// Driver Consumed Protocol Prototypes
//
#include <Protocol/SmmSxDispatch2.h>
#include <Protocol/SmmSwDispatch2.h>
#include <Protocol/FirmwareVolume.h>
#include <Protocol/GlobalNvsArea.h>
#include <Protocol/PciRootBridgeIo.h>
#include <Library/UefiDriverEntryPoint.h>
#include <Protocol/Spi.h>
#include <Library/IoLib.h>
#include <Library/PciLib.h>
#include <Library/PcdLib.h>
#include <Library/LockBoxLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/BaseLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/S3IoLib.h>
#include <Library/S3BootScriptLib.h>
#include <Guid/Acpi.h>
#include <Guid/GlobalVariable.h>
#include <Library/SmmServicesTableLib.h>
#include <Guid/SmramMemoryReserve.h>
#include <Library/ReportStatusCodeLib.h>
#include <Library/HobLib.h>
#include <QNCAccess.h>
#include <Library/QNCAccessLib.h>
#include <Library/IntelQNCLib.h>
#include <Library/PlatformHelperLib.h>
#include <Library/PlatformPcieHelperLib.h>
#include "Platform.h"
#include <IndustryStandard/Pci22.h>
#define EFI_ACPI_ACPI_ENABLE 0xA0
#define EFI_ACPI_ACPI_DISABLE 0xA1
#define R_IOPORT_CMOS_STANDARD_INDEX 0x70
#define R_IOPORT_CMOS_STANDARD_DATA 0x71
#define RTC_ADDRESS_REGISTER_C 12
#define RTC_ADDRESS_REGISTER_D 13
#define PCI_DEVICE(Bus, Dev, Func) \
Bus, Dev, Func
#define PCI_REG_MASK(Byte0, Byte1, Byte2, Byte3, Byte4, Byte5, Byte6, Byte7) \
Byte0, Byte1, Byte2, Byte3, Byte4, Byte5, Byte6, Byte7
#define PCI_DEVICE_END 0xFF
//
// Related data structures definition
//
typedef struct _EFI_ACPI_SMM_DEV {
//
// Parent dispatch driver returned sleep handle
//
EFI_HANDLE S3SleepEntryHandle;
EFI_HANDLE S4SleepEntryHandle;
EFI_HANDLE S1SleepEntryHandle;
EFI_HANDLE S5SoftOffEntryHandle;
EFI_HANDLE EnableAcpiHandle;
EFI_HANDLE DisableAcpiHandle;
EFI_HANDLE PpCallbackHandle;
EFI_HANDLE MorCallbackHandle;
//
// QNC Power Management I/O register base
//
UINT32 QncPmBase;
//
// QNC General Purpose Event0 register base
//
UINT32 QncGpe0Base;
UINT32 BootScriptSaved;
} EFI_ACPI_SMM_DEV;
//
// Prototypes
//
EFI_STATUS
InitPlatformAcpiSmm (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable,
IN OUT VOID *CommBuffer,
IN OUT UINTN *CommBufferSize
);
EFI_STATUS
SxSleepEntryCallBack (
IN EFI_HANDLE DispatchHandle,
IN CONST VOID *DispatchContext,
IN OUT VOID *CommBuffer,
IN OUT UINTN *CommBufferSize
);
EFI_STATUS
DisableAcpiCallback (
IN EFI_HANDLE DispatchHandle,
IN CONST VOID *DispatchContext,
IN OUT VOID *CommBuffer,
IN OUT UINTN *CommBufferSize
);
EFI_STATUS
EnableAcpiCallback (
IN EFI_HANDLE DispatchHandle,
IN CONST VOID *DispatchContext,
IN OUT VOID *CommBuffer,
IN OUT UINTN *CommBufferSize
);
EFI_STATUS
RegisterToDispatchDriver (
VOID
);
EFI_STATUS
GetAllQncPmBase (
IN EFI_SMM_SYSTEM_TABLE2 *Smst
);
EFI_STATUS
SaveRuntimeScriptTable (
IN EFI_SMM_SYSTEM_TABLE2 *Smst
);
EFI_STATUS
RestoreQncS3SwCallback (
IN EFI_HANDLE DispatchHandle,
IN CONST VOID *DispatchContext,
IN OUT VOID *CommBuffer,
IN OUT UINTN *CommBufferSize
);
extern EFI_GUID gQncS3CodeInLockBoxGuid;
extern EFI_GUID gQncS3ContextInLockBoxGuid;
#endif

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## @file
# Component description file for ACPI SMM Platform handler module
#
# This is QNC Smm platform driver .
# Copyright (c) 2013-2015 Intel Corporation.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = AcpiSmmPlatform
FILE_GUID = F5AC7057-5650-466e-B692-76A47223EFB0
MODULE_TYPE = DXE_SMM_DRIVER
VERSION_STRING = 1.0
PI_SPECIFICATION_VERSION = 0x0001000A
ENTRY_POINT = InitAcpiSmmPlatform
[Sources]
AcpiSmmPlatform.c
AcpiSmmPlatform.h
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
IntelFrameworkPkg/IntelFrameworkPkg.dec
IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
QuarkSocPkg/QuarkSocPkg.dec
QuarkPlatformPkg/QuarkPlatformPkg.dec
[LibraryClasses]
UefiBootServicesTableLib
UefiRuntimeServicesTableLib
ReportStatusCodeLib
UefiDriverEntryPoint
DebugLib
IoLib
PciLib
BaseMemoryLib
BaseLib
SmmServicesTableLib
PcdLib
HobLib
S3BootScriptLib
LockBoxLib
PlatformHelperLib
IntelQNCLib
PlatformPcieHelperLib
[Protocols]
gEfiSmmSxDispatch2ProtocolGuid
gEfiPciRootBridgeIoProtocolGuid
gEfiVariableArchProtocolGuid
gEfiVariableWriteArchProtocolGuid
gEfiGlobalNvsAreaProtocolGuid
gEfiSmmSwDispatch2ProtocolGuid
[Guids]
gEfiSmmPeiSmramMemoryReserveGuid
gQncS3CodeInLockBoxGuid
gQncS3ContextInLockBoxGuid
[Pcd]
gQuarkPlatformTokenSpaceGuid.PcdPlatformType
gEfiMdeModulePkgTokenSpaceGuid.PcdProgressCodeS3SuspendStart
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdS3AcpiReservedMemorySize
gEfiQuarkNcSocIdTokenSpaceGuid.PcdGpe0blkIoBaseAddress
gEfiQuarkNcSocIdTokenSpaceGuid.PcdPm1blkIoBaseAddress
[Depex]
gEfiSmmSxDispatch2ProtocolGuid AND
gEfiPciRootBridgeIoProtocolGuid AND
gEfiVariableArchProtocolGuid AND
gEfiVariableWriteArchProtocolGuid AND
gEfiGlobalNvsAreaProtocolGuid AND
gEfiQncS3SupportProtocolGuid

390
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/** @file
Processor power management initialization code.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "SmmPowerManagement.h"
//
// Global variables
//
extern EFI_ACPI_SDT_PROTOCOL *mAcpiSdt;
extern EFI_ACPI_TABLE_PROTOCOL *mAcpiTable;
extern EFI_GUID gPowerManagementAcpiTableStorageGuid;
/**
This function is the entry of processor power management initialization code.
It initializes the processor's power management features based on the user
configurations and hardware capabilities.
**/
VOID
PpmInit (
VOID
)
{
//
// Processor Power Management Flags
//
mGlobalNvsAreaPtr->Cfgd = PcdGet32(PcdPpmFlags);
//
// Patch and publish power management related acpi tables
//
PpmPatchAndPublishAcpiTables();
}
/**
This function is to patch and publish power management related acpi tables.
**/
VOID
PpmPatchAndPublishAcpiTables (
VOID
)
{
//
// Patch FADT table to enable C2,C3
//
PpmPatchFadtTable();
//
// Load all the power management acpi tables and patch IST table
//
PpmLoadAndPatchPMTables();
}
/**
This function is to patch PLvl2Lat and PLvl3Lat to enable C2, C3 support in OS.
**/
VOID
PpmPatchFadtTable (
VOID
)
{
EFI_STATUS Status;
EFI_ACPI_DESCRIPTION_HEADER *Table;
EFI_ACPI_SDT_HEADER *CurrentTable;
EFI_ACPI_TABLE_VERSION Version;
UINTN Index;
UINTN Handle;
EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *FadtPointer;
//
// Scan all the acpi tables to find FADT 2.0
//
Index = 0;
do {
Status = mAcpiSdt->GetAcpiTable (
Index,
&CurrentTable,
&Version,
&Handle
);
if (Status == EFI_NOT_FOUND) {
break;
}
ASSERT_EFI_ERROR (Status);
Index++;
} while (CurrentTable->Signature != EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE || CurrentTable->Revision != 0x03);
ASSERT (CurrentTable->Signature == EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE);
Table = NULL;
Status = gBS->AllocatePool (EfiBootServicesData, CurrentTable->Length, (VOID **) &Table);
ASSERT (Table != NULL);
CopyMem (Table, CurrentTable, CurrentTable->Length);
FadtPointer = (EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE*) Table;
//
// Update the ACPI table and recalculate checksum
//
Status = mAcpiTable->UninstallAcpiTable (mAcpiTable, Handle);
if (EFI_ERROR (Status)) {
//
// Should not get an error here ever, but abort if we do.
//
return ;
}
//
// Update the check sum
// It needs to be zeroed before the checksum calculation
//
((EFI_ACPI_SDT_HEADER *)Table)->Checksum = 0;
((EFI_ACPI_SDT_HEADER *)Table)->Checksum =
CalculateCheckSum8 ((VOID *)Table, Table->Length);
//
// Add the table
//
Status = mAcpiTable->InstallAcpiTable (
mAcpiTable,
Table,
Table->Length,
&Handle
);
ASSERT_EFI_ERROR (Status);
gBS->FreePool (Table);
}
VOID
SsdtTableUpdate (
IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader
)
/*++
Routine Description:
Update the SSDT table
Arguments:
Table - The SSDT table to be patched
Returns:
None
--*/
{
UINT8 *CurrPtr;
UINT8 *SsdtPointer;
UINT32 *Signature;
//
// Loop through the ASL looking for values that we must fix up.
//
CurrPtr = (UINT8 *) TableHeader;
for (SsdtPointer = CurrPtr;
SsdtPointer <= (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length);
SsdtPointer++
)
{
Signature = (UINT32 *) SsdtPointer;
if ((*Signature) == SIGNATURE_32 ('P', 'M', 'B', 'A')) {
switch (*(Signature+1)) {
case (SIGNATURE_32 ('L', 'V', 'L', '0')):
Signature[0] = PcdGet16(PcdPmbaIoBaseAddress);
Signature[1] = 0;
break;
case (SIGNATURE_32 ('L', 'V', 'L', '2')):
Signature[0] = PcdGet16(PcdPmbaIoLVL2);
Signature[1] = 0;
break;
}
}
}
}
EFI_STATUS
LocateSupportProtocol (
IN EFI_GUID *Protocol,
OUT VOID **Instance,
IN UINT32 Type
)
/*++
Routine Description:
Locate the first instance of a protocol. If the protocol requested is an
FV protocol, then it will return the first FV that contains the ACPI table
storage file.
Arguments:
Protocol The protocol to find.
Instance Return pointer to the first instance of the protocol
Returns:
EFI_SUCCESS The function completed successfully.
EFI_NOT_FOUND The protocol could not be located.
EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol.
--*/
{
EFI_STATUS Status;
EFI_HANDLE *HandleBuffer;
UINTN NumberOfHandles;
EFI_FV_FILETYPE FileType;
UINT32 FvStatus;
EFI_FV_FILE_ATTRIBUTES Attributes;
UINTN Size;
UINTN i;
FvStatus = 0;
//
// Locate protocol.
//
Status = gBS->LocateHandleBuffer (
ByProtocol,
Protocol,
NULL,
&NumberOfHandles,
&HandleBuffer
);
if (EFI_ERROR (Status)) {
//
// Defined errors at this time are not found and out of resources.
//
return Status;
}
//
// Looking for FV with ACPI storage file
//
for (i = 0; i < NumberOfHandles; i++) {
//
// Get the protocol on this handle
// This should not fail because of LocateHandleBuffer
//
Status = gBS->HandleProtocol (
HandleBuffer[i],
Protocol,
Instance
);
ASSERT_EFI_ERROR (Status);
if (!Type) {
//
// Not looking for the FV protocol, so find the first instance of the
// protocol. There should not be any errors because our handle buffer
// should always contain at least one or LocateHandleBuffer would have
// returned not found.
//
break;
}
//
// See if it has the ACPI storage file
//
Status = ((EFI_FIRMWARE_VOLUME2_PROTOCOL*) (*Instance))->ReadFile (*Instance,
&gPowerManagementAcpiTableStorageGuid,
NULL,
&Size,
&FileType,
&Attributes,
&FvStatus
);
//
// If we found it, then we are done
//
if (Status == EFI_SUCCESS) {
break;
}
}
//
// Our exit status is determined by the success of the previous operations
// If the protocol was found, Instance already points to it.
//
//
// Free any allocated buffers
//
gBS->FreePool (HandleBuffer);
return Status;
}
/**
This function is to load all the power management acpi tables and patch IST table.
**/
VOID
PpmLoadAndPatchPMTables (
VOID
)
{
EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
EFI_STATUS Status;
INTN Instance;
EFI_ACPI_COMMON_HEADER *CurrentTable;
UINTN TableHandle;
UINT32 FvStatus;
UINTN Size;
EFI_ACPI_TABLE_VERSION Version;
Status = LocateSupportProtocol (&gEfiFirmwareVolume2ProtocolGuid, (VOID**)&FwVol, 1);
if (EFI_ERROR (Status)) {
return;
}
//
// Read tables from the storage file.
//
Instance = 0;
CurrentTable = NULL;
while (Status == EFI_SUCCESS) {
Status = FwVol->ReadSection (
FwVol,
&gPowerManagementAcpiTableStorageGuid,
EFI_SECTION_RAW,
Instance,
(VOID**)&CurrentTable,
&Size,
&FvStatus
);
if (!EFI_ERROR(Status)) {
Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0;
if(((EFI_ACPI_DESCRIPTION_HEADER*) CurrentTable)->OemTableId == SIGNATURE_64 ('C', 'p', 'u', '0', 'I', 's', 't', 0)) {
Version = EFI_ACPI_TABLE_VERSION_NONE;
} else if(((EFI_ACPI_DESCRIPTION_HEADER*) CurrentTable)->OemTableId == SIGNATURE_64 ('C', 'p', 'u', '1', 'I', 's', 't', 0)) {
Version = EFI_ACPI_TABLE_VERSION_NONE;
}
SsdtTableUpdate ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable);
//
// Update the check sum
// It needs to be zeroed before the checksum calculation
//
((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum = 0;
((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum = (UINT8)
CalculateCheckSum8 ((VOID *)CurrentTable, CurrentTable->Length);
//
// Add the table
//
TableHandle = 0;
Status = mAcpiTable->InstallAcpiTable (
mAcpiTable,
CurrentTable,
CurrentTable->Length,
&TableHandle
);
ASSERT_EFI_ERROR (Status);
//
// Increment the instance
//
Instance++;
CurrentTable = NULL;
}
}
}

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/** @file
Processor power management initialization code.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _PPM_H
#define _PPM_H
//
// Bit definitions of PPMFlags
//
#define PPM_GV3 (1 << 0) // Geyserville 3
#define PPM_TURBO (1 << 1) // Turbo Mode
#define PPM_SUPER_LFM (1 << 2) // N/2 Ratio
#define PPM_C1 (1 << 4) // C1 Capable, Enabled
#define PPM_C2 (1 << 5) // C2 Capable, Enabled
#define PPM_C3 (1 << 6) // C3 Capable, Enabled
#define PPM_C4 (1 << 7) // C4 Capable, Enabled
#define PPM_C5 (1 << 8) // C5/Deep C4 Capable, Enabled
#define PPM_C6 (1 << 9) // C6 Capable, Enabled
#define PPM_C1E (1 << 10) // C1E Enabled
#define PPM_C2E (1 << 11) // C2E Enabled
#define PPM_C3E (1 << 12) // C3E Enabled
#define PPM_C4E (1 << 13) // C4E Enabled
#define PPM_HARD_C4E (1 << 14) // Hard C4E Capable, Enabled
#define PPM_TM1 (1 << 16) // Thermal Monitor 1
#define PPM_TM2 (1 << 17) // Thermal Monitor 2
#define PPM_PHOT (1 << 19) // Bi-directional ProcHot
#define PPM_MWAIT_EXT (1 << 21) // MWAIT extensions supported
#define PPM_CMP (1 << 24) // CMP supported, Enabled
#define PPM_TSTATE (1 << 28) // CPU T states supported
#define PPM_C_STATES (PPM_C1 + PPM_C2 + PPM_C3 + PPM_C4 + PPM_C5 + PPM_C6)
#define PPM_CE_STATES (PPM_C1E + PPM_C2E + PPM_C3E + PPM_C4E + PPM_HARD_C4E)
#define MAX_P_STATES_NUM 12
#define AML_NAME_OP 0x08
#define AML_SCOPE_OP 0x10
#define AML_PACKAGE_OP 0x12
#define AML_METHOD_OP 0x14
#define S3_CPU_REGISTER_TABLE_GUID \
{ \
0xc4ef988d, 0xe5e, 0x4403, { 0xbe, 0xeb, 0xf1, 0xbb, 0x6, 0x79, 0x6e, 0xdf } \
}
#pragma pack(1)
typedef struct {
UINT8 StartByte;
UINT32 NameStr;
UINT8 OpCode;
UINT16 Size; // Hardcode to 16bit width because the table we use is fixed size
UINT8 NumEntries;
} EFI_ACPI_NAME_COMMAND;
typedef struct {
UINT8 PackageOp;
UINT8 PkgLeadByte;
UINT8 NumEntries;
UINT8 DwordPrefix0;
UINT32 CoreFreq;
UINT8 DwordPrefix1;
UINT32 Power;
UINT8 DwordPrefix2;
UINT32 TransLatency;
UINT8 DwordPrefix3;
UINT32 BMLatency;
UINT8 DwordPrefix4;
UINT32 Control;
UINT8 DwordPrefix5;
UINT32 Status;
} EFI_PSS_PACKAGE;
#pragma pack()
typedef struct {
UINT32 Index;
UINT64 Value;
} S3_CPU_REGISTER;
//
// Function prototypes
//
/**
This function is the entry of processor power management initialization code.
It initializes the processor's power management features based on the user
configurations and hardware capablities.
**/
VOID
PpmInit (
VOID
);
/**
This function is to determine the Processor Power Management Flags
based on the hardware capability.
**/
VOID
PpmDetectCapability (
VOID
);
/**
This function is to determine the user configuration mask
**/
VOID
PpmGetUserConfigurationMask (
VOID
);
/**
This function is to patch and publish power management related acpi tables.
**/
VOID
PpmPatchAndPublishAcpiTables (
VOID
);
/**
This function is to patch PLvl2Lat and PLvl3Lat to enable C2, C3 support in OS.
**/
VOID
PpmPatchFadtTable (
VOID
);
/**
This function is to load all the power management acpi tables and patch IST table.
**/
VOID
PpmLoadAndPatchPMTables (
VOID
);
/**
This function is to save cpu registers for s3 resume.
**/
VOID
PpmS3SaveRegisters (
VOID
);
#endif

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/** @file
This is QNC Smm Power Management driver
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "SmmPowerManagement.h"
//
// Global variables
//
EFI_SMM_CPU_PROTOCOL *mSmmCpu = NULL;
EFI_GLOBAL_NVS_AREA *mGlobalNvsAreaPtr = NULL;
EFI_MP_SERVICES_PROTOCOL *mMpService = NULL;
EFI_ACPI_SDT_PROTOCOL *mAcpiSdt = NULL;
EFI_ACPI_TABLE_PROTOCOL *mAcpiTable = NULL;
EFI_GUID mS3CpuRegisterTableGuid = S3_CPU_REGISTER_TABLE_GUID;
EFI_STATUS
EFIAPI
InitializePowerManagement (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
/*++
Routine Description:
Initializes the SMM Handler Driver
Arguments:
ImageHandle -
SystemTable -
Returns:
None
--*/
{
EFI_STATUS Status;
EFI_SMM_SW_DISPATCH2_PROTOCOL *SwDispatch;
EFI_GLOBAL_NVS_AREA_PROTOCOL *GlobalNvsAreaProtocol;
//
// Get SMM CPU protocol
//
Status = gSmst->SmmLocateProtocol (
&gEfiSmmCpuProtocolGuid,
NULL,
(VOID **)&mSmmCpu
);
ASSERT_EFI_ERROR (Status);
//
// Get the Sw dispatch protocol
//
Status = gSmst->SmmLocateProtocol (
&gEfiSmmSwDispatch2ProtocolGuid,
NULL,
(VOID**)&SwDispatch
);
ASSERT_EFI_ERROR (Status);
//
// Get Global NVS Area Protocol
//
Status = gBS->LocateProtocol (&gEfiGlobalNvsAreaProtocolGuid, NULL, (VOID **)&GlobalNvsAreaProtocol);
ASSERT_EFI_ERROR (Status);
mGlobalNvsAreaPtr = GlobalNvsAreaProtocol->Area;
//
// Locate and cache PI AcpiSdt Protocol.
//
Status = gBS->LocateProtocol (
&gEfiAcpiSdtProtocolGuid,
NULL,
(VOID **) &mAcpiSdt
);
ASSERT_EFI_ERROR (Status);
//
// Locate and cache PI AcpiSdt Protocol.
//
Status = gBS->LocateProtocol (
&gEfiAcpiTableProtocolGuid,
NULL,
(VOID **) &mAcpiTable
);
ASSERT_EFI_ERROR (Status);
//
// Get MpService protocol
//
Status = gBS->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID **)&mMpService);
ASSERT_EFI_ERROR (Status);
//
// Initialize power management features on processors
//
PpmInit();
return Status;
}

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/** @file
Header file for QNC Smm Power Management driver
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _SMM_POWER_MANAGEMENT_H_
#define _SMM_POWER_MANAGEMENT_H_
#include <PiSmm.h>
#include <IntelQNCDxe.h>
#include <Protocol/AcpiTable.h>
#include <Protocol/SmmCpu.h>
#include <Protocol/SmmSwDispatch2.h>
#include <Protocol/GlobalNvsArea.h>
#include <Protocol/AcpiSystemDescriptionTable.h>
#include <Protocol/FirmwareVolume2.h>
#include <Protocol/MpService.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Library/IoLib.h>
#include <Library/PciLib.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/SmmServicesTableLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/S3BootScriptLib.h>
#include <Library/MemoryAllocationLib.h>
#include <IndustryStandard/Acpi.h>
#include <AcpiCpuData.h>
#include "Ppm.h"
//
// Module global variable
//
extern EFI_SMM_CPU_PROTOCOL *mSmmCpu;
extern EFI_GLOBAL_NVS_AREA *mGlobalNvsAreaPtr;
extern EFI_MP_SERVICES_PROTOCOL *mMpService;
//
// Function prototypes
//
#endif

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QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/SmmPowerManagement.inf Normal file
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## @file
# Component description file for SMM Power Management module
#
# This is QNC Smm Power Management driver .
# Copyright (c) 2013-2015 Intel Corporation.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = SmmPowerManagement
FILE_GUID = 271F1343-20D6-4e14-9B62-3C0297F56F07
MODULE_TYPE = DXE_SMM_DRIVER
VERSION_STRING = 1.0
PI_SPECIFICATION_VERSION = 0x0001000A
ENTRY_POINT = InitializePowerManagement
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
#
[Sources]
SmmPowerManagement.c
SmmPowerManagement.h
Ppm.c
Ppm.h
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
UefiCpuPkg/UefiCpuPkg.dec
QuarkSocPkg/QuarkSocPkg.dec
QuarkPlatformPkg/QuarkPlatformPkg.dec
[LibraryClasses]
UefiDriverEntryPoint
DebugLib
PcdLib
IoLib
PciLib
BaseLib
BaseMemoryLib
SmmServicesTableLib
UefiBootServicesTableLib
S3BootScriptLib
MemoryAllocationLib
[Protocols]
gEfiSmmCpuProtocolGuid # PROTOCOL ALWAYS_CONSUMED
gEfiSmmSwDispatch2ProtocolGuid # PROTOCOL ALWAYS_CONSUMED
gEfiGlobalNvsAreaProtocolGuid # PROTOCOL ALWAYS_CONSUMED
gEfiFirmwareVolume2ProtocolGuid # PROTOCOL ALWAYS_CONSUMED
gEfiMpServiceProtocolGuid # PROTOCOL ALWAYS_CONSUMED
gEfiAcpiSdtProtocolGuid # PROTOCOL ALWAYS_CONSUMED
gEfiAcpiTableProtocolGuid # PROTOCOL ALWAYS_CONSUMED
[Guids]
gPowerManagementAcpiTableStorageGuid
[Pcd]
gEfiQuarkNcSocIdTokenSpaceGuid.PcdPmbaIoBaseAddress
gEfiQuarkNcSocIdTokenSpaceGuid.PcdPmbaIoLVL2
gQuarkPlatformTokenSpaceGuid.PcdPpmFlags
[Depex]
gEfiSmmCpuProtocolGuid AND
gEfiSmmSwDispatch2ProtocolGuid AND
gEfiGlobalNvsAreaProtocolGuid AND
gEfiAcpiTableProtocolGuid AND
gEfiMpServiceProtocolGuid