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QuarkPlatformPkg: Add new package for Galileo boards

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Changes for V4
==============
1) Move delete of QuarkSocPkg\QuarkNorthCluster\Binary\QuarkMicrocode
   from QuarkPlatformPkg commit to QuarkSocPkg commit
2) Fix incorrect license header in PlatformSecLibModStrs.uni

Changes for V3
==============
1) Set PcdResetOnMemoryTypeInformationChange FALSE in QuarkMin.dsc
   This is required because QuarkMin.dsc uses the emulated variable
   driver that does not preserve any non-volatile UEFI variables
   across reset.  If the condition is met where the memory type
   information variable needs to be updated, then the system will reset
   every time the UEFI Shell is run.  By setting this PCD to FALSE,
   then reset action is disabled.
2) Move one binary file to QuarkSocBinPkg
3) Change RMU.bin FILE statements to INF statement in DSC FD region
   to be compatible with PACKAGES_PATH search for QuarkSocBinPkg

Changes for V2
==============
1) Use new generic PCI serial driver PciSioSerialDxe in MdeModulePkg
2) Configure PcdPciSerialParameters for PCI serial driver for Quark
3) Use new MtrrLib API to reduce time to set MTRRs for all DRAM
4) Convert all UNI files to utf-8
5) Replace tabs with spaces and remove trailing spaces
6) Add License.txt

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19287 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Michael Kinney
2015-12-15 19:23:57 +00:00
committed by mdkinney
parent 9b6bbcdbfd
commit b303605e1b
190 changed files with 39436 additions and 0 deletions
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QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPciUpdate.c Normal file
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/** @file
Update the _PRT and _PRW method for pci devices
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _ACPI_PCI_UPDATE_H_
#define _ACPI_PCI_UPDATE_H_
//
// Primary OpCode
//
#define AML_ZERO_OP 0x00
#define AML_ONE_OP 0x01
#define AML_ALIAS_OP 0x06
#define AML_NAME_OP 0x08
#define AML_BYTE_PREFIX 0x0a
#define AML_WORD_PREFIX 0x0b
#define AML_DWORD_PREFIX 0x0c
#define AML_STRING_PREFIX 0x0d
#define AML_QWORD_PREFIX 0x0e
#define AML_SCOPE_OP 0x10
#define AML_BUFFER_OP 0x11
#define AML_PACKAGE_OP 0x12
#define AML_VAR_PACKAGE_OP 0x13
#define AML_METHOD_OP 0x14
#define AML_DUAL_NAME_PREFIX 0x2e
#define AML_MULTI_NAME_PREFIX 0x2f
#define AML_NAME_CHAR_A 0x41
#define AML_NAME_CHAR_B 0x42
#define AML_NAME_CHAR_C 0x43
#define AML_NAME_CHAR_D 0x44
#define AML_NAME_CHAR_E 0x45
#define AML_NAME_CHAR_F 0x46
#define AML_NAME_CHAR_G 0x47
#define AML_NAME_CHAR_H 0x48
#define AML_NAME_CHAR_I 0x49
#define AML_NAME_CHAR_J 0x4a
#define AML_NAME_CHAR_K 0x4b
#define AML_NAME_CHAR_L 0x4c
#define AML_NAME_CHAR_M 0x4d
#define AML_NAME_CHAR_N 0x4e
#define AML_NAME_CHAR_O 0x4f
#define AML_NAME_CHAR_P 0x50
#define AML_NAME_CHAR_Q 0x51
#define AML_NAME_CHAR_R 0x52
#define AML_NAME_CHAR_S 0x53
#define AML_NAME_CHAR_T 0x54
#define AML_NAME_CHAR_U 0x55
#define AML_NAME_CHAR_V 0x56
#define AML_NAME_CHAR_W 0x57
#define AML_NAME_CHAR_X 0x58
#define AML_NAME_CHAR_Y 0x59
#define AML_NAME_CHAR_Z 0x5a
#define AML_ROOT_CHAR 0x5c
#define AML_PARENT_PREFIX_CHAR 0x5e
#define AML_NAME_CHAR__ 0x5f
#define AML_LOCAL0 0x60
#define AML_LOCAL1 0x61
#define AML_LOCAL2 0x62
#define AML_LOCAL3 0x63
#define AML_LOCAL4 0x64
#define AML_LOCAL5 0x65
#define AML_LOCAL6 0x66
#define AML_LOCAL7 0x67
#define AML_ARG0 0x68
#define AML_ARG1 0x69
#define AML_ARG2 0x6a
#define AML_ARG3 0x6b
#define AML_ARG4 0x6c
#define AML_ARG5 0x6d
#define AML_ARG6 0x6e
#define AML_STORE_OP 0x70
#define AML_REF_OF_OP 0x71
#define AML_ADD_OP 0x72
#define AML_CONCAT_OP 0x73
#define AML_SUBTRACT_OP 0x74
#define AML_INCREMENT_OP 0x75
#define AML_DECREMENT_OP 0x76
#define AML_MULTIPLY_OP 0x77
#define AML_DIVIDE_OP 0x78
#define AML_SHIFT_LEFT_OP 0x79
#define AML_SHIFT_RIGHT_OP 0x7a
#define AML_AND_OP 0x7b
#define AML_NAND_OP 0x7c
#define AML_OR_OP 0x7d
#define AML_NOR_OP 0x7e
#define AML_XOR_OP 0x7f
#define AML_NOT_OP 0x80
#define AML_FIND_SET_LEFT_BIT_OP 0x81
#define AML_FIND_SET_RIGHT_BIT_OP 0x82
#define AML_DEREF_OF_OP 0x83
#define AML_CONCAT_RES_OP 0x84
#define AML_MOD_OP 0x85
#define AML_NOTIFY_OP 0x86
#define AML_SIZE_OF_OP 0x87
#define AML_INDEX_OP 0x88
#define AML_MATCH_OP 0x89
#define AML_CREATE_DWORD_FIELD_OP 0x8a
#define AML_CREATE_WORD_FIELD_OP 0x8b
#define AML_CREATE_BYTE_FIELD_OP 0x8c
#define AML_CREATE_BIT_FIELD_OP 0x8d
#define AML_OBJECT_TYPE_OP 0x8e
#define AML_CREATE_QWORD_FIELD_OP 0x8f
#define AML_LAND_OP 0x90
#define AML_LOR_OP 0x91
#define AML_LNOT_OP 0x92
#define AML_LEQUAL_OP 0x93
#define AML_LGREATER_OP 0x94
#define AML_LLESS_OP 0x95
#define AML_TO_BUFFER_OP 0x96
#define AML_TO_DEC_STRING_OP 0x97
#define AML_TO_HEX_STRING_OP 0x98
#define AML_TO_INTEGER_OP 0x99
#define AML_TO_STRING_OP 0x9c
#define AML_COPY_OBJECT_OP 0x9d
#define AML_MID_OP 0x9e
#define AML_CONTINUE_OP 0x9f
#define AML_IF_OP 0xa0
#define AML_ELSE_OP 0xa1
#define AML_WHILE_OP 0xa2
#define AML_NOOP_OP 0xa3
#define AML_RETURN_OP 0xa4
#define AML_BREAK_OP 0xa5
#define AML_BREAK_POINT_OP 0xcc
#define AML_ONES_OP 0xff
//
// Extended OpCode
//
#define AML_EXT_OP 0x5b
#define AML_EXT_MUTEX_OP 0x01
#define AML_EXT_EVENT_OP 0x02
#define AML_EXT_COND_REF_OF_OP 0x12
#define AML_EXT_CREATE_FIELD_OP 0x13
#define AML_EXT_LOAD_TABLE_OP 0x1f
#define AML_EXT_LOAD_OP 0x20
#define AML_EXT_STALL_OP 0x21
#define AML_EXT_SLEEP_OP 0x22
#define AML_EXT_ACQUIRE_OP 0x23
#define AML_EXT_SIGNAL_OP 0x24
#define AML_EXT_WAIT_OP 0x25
#define AML_EXT_RESET_OP 0x26
#define AML_EXT_RELEASE_OP 0x27
#define AML_EXT_FROM_BCD_OP 0x28
#define AML_EXT_TO_BCD_OP 0x29
#define AML_EXT_UNLOAD_OP 0x2a
#define AML_EXT_REVISION_OP 0x30
#define AML_EXT_DEBUG_OP 0x31
#define AML_EXT_FATAL_OP 0x32
#define AML_EXT_TIMER_OP 0x33
#define AML_EXT_REGION_OP 0x80
#define AML_EXT_FIELD_OP 0x81
#define AML_EXT_DEVICE_OP 0x82
#define AML_EXT_PROCESSOR_OP 0x83
#define AML_EXT_POWER_RES_OP 0x84
#define AML_EXT_THERMAL_ZONE_OP 0x85
#define AML_EXT_INDEX_FIELD_OP 0x86
#define AML_EXT_BANK_FIELD_OP 0x87
#define AML_EXT_DATA_REGION_OP 0x88
#pragma pack(1)
typedef struct {
UINT32 BridgeAddress;
UINT32 DeviceAddress;
UINT8 INTA[2]; // the first member record the 8259 link, the second member record the io apic irq number
UINT8 INTB[2];
UINT8 INTC[2];
UINT8 INTD[2];
UINT8 GPEPin;
UINT8 SxNum;
} PCI_DEVICE_INFO;
#pragma pack()
#define PCI_DEVICE_INFO_MAX_NUM 50
#define CURRENT_PCI_DEVICE_NUM 13
#define PIRQ_LINKA 1
#define PIRQ_LINKB 2
#define PIRQ_LINKC 3
#define PIRQ_LINKD 4
#define PIRQ_LINKE 5
#define PIRQ_LINKF 6
#define PIRQ_LINKG 7
#define PIRQ_LINKH 8
#define PIRQ_INVALID 0xFF
typedef struct _PCI_DEVICE_SETTING{
UINT8 PciDeviceInfoNumber;
PCI_DEVICE_INFO PciDeviceInfo[PCI_DEVICE_INFO_MAX_NUM];
}PCI_DEVICE_SETTING;
typedef struct _AML_BYTE_ENCODING AML_BYTE_ENCODING;
//
// AML Handle Entry definition.
//
// Signature must be set to EFI_AML_HANDLE_SIGNATURE or EFI_AML_ROOT_HANDLE_SIGNATURE
// Buffer is the ACPI node buffer pointer, the first/second bytes are opcode.
// This buffer should not be freed.
// Size is the total size of this ACPI node buffer.
//
typedef struct {
UINT32 Signature;
UINT8 *Buffer;
UINTN Size;
AML_BYTE_ENCODING *AmlByteEncoding;
BOOLEAN Modified;
} EFI_AML_HANDLE;
typedef UINT32 AML_OP_PARSE_INDEX;
typedef UINT32 AML_OP_PARSE_FORMAT;
typedef UINT32 AML_OP_ATTRIBUTE;
struct _AML_BYTE_ENCODING {
UINT8 OpCode;
UINT8 SubOpCode;
AML_OP_PARSE_INDEX MaxIndex;
AML_OP_PARSE_FORMAT Format[6];
AML_OP_ATTRIBUTE Attribute;
};
//
// Check device info fucntion prototype
//
typedef
BOOLEAN
(* CHECK_HANDLE_INFO) (
IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,
IN EFI_ACPI_HANDLE CheckHandle,
IN VOID *Context
);
extern EFI_ACPI_HANDLE mDsdtHandle;
extern EFI_ACPI_SDT_PROTOCOL *mAcpiSdt;
/**
Init Pci Device Structure
@param mConfigData - Pointer of Pci Device information Structure
**/
VOID
InitPciDeviceInfoStructure (
PCI_DEVICE_SETTING *mConfigData
);
/**
update pci routing information in acpi table based on pcd settings
@param AcpiSdt Pointer to Acpi SDT protocol
@param DsdtHandle ACPI root handle
@param PciDeviceInfo Pointer to PCI_DEVICE_INFO
**/
EFI_STATUS
SdtUpdatePciRouting (
IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,
IN EFI_ACPI_HANDLE DsdtHandle,
IN PCI_DEVICE_INFO *PciDeviceInfo
);
/**
update power resource wake up information in acpi table based on pcd settings
@param AcpiSdt Pointer to Acpi SDT protocol
@param DsdtHandle ACPI root handle
@param PciDeviceInfo Pointer to PCI_DEVICE_INFO
**/
EFI_STATUS
SdtUpdatePowerWake (
IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,
IN EFI_ACPI_HANDLE DsdtHandle,
IN PCI_DEVICE_INFO *PciDeviceInfo
);
/**
Get the root bridge handle by scanning the acpi table
@param AcpiSdt Pointer to Acpi SDT protocol
@param DsdtHandle ACPI root handle
@retval EFI_ACPI_HANDLE the handle of the root bridge
**/
EFI_ACPI_HANDLE
SdtGetRootBridgeHandle (
IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,
IN EFI_ACPI_HANDLE DsdtHandle
);
/**
Check input Pci device info is changed from the default values
@param PciDeviceInfo Pointer to PCI_DEVICE_INFO
@param UpdatePRT Pointer to BOOLEAN
@param UpdatePRW Pointer to BOOLEAN
**/
VOID
SdtCheckPciDeviceInfoChanged (
IN PCI_DEVICE_INFO *PciDeviceInfo,
IN BOOLEAN *UpdatePRT,
IN BOOLEAN *UpdatePRW
);
#endif

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/** @file
ACPI Platform Driver
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Protocol/AcpiTable.h>
#include <IndustryStandard/Pci22.h>
#include "AcpiPlatform.h"
//
// Global Variable
//
EFI_GLOBAL_NVS_AREA_PROTOCOL mGlobalNvsArea;
EFI_ACPI_SDT_PROTOCOL *mAcpiSdt;
EFI_ACPI_HANDLE mDsdtHandle = NULL;
EFI_STATUS
LocateSupportProtocol (
IN EFI_GUID *Protocol,
OUT VOID **Instance,
IN UINT32 Type
)
/*++
Routine Description:
Locate the first instance of a protocol. If the protocol requested is an
FV protocol, then it will return the first FV that contains the ACPI table
storage file.
Arguments:
Protocol The protocol to find.
Instance Return pointer to the first instance of the protocol
Returns:
EFI_SUCCESS The function completed successfully.
EFI_NOT_FOUND The protocol could not be located.
EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol.
--*/
{
EFI_STATUS Status;
EFI_HANDLE *HandleBuffer;
UINTN NumberOfHandles;
EFI_FV_FILETYPE FileType;
UINT32 FvStatus;
EFI_FV_FILE_ATTRIBUTES Attributes;
UINTN Size;
UINTN i;
FvStatus = 0;
//
// Locate protocol.
//
Status = gBS->LocateHandleBuffer (
ByProtocol,
Protocol,
NULL,
&NumberOfHandles,
&HandleBuffer
);
if (EFI_ERROR (Status)) {
//
// Defined errors at this time are not found and out of resources.
//
return Status;
}
//
// Looking for FV with ACPI storage file
//
for (i = 0; i < NumberOfHandles; i++) {
//
// Get the protocol on this handle
// This should not fail because of LocateHandleBuffer
//
Status = gBS->HandleProtocol (
HandleBuffer[i],
Protocol,
Instance
);
ASSERT_EFI_ERROR (Status);
if (!Type) {
//
// Not looking for the FV protocol, so find the first instance of the
// protocol. There should not be any errors because our handle buffer
// should always contain at least one or LocateHandleBuffer would have
// returned not found.
//
break;
}
//
// See if it has the ACPI storage file
//
Status = ((EFI_FIRMWARE_VOLUME2_PROTOCOL*) (*Instance))->ReadFile (*Instance,
(EFI_GUID*)PcdGetPtr (PcdAcpiTableStorageFile),
NULL,
&Size,
&FileType,
&Attributes,
&FvStatus
);
//
// If we found it, then we are done
//
if (Status == EFI_SUCCESS) {
break;
}
}
//
// Our exit status is determined by the success of the previous operations
// If the protocol was found, Instance already points to it.
//
//
// Free any allocated buffers
//
gBS->FreePool (HandleBuffer);
return Status;
}
VOID
DsdtTableUpdate (
IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader,
IN OUT EFI_ACPI_TABLE_VERSION *Version
)
/*++
Routine Description:
Update the DSDT table
Arguments:
Table - The table to be set
Version - Version to publish
Returns:
None
--*/
{
UINT8 *CurrPtr;
UINT8 *DsdtPointer;
UINT32 *Signature;
UINT8 *Operation;
UINT32 *Address;
UINT16 *Size;
//
// Loop through the ASL looking for values that we must fix up.
//
CurrPtr = (UINT8 *) TableHeader;
for (DsdtPointer = CurrPtr;
DsdtPointer <= (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length);
DsdtPointer++
)
{
Signature = (UINT32 *) DsdtPointer;
switch (*Signature) {
//
// MNVS operation region
//
case (SIGNATURE_32 ('M', 'N', 'V', 'S')):
//
// Conditional match. For Region Objects, the Operator will always be the
// byte immediately before the specific name. Therefore, subtract 1 to check
// the Operator.
//
Operation = DsdtPointer - 1;
if (*Operation == AML_OPREGION_OP) {
Address = (UINT32 *) (DsdtPointer + 6);
*Address = (UINT32) (UINTN) mGlobalNvsArea.Area;
Size = (UINT16 *) (DsdtPointer + 11);
*Size = sizeof (EFI_GLOBAL_NVS_AREA);
}
break;
//
// Update processor PBLK register I/O base address
//
case (SIGNATURE_32 ('P', 'R', 'I', 'O')):
//
// Conditional match. Update the following ASL code:
// Processor (CPU0, 0x01, 0x4F495250, 0x06) {}
// The 3rd parameter will be updated to the actual PBLK I/O base address.
// the Operator.
//
Operation = DsdtPointer - 8;
if ((*Operation == AML_EXT_OP) && (*(Operation + 1) == AML_EXT_PROCESSOR_OP)) {
*(UINT32 *)DsdtPointer = PcdGet16(PcdPmbaIoBaseAddress);
}
break;
default:
break;
}
}
}
VOID
ApicTableUpdate (
IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader,
IN OUT EFI_ACPI_TABLE_VERSION *Version
)
/*++
Routine Description:
Update the processors information in the APIC table
Arguments:
Table - The table to be set
Version - Version to publish
Returns:
None
--*/
{
EFI_STATUS Status;
EFI_MP_SERVICES_PROTOCOL *MpService;
UINT8 *CurrPtr;
UINT8 *EndPtr;
UINT8 CurrIoApic;
UINT8 CurrProcessor;
UINTN NumberOfCPUs;
UINTN NumberOfEnabledCPUs;
UINTN BufferSize;
EFI_PROCESSOR_INFORMATION MpContext;
ACPI_APIC_STRUCTURE_PTR *ApicPtr;
CurrIoApic = 0;
CurrProcessor = 0;
//
// Find the MP Protocol. This is an MP platform, so MP protocol must be
// there.
//
Status = gBS->LocateProtocol (
&gEfiMpServiceProtocolGuid,
NULL,
(VOID**)&MpService
);
if (EFI_ERROR (Status)) {
//
// Failed to get MP information, doesn't publish the invalid table
//
*Version = EFI_ACPI_TABLE_VERSION_NONE;
return;
}
//
// Determine the number of processors
//
MpService->GetNumberOfProcessors (
MpService,
&NumberOfCPUs,
&NumberOfEnabledCPUs
);
CurrPtr = (UINT8*) &(TableHeader[1]);
CurrPtr = CurrPtr + 8; // Size of Local APIC Address & Flag
EndPtr = (UINT8*) TableHeader;
EndPtr = EndPtr + TableHeader->Length;
while (CurrPtr < EndPtr) {
ApicPtr = (ACPI_APIC_STRUCTURE_PTR*) CurrPtr;
switch (ApicPtr->AcpiApicCommon.Type) {
case EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC:
BufferSize = sizeof (EFI_PROCESSOR_INFORMATION);
ApicPtr->AcpiLocalApic.Flags = 0;
ApicPtr->AcpiLocalApic.ApicId = 0;
Status = MpService->GetProcessorInfo (
MpService,
CurrProcessor,
&MpContext
);
if (!EFI_ERROR (Status)) {
if (MpContext.StatusFlag & PROCESSOR_ENABLED_BIT) {
ApicPtr->AcpiLocalApic.Flags = EFI_ACPI_3_0_LOCAL_APIC_ENABLED;
}
ApicPtr->AcpiLocalApic.ApicId = (UINT8)MpContext.ProcessorId;
}
CurrProcessor++;
break;
case EFI_ACPI_1_0_IO_APIC:
//
// IO APIC entries can be patched here
//
if (CurrIoApic == 0) {
//
// Update SOC internel IOAPIC base
//
ApicPtr->AcpiIoApic.IoApicId = PcdGet8 (PcdIoApicSettingIoApicId);
ApicPtr->AcpiIoApic.IoApicAddress = (UINT32)PcdGet64(PcdIoApicBaseAddress);
ApicPtr->AcpiIoApic.GlobalSystemInterruptBase = 0;
} else {
//
// Porting is required to update other IOAPIC entries if available
//
ASSERT (0);
}
CurrIoApic++;
break;
default:
break;
};
CurrPtr = CurrPtr + ApicPtr->AcpiApicCommon.Length;
}
}
VOID
AcpiUpdateTable (
IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader,
IN OUT EFI_ACPI_TABLE_VERSION *Version
)
/*++
Routine Description:
Set the correct table revision upon the setup value
Arguments:
Table - The table to be set
Version - Version to publish
Returns:
None
--*/
{
EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE *FadtHeader1;
EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *FadtHeader2;
EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *FadtHeader3;
EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE *AllocationStructurePtr;
if (TableHeader != NULL && Version != NULL) {
*Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0;
//
// Here we use all 3.0 signature because all version use same signature if they supported
//
switch (TableHeader->Signature) {
//
// "APIC" Multiple APIC Description Table
//
case EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE:
ApicTableUpdate (TableHeader, Version);
break;
//
// "DSDT" Differentiated System Description Table
//
case EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:
DsdtTableUpdate (TableHeader, Version);
break;
//
// "FACP" Fixed ACPI Description Table (FADT)
//
case EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE:
*Version = EFI_ACPI_TABLE_VERSION_NONE;
if (TableHeader->Revision == EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
*Version = EFI_ACPI_TABLE_VERSION_1_0B;
FadtHeader1 = (EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE *) TableHeader;
FadtHeader1->SmiCmd = PcdGet16(PcdSmmActivationPort);
FadtHeader1->Pm1aEvtBlk = PcdGet16(PcdPm1blkIoBaseAddress);
FadtHeader1->Pm1aCntBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C;
FadtHeader1->PmTmrBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1T;
FadtHeader1->Gpe0Blk = PcdGet16(PcdGpe0blkIoBaseAddress);
} else if (TableHeader->Revision == EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
*Version = EFI_ACPI_TABLE_VERSION_2_0;
FadtHeader2 = (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *) TableHeader;
FadtHeader2->SmiCmd = PcdGet16(PcdSmmActivationPort);
FadtHeader2->Pm1aEvtBlk = PcdGet16(PcdPm1blkIoBaseAddress);
FadtHeader2->Pm1aCntBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C;
FadtHeader2->PmTmrBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1T;
FadtHeader2->Gpe0Blk = PcdGet16(PcdGpe0blkIoBaseAddress);
FadtHeader2->XPm1aEvtBlk.Address = FadtHeader2->Pm1aEvtBlk;
FadtHeader2->XPm1aCntBlk.Address = FadtHeader2->Pm1aCntBlk;
FadtHeader2->XPmTmrBlk.Address = FadtHeader2->PmTmrBlk;
FadtHeader2->XGpe0Blk.Address = FadtHeader2->Gpe0Blk;
} else if (TableHeader->Revision == EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
*Version = EFI_ACPI_TABLE_VERSION_3_0;
FadtHeader3 = (EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *) TableHeader;
FadtHeader3->SmiCmd = PcdGet16(PcdSmmActivationPort);
FadtHeader3->Pm1aEvtBlk = PcdGet16(PcdPm1blkIoBaseAddress);
FadtHeader3->Pm1aCntBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C;
FadtHeader3->PmTmrBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1T;
FadtHeader3->Gpe0Blk = PcdGet16(PcdGpe0blkIoBaseAddress);
FadtHeader3->XPm1aEvtBlk.Address = FadtHeader3->Pm1aEvtBlk;
FadtHeader3->XPm1aCntBlk.Address = FadtHeader3->Pm1aCntBlk;
FadtHeader3->XPmTmrBlk.Address = FadtHeader3->PmTmrBlk;
FadtHeader3->XGpe0Blk.Address = FadtHeader3->Gpe0Blk;
}
break;
//
// "FACS" Firmware ACPI Control Structure
//
case EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE:
break;
//
// "SSDT" Secondary System Description Table
//
case EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:
break;
//
// "HPET" IA-PC High Precision Event Timer Table
//
case EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE:
//
// If HPET is disabled in setup, don't publish the table.
//
if (mGlobalNvsArea.Area->HpetEnable == 0) {
*Version = EFI_ACPI_TABLE_VERSION_NONE;
}
((EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER *) TableHeader)->BaseAddressLower32Bit.Address
= PcdGet64 (PcdHpetBaseAddress);
break;
//
// "SPCR" Serial Port Concole Redirection Table
//
case EFI_ACPI_3_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE:
break;
//
// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
//
case EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE:
AllocationStructurePtr = (EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE *)
((UINT8 *)TableHeader + sizeof(EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER));
AllocationStructurePtr->BaseAddress = PcdGet64(PcdPciExpressBaseAddress);
break;
// Lakeport platform doesn't support the following table
/*
//
// "ECDT" Embedded Controller Boot Resources Table
//
case EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE:
break;
//
// "PSDT" Persistent System Description Table
//
case EFI_ACPI_3_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:
break;
//
// "SBST" Smart Battery Specification Table
//
case EFI_ACPI_3_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE:
break;
//
// "SLIT" System Locality Information Table
//
case EFI_ACPI_3_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE:
break;
//
// "SRAT" Static Resource Affinity Table
//
case EFI_ACPI_3_0_STATIC_RESOURCE_AFFINITY_TABLE_SIGNATURE:
break;
//
// "XSDT" Extended System Description Table
//
case EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:
break;
//
// "BOOT" MS Simple Boot Spec
//
case EFI_ACPI_3_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE:
break;
//
// "CPEP" Corrected Platform Error Polling Table
//
case EFI_ACPI_3_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE:
break;
//
// "DBGP" MS Debug Port Spec
//
case EFI_ACPI_3_0_DEBUG_PORT_TABLE_SIGNATURE:
break;
//
// "ETDT" Event Timer Description Table
//
case EFI_ACPI_3_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE:
break;
//
// "SPMI" Server Platform Management Interface Table
//
case EFI_ACPI_3_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE:
break;
//
// "TCPA" Trusted Computing Platform Alliance Capabilities Table
//
case EFI_ACPI_3_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE:
break;
*/
default:
break;
}
}
}
//
// Description:
// Entrypoint of Acpi Platform driver
// In:
// ImageHandle
// SystemTable
// Out:
// EFI_SUCCESS
// EFI_LOAD_ERROR
// EFI_OUT_OF_RESOURCES
//
EFI_STATUS
AcpiPlatformEntryPoint (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
INTN Instance;
EFI_ACPI_COMMON_HEADER *CurrentTable;
UINTN TableHandle;
UINT32 FvStatus;
UINTN Size;
EFI_ACPI_TABLE_VERSION Version;
QNC_DEVICE_ENABLES QNCDeviceEnables;
EFI_HANDLE Handle;
UINTN Index;
PCI_DEVICE_INFO *PciDeviceInfo;
EFI_ACPI_HANDLE PciRootHandle;
BOOLEAN UpdatePRT;
BOOLEAN UpdatePRW;
PCI_DEVICE_SETTING *mConfigData;
DEBUG((DEBUG_INFO, "ACPI Platform start...\n"));
Instance = 0;
TableHandle = 0;
CurrentTable = NULL;
mConfigData = NULL;
QNCDeviceEnables.Uint32 = PcdGet32 (PcdDeviceEnables);
//
// Initialize the EFI Driver Library
//
ASSERT (sizeof (EFI_GLOBAL_NVS_AREA) == 512);
Status = gBS->AllocatePool (
EfiACPIMemoryNVS,
sizeof (EFI_GLOBAL_NVS_AREA),
(VOID**)&mGlobalNvsArea.Area
);
Handle = NULL;
Status = gBS->InstallProtocolInterface (
&Handle,
&gEfiGlobalNvsAreaProtocolGuid,
EFI_NATIVE_INTERFACE,
&mGlobalNvsArea
);
ASSERT_EFI_ERROR (Status);
if (!EFI_ERROR (Status)) {
SetMem (
mGlobalNvsArea.Area,
sizeof (EFI_GLOBAL_NVS_AREA),
0
);
}
//
// Initialize the data. Eventually, this will be controlled by setup options.
//
mGlobalNvsArea.Area->HpetEnable = PcdGetBool (PcdHpetEnable);
mGlobalNvsArea.Area->Pm1blkIoBaseAddress = PcdGet16(PcdPm1blkIoBaseAddress);
mGlobalNvsArea.Area->PmbaIoBaseAddress = PcdGet16(PcdPmbaIoBaseAddress);
mGlobalNvsArea.Area->Gpe0blkIoBaseAddress = PcdGet16(PcdGpe0blkIoBaseAddress);
mGlobalNvsArea.Area->GbaIoBaseAddress = PcdGet16(PcdGbaIoBaseAddress);
mGlobalNvsArea.Area->SmbaIoBaseAddress = PcdGet16(PcdSmbaIoBaseAddress);
mGlobalNvsArea.Area->WdtbaIoBaseAddress = PcdGet16(PcdWdtbaIoBaseAddress);
mGlobalNvsArea.Area->HpetBaseAddress = (UINT32)PcdGet64(PcdHpetBaseAddress);
mGlobalNvsArea.Area->HpetSize = (UINT32)PcdGet64(PcdHpetSize);
mGlobalNvsArea.Area->PciExpressBaseAddress= (UINT32)PcdGet64(PcdPciExpressBaseAddress);
mGlobalNvsArea.Area->PciExpressSize = (UINT32)PcdGet64(PcdPciExpressSize);
mGlobalNvsArea.Area->RcbaMmioBaseAddress = (UINT32)PcdGet64(PcdRcbaMmioBaseAddress);
mGlobalNvsArea.Area->RcbaMmioSize = (UINT32)PcdGet64(PcdRcbaMmioSize);
mGlobalNvsArea.Area->IoApicBaseAddress = (UINT32)PcdGet64(PcdIoApicBaseAddress);
mGlobalNvsArea.Area->IoApicSize = (UINT32)PcdGet64(PcdIoApicSize);
mGlobalNvsArea.Area->TpmPresent = (UINT32)(FALSE);
mGlobalNvsArea.Area->DBG2Present = (UINT32)(FALSE);
mGlobalNvsArea.Area->PlatformType = (UINT32)PcdGet16 (PcdPlatformType);
//
// Configure platform IO expander I2C Slave Address.
//
if (mGlobalNvsArea.Area->PlatformType == Galileo) {
if (PlatformLegacyGpioGetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO)) {
mGlobalNvsArea.Area->AlternateSla = FALSE;
} else {
mGlobalNvsArea.Area->AlternateSla = TRUE;
}
}
//
// Find the AcpiTable protocol
//
Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID**)&AcpiTable);
if (EFI_ERROR (Status)) {
return EFI_ABORTED;
}
//
// Initialize MADT table
//
Status = MadtTableInitialize (&CurrentTable, &Size);
ASSERT_EFI_ERROR (Status);
//
// Perform any table specific updates.
//
AcpiUpdateTable ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable, &Version);
//
// Update the check sum
// It needs to be zeroed before the checksum calculation
//
((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum = 0;
((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum =
CalculateCheckSum8 ((VOID *)CurrentTable, CurrentTable->Length);
//
// Add the table
//
TableHandle = 0;
Status = AcpiTable->InstallAcpiTable (
AcpiTable,
CurrentTable,
CurrentTable->Length,
&TableHandle
);
ASSERT_EFI_ERROR (Status);
CurrentTable = NULL;
//
// Init Pci Device PRT PRW information structure from PCD
//
mConfigData = (PCI_DEVICE_SETTING *)AllocateZeroPool (sizeof (PCI_DEVICE_SETTING));
ASSERT_EFI_ERROR (mConfigData);
InitPciDeviceInfoStructure (mConfigData);
//
// Get the Acpi SDT protocol for manipulation on acpi table
//
Status = gBS->LocateProtocol (&gEfiAcpiSdtProtocolGuid, NULL, (VOID **)&mAcpiSdt);
ASSERT_EFI_ERROR (Status);
//
// Locate the firmware volume protocol
//
Status = LocateSupportProtocol (&gEfiFirmwareVolume2ProtocolGuid, (VOID**)&FwVol, 1);
if (EFI_ERROR (Status)) {
return EFI_ABORTED;
}
//
// Read tables from the storage file.
//
while (Status == EFI_SUCCESS) {
Status = FwVol->ReadSection (
FwVol,
(EFI_GUID*)PcdGetPtr (PcdAcpiTableStorageFile),
EFI_SECTION_RAW,
Instance,
(VOID**)&CurrentTable,
&Size,
&FvStatus
);
if (!EFI_ERROR(Status)) {
//
// Perform any table specific updates.
//
AcpiUpdateTable ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable, &Version);
//
// Update the check sum
// It needs to be zeroed before the checksum calculation
//
((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum = 0;
((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum =
CalculateCheckSum8 ((VOID *)CurrentTable, CurrentTable->Length);
//
// Add the table
//
TableHandle = 0;
Status = AcpiTable->InstallAcpiTable (
AcpiTable,
CurrentTable,
((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable)->Length,
&TableHandle
);
if (EFI_ERROR(Status)) {
return EFI_ABORTED;
}
//
// If this table is the DSDT table, then update the _PRT and _PRW based on
// the settings from pcds
//
if (CurrentTable->Signature == EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) {
//
// Create the root handle for DSDT table
//
Status = mAcpiSdt->OpenSdt (TableHandle, &mDsdtHandle);
ASSERT_EFI_ERROR (Status);
PciRootHandle = NULL;
PciRootHandle = SdtGetRootBridgeHandle (mAcpiSdt, mDsdtHandle);
ASSERT (PciRootHandle != NULL);
PciDeviceInfo = NULL;
for (Index = 0; Index < mConfigData->PciDeviceInfoNumber; Index++) {
PciDeviceInfo = &(mConfigData->PciDeviceInfo[Index]);
//
// Check whether this is a valid item
//
if ((PciDeviceInfo->BridgeAddress != 0xFFFFFFFF) && (PciDeviceInfo->DeviceAddress != 0xFFFFFFFF)) {
//DEBUG ((EFI_D_ERROR, "Valid pci info structure: bridge address:0x%x, device address:0x%x\n", PciDeviceInfo->BridgeAddress, PciDeviceInfo->DeviceAddress));
UpdatePRT = FALSE;
UpdatePRW = FALSE;
SdtCheckPciDeviceInfoChanged (PciDeviceInfo, &UpdatePRT, &UpdatePRW);
//
// Check whether there is any valid pci routing item
//
if (UpdatePRT) {
//
// Update the pci routing information
//
//DEBUG ((EFI_D_ERROR, "Update _PRT\n"));
SdtUpdatePciRouting (mAcpiSdt, PciRootHandle, PciDeviceInfo);
}
//
// Check whether there is any valid pci routing item
//
if (UpdatePRW) {
//
// Update the pci wakeup information
//
//DEBUG ((EFI_D_ERROR, "Update _PRW\n"));
SdtUpdatePowerWake (mAcpiSdt, PciRootHandle, PciDeviceInfo);
}
}
}
Status = mAcpiSdt->Close (PciRootHandle);
ASSERT_EFI_ERROR (Status);
//
// Mark the root handle as modified , let SDT protocol recaculate the checksum
//
((EFI_AML_HANDLE *)mDsdtHandle)->Modified = TRUE;
Status = mAcpiSdt->Close (mDsdtHandle);
ASSERT_EFI_ERROR (Status);
}
//
// Increment the instance
//
Instance++;
CurrentTable = NULL;
}
}
gBS->FreePool (mConfigData);
return EFI_SUCCESS;
}

126
QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.h Normal file
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@@ -0,0 +1,126 @@
/** @file
This is an implementation of the ACPI platform driver. Requirements for
this driver are defined in the Tiano ACPI External Product Specification,
revision 0.3.6.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _ACPI_PLATFORM_H_
#define _ACPI_PLATFORM_H_
//
// Statements that include other header files
//
#include <PiDxe.h>
#include <IntelQNCDxe.h>
#include <Platform.h>
#include <PlatformBoards.h>
#include <Ioh.h>
#include <QNCCommonDefinitions.h>
#include <Protocol/GlobalNvsArea.h>
#include <Protocol/MpService.h>
#include <Protocol/AcpiSystemDescriptionTable.h>
#include <Protocol/FirmwareVolume2.h>
#include <Library/UefiDriverEntryPoint.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/UefiLib.h>
#include <Library/DxeServicesLib.h>
#include <Library/DevicePathLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/QNCAccessLib.h>
#include <Library/PlatformHelperLib.h>
#include <IndustryStandard/Acpi.h>
#include <IndustryStandard/HighPrecisionEventTimerTable.h>
#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
#include "Madt.h"
#include "AcpiPciUpdate.h"
#pragma pack(1)
typedef struct {
UINT8 StartByte;
UINT32 NameStr;
UINT8 OpCode;
UINT16 Size; // Hardcode to 16bit width because the table we use is fixed size
UINT8 NumEntries;
} EFI_ACPI_NAME_COMMAND;
typedef struct {
UINT8 PackageOp;
UINT8 PkgLeadByte;
UINT8 NumEntries;
UINT8 DwordPrefix0;
UINT32 CoreFreq;
UINT8 DwordPrefix1;
UINT32 Power;
UINT8 DwordPrefix2;
UINT32 TransLatency;
UINT8 DwordPrefix3;
UINT32 BMLatency;
UINT8 DwordPrefix4;
UINT32 Control;
UINT8 DwordPrefix5;
UINT32 Status;
} EFI_PSS_PACKAGE;
#pragma pack()
#define AML_NAME_OP 0x08
#define AML_METHOD_OP 0x14
#define AML_OPREGION_OP 0x80
#define AML_PACKAGE_OP 0x12 // Package operator.
//
// ACPI table information used to initialize tables.
//
#define EFI_ACPI_OEM_ID "INTEL "
#define EFI_ACPI_OEM_TABLE_ID 0x2020204F4E414954ULL // "TIANO "
#define EFI_ACPI_OEM_REVISION 0x00000002
#define EFI_ACPI_CREATOR_ID 0x5446534D // "MSFT"
#define EFI_ACPI_CREATOR_REVISION 0x01000013
#define ACPI_COMPATIBLE_1_0 0
#define ACPI_COMPATIBLE_2_0 1
#define ACPI_COMPATIBLE_3_0 2
//
// Private Driver Data
//
//
// Define Union of IO APIC & Local APIC structure;
//
typedef union {
EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE AcpiLocalApic;
EFI_ACPI_2_0_IO_APIC_STRUCTURE AcpiIoApic;
struct {
UINT8 Type;
UINT8 Length;
} AcpiApicCommon;
} ACPI_APIC_STRUCTURE_PTR;
#endif

202
QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.inf Normal file
View File

@@ -0,0 +1,202 @@
## @file
# Component description file for AcpiPlatform module.
#
# This is an implementation of the ACPI platform driver,
# whose requirements are from ACPI External Product Specification.
# Copyright (c) 2013-2015 Intel Corporation.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = AcpiPlatform
FILE_GUID = 368B3649-F204-4cd0-89A8-091077C070FA
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = AcpiPlatformEntryPoint
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
#
[Sources]
AcpiPlatform.c
AcpiPlatform.h
MadtPlatform.c
Madt.h
AcpiPciUpdate.c
AcpiPciUpdate.h
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
UefiCpuPkg/UefiCpuPkg.dec
QuarkSocPkg/QuarkSocPkg.dec
QuarkPlatformPkg/QuarkPlatformPkg.dec
[LibraryClasses]
UefiLib
DxeServicesLib
PcdLib
IoLib
BaseMemoryLib
DebugLib
UefiRuntimeServicesTableLib
UefiBootServicesTableLib
UefiDriverEntryPoint
DevicePathLib
PlatformHelperLib
[Protocols]
gEfiGlobalNvsAreaProtocolGuid # PROTOCOL ALWAYS_CONSUMED
gEfiMpServiceProtocolGuid # PROTOCOL SOMETIMES_CONSUMED
gEfiAcpiSdtProtocolGuid # PROTOCOL ALWAYS_CONSUMED
gEfiAcpiTableProtocolGuid # PROTOCOL ALWAYS_CONSUMED
[Pcd]
gQuarkPlatformTokenSpaceGuid.PcdPlatformType
gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14GlobalIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15Enable
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15SourceIrq
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15TrigerMode
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15GlobalIrq
gEfiQuarkNcSocIdTokenSpaceGuid.PcdIoApicBaseAddress
gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingIoApicAddress
gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingGlobalInterruptBase
gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingIoApicId
gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingNmiEnable
gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingNmiSource
gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingPolarity
gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingTrigerMode
gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingNmiEnabelApicIdMask
gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingAddressOverrideEnable
gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingPolarity
gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingTrigerMode
gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingLocalApicLint
gQuarkPlatformTokenSpaceGuid.PcdLocalApicAddressOverride
gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmmActivationPort
gEfiQuarkNcSocIdTokenSpaceGuid.PcdPm1blkIoBaseAddress
gEfiQuarkNcSocIdTokenSpaceGuid.PcdGpe0blkIoBaseAddress
gEfiQuarkNcSocIdTokenSpaceGuid.PcdPmbaIoBaseAddress
gEfiQuarkNcSocIdTokenSpaceGuid.PcdGbaIoBaseAddress
gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmbaIoBaseAddress
gEfiQuarkNcSocIdTokenSpaceGuid.PcdHpetBaseAddress
gEfiQuarkNcSocIdTokenSpaceGuid.PcdHpetSize
gEfiQuarkNcSocIdTokenSpaceGuid.PcdIoApicBaseAddress
gEfiQuarkNcSocIdTokenSpaceGuid.PcdIoApicSize
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciExpressSize
gEfiQuarkNcSocIdTokenSpaceGuid.PcdRcbaMmioBaseAddress
gEfiQuarkNcSocIdTokenSpaceGuid.PcdRcbaMmioSize
gEfiQuarkNcSocIdTokenSpaceGuid.PcdWdtbaIoBaseAddress
gQuarkPlatformTokenSpaceGuid.PcdHpetEnable
gEfiQuarkNcSocIdTokenSpaceGuid.PcdDeviceEnables
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile
[Depex]
gEfiMpServiceProtocolGuid AND gEfiAcpiTableProtocolGuid

213
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/** @file
This file describes the contents of the ACPI Multiple APIC Description
Table (MADT). Some additional ACPI values are defined in Acpi10.h and
Acpi20.h.
To make changes to the MADT, it is necessary to update the count for the
APIC structure being updated, and to modify table found in Madt.c.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _MADT_H
#define _MADT_H
//
// Statements that include other files
//
#include <IndustryStandard/Acpi.h>
#include <Library/PcdLib.h>
//
// MADT Definitions
//
#define EFI_ACPI_OEM_MADT_REVISION 0x00000001
//
// Local APIC address
//
#define EFI_ACPI_LOCAL_APIC_ADDRESS 0xFEE00000
//
// Multiple APIC Flags are defined in AcpiX.0.h
//
#define EFI_ACPI_1_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_1_0_PCAT_COMPAT)
#define EFI_ACPI_2_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_2_0_PCAT_COMPAT)
//
// Define the number of each table type.
// This is where the table layout is modified.
//
#define EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT 2
#define EFI_ACPI_IO_APIC_COUNT 1
#define EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT 2
#define EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT 0
#define EFI_ACPI_LOCAL_APIC_NMI_COUNT 2
#define EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT 0
#define EFI_ACPI_IO_SAPIC_COUNT 0
#define EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT 0
#define EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT 0
#define EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT_MAX 16
//
// MADT structure
//
//
// Ensure proper structure formats
//
#pragma pack (1)
//
// ACPI 1.0 Table structure
//
typedef struct {
EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0
EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT];
#endif
#if EFI_ACPI_IO_APIC_COUNT > 0
EFI_ACPI_1_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT];
#endif
#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0
EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];
#endif
#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0
EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT];
#endif
#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0
EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT];
#endif
#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0
EFI_ACPI_1_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_OVERRIDE_COUNT];
#endif
} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
//
// ACPI 2.0 Table structure
//
typedef struct {
EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0
EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT];
#endif
#if EFI_ACPI_IO_APIC_COUNT > 0
EFI_ACPI_2_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT];
#endif
#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0
EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];
#endif
#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0
EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT];
#endif
#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0
EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT];
#endif
#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0
EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT];
#endif
#if EFI_ACPI_IO_SAPIC_COUNT > 0
EFI_ACPI_2_0_IO_SAPIC_STRUCTURE IoSapic[EFI_ACPI_IO_SAPIC_COUNT];
#endif
#if EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT > 0
EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE LocalSapic[EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT];
#endif
#if EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT > 0
EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE PlatformInterruptSources[EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT];
#endif
} EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
#define _PcdIntSettingTblEnable(x) PcdGet8 (PcdInterruptOverrideSettingTable##x##Enable)
#define PcdIntSettingTblEnable(x) _PcdIntSettingTblEnable(x)
#define _PcdIntSettingTblSourceIrq(x) PcdGet8 (PcdInterruptOverrideSettingTable##x##Enable)
#define PcdIntSettingTblSourceIrq(x) _PcdIntSettingTblSourceIrq(x)
#define _PcdIntSettingTblPolarity(x) PcdGet8 (PcdInterruptOverrideSettingTable##x##Polarity)
#define PcdIntSettingTblPolarity(x) _PcdIntSettingTblPolarity(x)
#define _PcdIntSettingTableTrigerMode(x) PcdGet8 (PcdInterruptOverrideSettingTable##x##TrigerMode)
#define PcdIntSettingTableTrigerMode(x) _PcdIntSettingTableTrigerMode(x)
#define _PcdIntSettingTableGlobalIrq(x) PcdGet32 (PcdInterruptOverrideSettingTable##x##GlobalIrq)
#define PcdIntSettingTableGlobalIrq(x) _PcdIntSettingTableGlobalIrq(x)
typedef struct {
UINT8 Enable;
UINT8 SourceIrq;
UINT8 Polarity;
UINT8 TrigerMode;
UINT32 GlobalIrq;
} INTERRUPT_OVERRIDE_SETTING;
typedef struct {
UINT32 IoApicAddress;
UINT32 GlobalInterruptBase;
UINT8 IoApicId;
UINT8 NmiEnable;
UINT8 NmiSource;
UINT8 Polarity;
UINT8 TrigerMode;
} IO_APIC_SETTING;
typedef struct {
UINT8 NmiEnabelApicIdMask;
UINT8 AddressOverrideEnable;
UINT8 Polarity;
UINT8 TrigerMode;
UINT8 LocalApicLint;
UINT8 Reserve[3];
UINT32 LocalApicAddress;
UINT64 LocalApicAddressOverride;
} LOCAL_APIC_SETTING;
typedef struct _MADT_CONFIG_DATA {
INTERRUPT_OVERRIDE_SETTING MadtInterruptSetting[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT_MAX];
IO_APIC_SETTING MadtIoApicSetting;
LOCAL_APIC_SETTING MadtLocalApicSetting;
}MADT_CONFIG_DATA;
#pragma pack ()
EFI_STATUS
EFIAPI
MadtTableInitialize (
OUT EFI_ACPI_COMMON_HEADER **MadtTable,
OUT UINTN *Size
);
#endif

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/** @file
This file contains Madt Talbe initialized work.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//
// Statements that include other files
//
#include "AcpiPlatform.h"
VOID
InitMadtConfigData (MADT_CONFIG_DATA *mConfigData)
{
mConfigData->MadtInterruptSetting[0].Enable = PcdGet8 (PcdInterruptOverrideSettingTable0Enable);
mConfigData->MadtInterruptSetting[0].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable0SourceIrq);
mConfigData->MadtInterruptSetting[0].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable0Polarity);
mConfigData->MadtInterruptSetting[0].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable0TrigerMode);
mConfigData->MadtInterruptSetting[0].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable0GlobalIrq);
mConfigData->MadtInterruptSetting[1].Enable = PcdGet8 (PcdInterruptOverrideSettingTable1Enable);
mConfigData->MadtInterruptSetting[1].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable1SourceIrq);
mConfigData->MadtInterruptSetting[1].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable1Polarity);
mConfigData->MadtInterruptSetting[1].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable1TrigerMode);
mConfigData->MadtInterruptSetting[1].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable1GlobalIrq);
mConfigData->MadtInterruptSetting[2].Enable = PcdGet8 (PcdInterruptOverrideSettingTable2Enable);
mConfigData->MadtInterruptSetting[2].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable2SourceIrq);
mConfigData->MadtInterruptSetting[2].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable2Polarity);
mConfigData->MadtInterruptSetting[2].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable2TrigerMode);
mConfigData->MadtInterruptSetting[2].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable2GlobalIrq);
mConfigData->MadtInterruptSetting[3].Enable = PcdGet8 (PcdInterruptOverrideSettingTable3Enable);
mConfigData->MadtInterruptSetting[3].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable3SourceIrq);
mConfigData->MadtInterruptSetting[3].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable3Polarity);
mConfigData->MadtInterruptSetting[3].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable3TrigerMode);
mConfigData->MadtInterruptSetting[3].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable3GlobalIrq);
mConfigData->MadtInterruptSetting[4].Enable = PcdGet8 (PcdInterruptOverrideSettingTable4Enable);
mConfigData->MadtInterruptSetting[4].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable4SourceIrq);
mConfigData->MadtInterruptSetting[4].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable4Polarity);
mConfigData->MadtInterruptSetting[4].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable4TrigerMode);
mConfigData->MadtInterruptSetting[4].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable4GlobalIrq);
mConfigData->MadtInterruptSetting[5].Enable = PcdGet8 (PcdInterruptOverrideSettingTable5Enable);
mConfigData->MadtInterruptSetting[5].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable5SourceIrq);
mConfigData->MadtInterruptSetting[5].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable5Polarity);
mConfigData->MadtInterruptSetting[5].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable5TrigerMode);
mConfigData->MadtInterruptSetting[5].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable5GlobalIrq);
mConfigData->MadtInterruptSetting[6].Enable = PcdGet8 (PcdInterruptOverrideSettingTable6Enable);
mConfigData->MadtInterruptSetting[6].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable6SourceIrq);
mConfigData->MadtInterruptSetting[6].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable6Polarity);
mConfigData->MadtInterruptSetting[6].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable6TrigerMode);
mConfigData->MadtInterruptSetting[6].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable6GlobalIrq);
mConfigData->MadtInterruptSetting[7].Enable = PcdGet8 (PcdInterruptOverrideSettingTable7Enable);
mConfigData->MadtInterruptSetting[7].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable7SourceIrq);
mConfigData->MadtInterruptSetting[7].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable7Polarity);
mConfigData->MadtInterruptSetting[7].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable7TrigerMode);
mConfigData->MadtInterruptSetting[7].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable7GlobalIrq);
mConfigData->MadtInterruptSetting[8].Enable = PcdGet8 (PcdInterruptOverrideSettingTable8Enable);
mConfigData->MadtInterruptSetting[8].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable8SourceIrq);
mConfigData->MadtInterruptSetting[8].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable8Polarity);
mConfigData->MadtInterruptSetting[8].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable8TrigerMode);
mConfigData->MadtInterruptSetting[8].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable8GlobalIrq);
mConfigData->MadtInterruptSetting[9].Enable = PcdGet8 (PcdInterruptOverrideSettingTable9Enable);
mConfigData->MadtInterruptSetting[9].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable9SourceIrq);
mConfigData->MadtInterruptSetting[9].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable9Polarity);
mConfigData->MadtInterruptSetting[9].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable9TrigerMode);
mConfigData->MadtInterruptSetting[9].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable9GlobalIrq);
mConfigData->MadtInterruptSetting[10].Enable = PcdGet8 (PcdInterruptOverrideSettingTable10Enable);
mConfigData->MadtInterruptSetting[10].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable10SourceIrq);
mConfigData->MadtInterruptSetting[10].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable10Polarity);
mConfigData->MadtInterruptSetting[10].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable10TrigerMode);
mConfigData->MadtInterruptSetting[10].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable10GlobalIrq);
mConfigData->MadtInterruptSetting[11].Enable = PcdGet8 (PcdInterruptOverrideSettingTable11Enable);
mConfigData->MadtInterruptSetting[11].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable11SourceIrq);
mConfigData->MadtInterruptSetting[11].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable11Polarity);
mConfigData->MadtInterruptSetting[11].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable11TrigerMode);
mConfigData->MadtInterruptSetting[11].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable11GlobalIrq);
mConfigData->MadtInterruptSetting[12].Enable = PcdGet8 (PcdInterruptOverrideSettingTable12Enable);
mConfigData->MadtInterruptSetting[12].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable12SourceIrq);
mConfigData->MadtInterruptSetting[12].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable12Polarity);
mConfigData->MadtInterruptSetting[12].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable12TrigerMode);
mConfigData->MadtInterruptSetting[12].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable12GlobalIrq);
mConfigData->MadtInterruptSetting[13].Enable = PcdGet8 (PcdInterruptOverrideSettingTable13Enable);
mConfigData->MadtInterruptSetting[13].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable13SourceIrq);
mConfigData->MadtInterruptSetting[13].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable13Polarity);
mConfigData->MadtInterruptSetting[13].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable13TrigerMode);
mConfigData->MadtInterruptSetting[13].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable13GlobalIrq);
mConfigData->MadtInterruptSetting[14].Enable = PcdGet8 (PcdInterruptOverrideSettingTable14Enable);
mConfigData->MadtInterruptSetting[14].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable14SourceIrq);
mConfigData->MadtInterruptSetting[14].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable14Polarity);
mConfigData->MadtInterruptSetting[14].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable14TrigerMode);
mConfigData->MadtInterruptSetting[14].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable14GlobalIrq);
mConfigData->MadtInterruptSetting[15].Enable = PcdGet8 (PcdInterruptOverrideSettingTable15Enable);
mConfigData->MadtInterruptSetting[15].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable15SourceIrq);
mConfigData->MadtInterruptSetting[15].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable15Polarity);
mConfigData->MadtInterruptSetting[15].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable15TrigerMode);
mConfigData->MadtInterruptSetting[15].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable15GlobalIrq);
mConfigData->MadtIoApicSetting.IoApicAddress = (UINT32)PcdGet64(PcdIoApicBaseAddress);
mConfigData->MadtIoApicSetting.GlobalInterruptBase = PcdGet32 (PcdIoApicSettingGlobalInterruptBase);
mConfigData->MadtIoApicSetting.IoApicId = PcdGet8 (PcdIoApicSettingIoApicId);
mConfigData->MadtIoApicSetting.NmiEnable = PcdGet8 (PcdIoApicSettingNmiEnable);
mConfigData->MadtIoApicSetting.NmiSource = PcdGet8 (PcdIoApicSettingNmiSource);
mConfigData->MadtIoApicSetting.Polarity = PcdGet8 (PcdIoApicSettingPolarity);
mConfigData->MadtIoApicSetting.TrigerMode = PcdGet8 (PcdIoApicSettingTrigerMode);
mConfigData->MadtLocalApicSetting.NmiEnabelApicIdMask = PcdGet8 (PcdLocalApicSettingNmiEnabelApicIdMask);
mConfigData->MadtLocalApicSetting.AddressOverrideEnable = PcdGet8 (PcdLocalApicSettingAddressOverrideEnable);
mConfigData->MadtLocalApicSetting.Polarity = PcdGet8 (PcdLocalApicSettingPolarity);
mConfigData->MadtLocalApicSetting.TrigerMode = PcdGet8 (PcdLocalApicSettingTrigerMode);
mConfigData->MadtLocalApicSetting.LocalApicLint = PcdGet8 (PcdLocalApicSettingLocalApicLint);
mConfigData->MadtLocalApicSetting.LocalApicAddressOverride = PcdGet64 (PcdLocalApicAddressOverride);
mConfigData->MadtLocalApicSetting.LocalApicAddress = PcdGet32 (PcdCpuLocalApicBaseAddress);
}
UINT32
GetAcutalMadtTableSize (
IN MADT_CONFIG_DATA * MadtConfigData,
IN INTN NumberOfCPUs
)
{
UINT32 MadtSize;
UINT8 Index;
MadtSize = (UINT32)(sizeof (EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER) +
sizeof (EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE) * NumberOfCPUs +
sizeof (EFI_ACPI_2_0_IO_APIC_STRUCTURE) +
sizeof (EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE) * (MadtConfigData->MadtLocalApicSetting.AddressOverrideEnable != 0?1:0)
);
for (Index = 0; Index < EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT_MAX; Index ++ ) {
if (MadtConfigData->MadtInterruptSetting[Index].Enable != 0) {
MadtSize += sizeof (EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE);
}
}
for (Index = 0; Index < NumberOfCPUs; Index ++ ) {
if (0 != (MadtConfigData->MadtLocalApicSetting.NmiEnabelApicIdMask & (1 << Index))) {
MadtSize += sizeof (EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE);
}
}
if (0 != MadtConfigData->MadtIoApicSetting.NmiEnable) {
MadtSize += sizeof (EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE);
}
return MadtSize;
}
//
// Init Multiple APIC Description Table
//
EFI_STATUS
MadtTableInitialize (
OUT EFI_ACPI_COMMON_HEADER **MadtTable,
OUT UINTN *Size
)
{
EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *Madt;
EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE *ProcLocalApic;
EFI_ACPI_2_0_IO_APIC_STRUCTURE *IoApic;
EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE *InterruptSourceOverride;
EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE *IoApicNmiSource;
EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE *LocalApicNmiSource;
EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE *LocalApicAddressOverride;
EFI_MP_SERVICES_PROTOCOL *MpService;
UINTN NumberOfCPUs;
UINTN NumberOfEnabledCPUs;
MADT_CONFIG_DATA MadtConfigData;
UINT32 MadtSize;
UINTN Index;
EFI_STATUS Status;
ASSERT (NULL != MadtTable);
ASSERT (NULL != Size);
//
// Init Madt table data
//
InitMadtConfigData (&MadtConfigData);
//
// Find the MP Protocol. This is an MP platform, so MP protocol must be
// there.
//
Status = gBS->LocateProtocol (
&gEfiMpServiceProtocolGuid,
NULL,
(VOID **)&MpService
);
ASSERT_EFI_ERROR (Status);
//
// Determine the number of processors
//
MpService->GetNumberOfProcessors (
MpService,
&NumberOfCPUs,
&NumberOfEnabledCPUs
);
//ASSERT (NumberOfCPUs <= 2 && NumberOfCPUs > 0);
MadtSize = GetAcutalMadtTableSize (&MadtConfigData, NumberOfCPUs);
Madt = (EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *)AllocateZeroPool (MadtSize);
ASSERT_EFI_ERROR (Madt);
//
// Initialize MADT Header information
//
Madt->Header.Signature = EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE;
Madt->Header.Length = MadtSize;
Madt->Header.Revision = EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION;
Madt->Header.OemTableId = EFI_ACPI_OEM_TABLE_ID;
Madt->Header.OemRevision = EFI_ACPI_OEM_MADT_REVISION;
Madt->Header.CreatorId = EFI_ACPI_CREATOR_ID;
Madt->LocalApicAddress = MadtConfigData.MadtLocalApicSetting.LocalApicAddress;
Madt->Flags = EFI_ACPI_2_0_MULTIPLE_APIC_FLAGS;
CopyMem (Madt->Header.OemId, EFI_ACPI_OEM_ID, 6);
ProcLocalApic = (EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE *) (Madt + 1);
//
// Initialization of Processor's local APICs
//
for (Index = 0;Index < NumberOfCPUs; Index++) {
ProcLocalApic[Index].Type = EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC;
ProcLocalApic[Index].Length = sizeof (EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE);
ProcLocalApic[Index].AcpiProcessorId = (UINT8)(Index + 1);
ProcLocalApic[Index].ApicId = 0xff;
ProcLocalApic[Index].Flags = 0;
}
//
// Initialization of IO APIC.
// Note: Here assumes that there must be one and only one IO APIC in platform.
//
IoApic = (EFI_ACPI_2_0_IO_APIC_STRUCTURE *) (&ProcLocalApic[Index]);
IoApic->Type = EFI_ACPI_2_0_IO_APIC;
IoApic->Length = sizeof (EFI_ACPI_2_0_IO_APIC_STRUCTURE);
IoApic->IoApicId = MadtConfigData.MadtIoApicSetting.IoApicId;
IoApic->IoApicAddress = MadtConfigData.MadtIoApicSetting.IoApicAddress;
IoApic->GlobalSystemInterruptBase = MadtConfigData.MadtIoApicSetting.GlobalInterruptBase;
InterruptSourceOverride = (EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE *) (IoApic + 1);
for (Index = 0;Index < EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT_MAX; Index++ ){
if (MadtConfigData.MadtInterruptSetting[Index].Enable) {
InterruptSourceOverride->Type = EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE;
InterruptSourceOverride->Length = sizeof (EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE);
InterruptSourceOverride->Bus = 0;
InterruptSourceOverride->Source = MadtConfigData.MadtInterruptSetting[Index].SourceIrq;
InterruptSourceOverride->Flags = ((MadtConfigData.MadtInterruptSetting[Index].TrigerMode & 0x03) << 2) | (MadtConfigData.MadtInterruptSetting[Index].Polarity & 0x03);
InterruptSourceOverride->GlobalSystemInterrupt = MadtConfigData.MadtInterruptSetting[Index].GlobalIrq;
InterruptSourceOverride++;
}
}
//
// support NMI source configuration.
//
IoApicNmiSource = (EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE *) InterruptSourceOverride;
if ((BOOLEAN) MadtConfigData.MadtIoApicSetting.NmiEnable) {
IoApicNmiSource->Type = EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE;
IoApicNmiSource->Length = sizeof (EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE);
IoApicNmiSource->Flags = ((MadtConfigData.MadtIoApicSetting.TrigerMode & 0x03) << 2) | (MadtConfigData.MadtIoApicSetting.Polarity & 0x03);
IoApicNmiSource->GlobalSystemInterrupt = MadtConfigData.MadtIoApicSetting.NmiSource;
IoApicNmiSource ++;
}
//
// Assume each processor has same NMI interrupt source.
//
LocalApicNmiSource = (EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE *) IoApicNmiSource;
for (Index = 0;Index < NumberOfCPUs; Index++) {
if (0 != (MadtConfigData.MadtLocalApicSetting.NmiEnabelApicIdMask & (1 << Index))){
LocalApicNmiSource->Type = EFI_ACPI_2_0_LOCAL_APIC_NMI;
LocalApicNmiSource->Length = sizeof (EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE);
LocalApicNmiSource->LocalApicLint = MadtConfigData.MadtLocalApicSetting.LocalApicLint;
LocalApicNmiSource->Flags = ((MadtConfigData.MadtLocalApicSetting.TrigerMode & 0x03) << 2) | (MadtConfigData.MadtLocalApicSetting.Polarity & 0x03);
LocalApicNmiSource->AcpiProcessorId = (UINT8)(Index + 1);
LocalApicNmiSource++;
}
}
LocalApicAddressOverride = (EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE *) LocalApicNmiSource;
if ((BOOLEAN) MadtConfigData.MadtLocalApicSetting.AddressOverrideEnable) {
LocalApicAddressOverride->Type = EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE;
LocalApicAddressOverride->Length = sizeof (EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE);
LocalApicAddressOverride->LocalApicAddress = MadtConfigData.MadtLocalApicSetting.LocalApicAddressOverride;
LocalApicAddressOverride++;
}
*Size = MadtSize;
*MadtTable = (EFI_ACPI_COMMON_HEADER *) Madt;
return EFI_SUCCESS;
}

83
QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/BootScriptExecutorDxe.inf Normal file
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## @file
# Boot Script Executor Module
#
# This is a standalone Boot Script Executor. Standalone means it does not
# depends on any PEI or DXE service.
#
# Copyright (c) 2013-2015 Intel Corporation.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BootScriptExecutorDxe
FILE_GUID = FA20568B-548B-4b2b-81EF-1BA08D4A3CEC
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = BootScriptExecutorEntryPoint
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64
#
[Sources]
ScriptExecute.h
ScriptExecute.c
[Sources.Ia32]
IA32/SetIdtEntry.c
IA32/S3Asm.asm
IA32/S3Asm.S
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
QuarkPlatformPkg/QuarkPlatformPkg.dec
QuarkSocPkg/QuarkSocPkg.dec
[LibraryClasses]
TimerLib
PcdLib
BaseMemoryLib
SmbusLib
UefiDriverEntryPoint
BaseLib
PciLib
IoLib
S3BootScriptLib
PeCoffLib
DxeServicesLib
UefiBootServicesTableLib
UefiRuntimeServicesTableLib
CacheMaintenanceLib
UefiLib
DebugAgentLib
LockBoxLib
IntelQNCLib
QNCAccessLib
[Guids]
gEfiBootScriptExecutorVariableGuid
gEfiBootScriptExecutorContextGuid
gPerformanceProtocolGuid
gEfiEventExitBootServicesGuid
[FeaturePcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable
[Depex]
gEfiLockBoxProtocolGuid

50
QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/IA32/S3Asm.S Normal file
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## @file
#
# Copyright (c) 2013-2015 Intel Corporation.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#-----------------------------------------
#VOID
#AsmTransferControl (
# IN UINT32 S3WakingVector,
# IN UINT32 AcpiLowMemoryBase
# );
#-----------------------------------------
ASM_GLOBAL ASM_PFX(AsmTransferControl)
ASM_PFX(AsmTransferControl):
# S3WakingVector :DWORD
# AcpiLowMemoryBase :DWORD
pushl %ebp
movl %esp,%ebp
leal LABLE, %eax
pushl $0x28 # CS
pushl %eax
movl 8(%ebp),%ecx
shrdl $20,%ecx,%ebx
andl $0xf,%ecx
movw %cx,%bx
movl %ebx, jmp_addr
lret
LABLE:
.byte 0xb8,0x30,0 # mov ax, 30h as selector
movw %ax,%ds
movw %ax,%es
movw %ax,%fs
movw %ax,%gs
movw %ax,%ss
movl %cr0, %eax # Get control register 0
.byte 0x66
.byte 0x83,0xe0,0xfe # and eax, 0fffffffeh ; Clear PE bit (bit #0)
.byte 0xf,0x22,0xc0 # mov cr0, eax ; Activate real mode
.byte 0xea # jmp far @jmp_addr
jmp_addr:
.long 0

57
QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/IA32/S3Asm.asm Normal file
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;; @file
; This is the assembly code for transferring to control to OS S3 waking vector
; for IA32 platform
;
; Copyright (c) 2013-2015 Intel Corporation.
;
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
.586P
.model flat,C
.code
;-----------------------------------------
;VOID
;AsmTransferControl (
; IN UINT32 S3WakingVector,
; IN UINT32 AcpiLowMemoryBase
; );
;-----------------------------------------
AsmTransferControl PROC
; S3WakingVector :DWORD
; AcpiLowMemoryBase :DWORD
push ebp
mov ebp, esp
lea eax, @F
push 28h ; CS
push eax
mov ecx, [ebp + 8]
shrd ebx, ecx, 20
and ecx, 0fh
mov bx, cx
mov @jmp_addr, ebx
retf
@@:
DB 0b8h, 30h, 0 ; mov ax, 30h as selector
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
mov ss, ax
mov eax, cr0 ; Get control register 0
DB 66h
DB 83h, 0e0h, 0feh ; and eax, 0fffffffeh ; Clear PE bit (bit #0)
DB 0fh, 22h, 0c0h ; mov cr0, eax ; Activate real mode
DB 0eah ; jmp far @jmp_addr
@jmp_addr DD ?
AsmTransferControl ENDP
END

63
QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/IA32/SetIdtEntry.c Normal file
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/** @file
Set a IDT entry for debug purpose
Set a IDT entry for interrupt vector 3 for debug purpose for IA32 platform
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "ScriptExecute.h"
//
// INTERRUPT_GATE_DESCRIPTOR and SetIdtEntry () are used to setup IDT to do debug
//
#pragma pack(1)
typedef struct {
UINT16 OffsetLow;
UINT16 SegmentSelector;
UINT16 Attributes;
UINT16 OffsetHigh;
} INTERRUPT_GATE_DESCRIPTOR;
#define INTERRUPT_GATE_ATTRIBUTE 0x8e00
#pragma pack()
/**
Set a IDT entry for interrupt vector 3 for debug purpose.
@param AcpiS3Context a pointer to a structure of ACPI_S3_CONTEXT
**/
VOID
SetIdtEntry (
IN ACPI_S3_CONTEXT *AcpiS3Context
)
{
INTERRUPT_GATE_DESCRIPTOR *IdtEntry;
IA32_DESCRIPTOR *IdtDescriptor;
UINTN S3DebugBuffer;
//
// Restore IDT for debug
//
IdtDescriptor = (IA32_DESCRIPTOR *) (UINTN) (AcpiS3Context->IdtrProfile);
IdtEntry = (INTERRUPT_GATE_DESCRIPTOR *)(IdtDescriptor->Base + (3 * sizeof (INTERRUPT_GATE_DESCRIPTOR)));
S3DebugBuffer = (UINTN) (AcpiS3Context->S3DebugBufferAddress);
IdtEntry->OffsetLow = (UINT16)S3DebugBuffer;
IdtEntry->SegmentSelector = (UINT16)AsmReadCs ();
IdtEntry->Attributes = (UINT16)INTERRUPT_GATE_ATTRIBUTE;
IdtEntry->OffsetHigh = (UINT16)(S3DebugBuffer >> 16);
AsmWriteIdtr (IdtDescriptor);
}

385
QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/ScriptExecute.c Normal file
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/** @file
This is the code for Boot Script Executer module.
This driver is dispatched by Dxe core and the driver will reload itself to ACPI NVS memory
in the entry point. The functionality is to interpret and restore the S3 boot script
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "ScriptExecute.h"
#pragma pack(1)
typedef union {
struct {
UINT32 LimitLow : 16;
UINT32 BaseLow : 16;
UINT32 BaseMid : 8;
UINT32 Type : 4;
UINT32 System : 1;
UINT32 Dpl : 2;
UINT32 Present : 1;
UINT32 LimitHigh : 4;
UINT32 Software : 1;
UINT32 Reserved : 1;
UINT32 DefaultSize : 1;
UINT32 Granularity : 1;
UINT32 BaseHigh : 8;
} Bits;
UINT64 Uint64;
} IA32_GDT;
#pragma pack()
EFI_GUID mBootScriptExecutorImageGuid = {
0x9a8d3433, 0x9fe8, 0x42b6, {0x87, 0xb, 0x1e, 0x31, 0xc8, 0x4e, 0xbe, 0x3b}
};
//
// Global Descriptor Table (GDT)
//
GLOBAL_REMOVE_IF_UNREFERENCED IA32_GDT mGdtEntries[] = {
/* selector { Global Segment Descriptor } */
/* 0x00 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
/* 0x08 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
/* 0x10 */ {{0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 0, 1, 1, 0}},
/* 0x18 */ {{0xFFFF, 0, 0, 0x3, 1, 0, 1, 0xF, 0, 0, 1, 1, 0}},
/* 0x20 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
/* 0x28 */ {{0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 0, 0, 1, 0}},
/* 0x30 */ {{0xFFFF, 0, 0, 0x3, 1, 0, 1, 0xF, 0, 0, 0, 1, 0}},
/* 0x38 */ {{0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 1, 0, 1, 0}},
/* 0x40 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
};
//
// IA32 Gdt register
//
GLOBAL_REMOVE_IF_UNREFERENCED CONST IA32_DESCRIPTOR mGdt = {
sizeof (mGdtEntries) - 1,
(UINTN) mGdtEntries
};
/**
Entry function of Boot script exector. This function will be executed in
S3 boot path.
This function should not return, because it is invoked by switch stack.
@param AcpiS3Context a pointer to a structure of ACPI_S3_CONTEXT
@param PeiS3ResumeState a pointer to a structure of PEI_S3_RESUME_STATE
@retval EFI_INVALID_PARAMETER - OS waking vector not found
@retval EFI_UNSUPPORTED - something wrong when we resume to OS
**/
EFI_STATUS
EFIAPI
S3BootScriptExecutorEntryFunction (
IN ACPI_S3_CONTEXT *AcpiS3Context,
IN PEI_S3_RESUME_STATE *PeiS3ResumeState
)
{
EFI_STATUS Status;
//
// Disable interrupt of Debug timer, since new IDT table cannot handle it.
//
SaveAndSetDebugTimerInterrupt (FALSE);
//
// Restore IDT for debug
//
SetIdtEntry (AcpiS3Context);
//
// Initialize Debug Agent to support source level debug in S3 path.
//
InitializeDebugAgent (DEBUG_AGENT_INIT_S3, NULL, NULL);
//
// Because not install BootScriptExecute PPI(used just in this module), So just pass NULL
// for that parameter.
//
Status = S3BootScriptExecute ();
AsmWbinvd ();
//
// We need turn back to S3Resume - install boot script done ppi and report status code on S3resume.
//
if (PeiS3ResumeState != 0) {
//
// Need report status back to S3ResumePeim.
// If boot script execution is failed, S3ResumePeim wil report the error status code.
//
PeiS3ResumeState->ReturnStatus = (UINT64)(UINTN)Status;
//
// IA32 S3 Resume
//
DEBUG ((EFI_D_INFO, "Call SwitchStack() to return to S3 Resume in PEI Phase\n"));
PeiS3ResumeState->AsmTransferControl = (EFI_PHYSICAL_ADDRESS)(UINTN)PlatformTransferControl16;
SwitchStack (
(SWITCH_STACK_ENTRY_POINT)(UINTN)PeiS3ResumeState->ReturnEntryPoint,
(VOID *)(UINTN)AcpiS3Context,
(VOID *)(UINTN)PeiS3ResumeState,
(VOID *)(UINTN)PeiS3ResumeState->ReturnStackPointer
);
//
// Never run to here
//
CpuDeadLoop();
return EFI_UNSUPPORTED;
}
//
// Never run to here
//
CpuDeadLoop();
return EFI_UNSUPPORTED;
}
/**
Entrypoint of Boot script exector driver, this function will be executed in
normal boot phase and invoked by DXE dispatch.
@param[in] ImageHandle The firmware allocated handle for the EFI image.
@param[in] SystemTable A pointer to the EFI System Table.
@retval EFI_SUCCESS The entry point is executed successfully.
@retval other Some error occurs when executing this entry point.
**/
EFI_STATUS
EFIAPI
BootScriptExecutorEntryPoint (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
UINT8 *Buffer;
UINTN BufferSize;
UINTN Pages;
EFI_PHYSICAL_ADDRESS FfsBuffer;
PE_COFF_LOADER_IMAGE_CONTEXT ImageContext;
BOOT_SCRIPT_EXECUTOR_VARIABLE *EfiBootScriptExecutorVariable;
EFI_PHYSICAL_ADDRESS BootScriptExecutorBuffer;
EFI_STATUS Status;
VOID *DevicePath;
EFI_HANDLE NewImageHandle;
//
// Test if the gEfiCallerIdGuid of this image is already installed. if not, the entry
// point is loaded by DXE code which is the first time loaded. or else, it is already
// be reloaded be itself.This is a work-around
//
Status = gBS->LocateProtocol (&gEfiCallerIdGuid, NULL, &DevicePath);
if (EFI_ERROR (Status)) {
//
// This is the first-time loaded by DXE core. reload itself to NVS mem
//
//
// A workarouond: Here we install a dummy handle
//
NewImageHandle = NULL;
Status = gBS->InstallProtocolInterface (
&NewImageHandle,
&gEfiCallerIdGuid,
EFI_NATIVE_INTERFACE,
NULL
);
Status = GetSectionFromAnyFv (
&gEfiCallerIdGuid,
EFI_SECTION_PE32,
0,
(VOID **) &Buffer,
&BufferSize
);
ImageContext.Handle = Buffer;
ImageContext.ImageRead = PeCoffLoaderImageReadFromMemory;
//
// Get information about the image being loaded
//
Status = PeCoffLoaderGetImageInfo (&ImageContext);
if (EFI_ERROR (Status)) {
return Status;
}
Pages = EFI_SIZE_TO_PAGES(BufferSize + ImageContext.SectionAlignment);
FfsBuffer = 0xFFFFFFFF;
Status = gBS->AllocatePages (
AllocateMaxAddress,
EfiACPIMemoryNVS,
Pages,
&FfsBuffer
);
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
ImageContext.ImageAddress = (PHYSICAL_ADDRESS)(UINTN)FfsBuffer;
//
// Align buffer on section boundry
//
ImageContext.ImageAddress += ImageContext.SectionAlignment - 1;
ImageContext.ImageAddress &= ~(ImageContext.SectionAlignment - 1);
//
// Load the image to our new buffer
//
Status = PeCoffLoaderLoadImage (&ImageContext);
if (EFI_ERROR (Status)) {
gBS->FreePages (FfsBuffer, Pages);
return Status;
}
//
// Relocate the image in our new buffer
//
Status = PeCoffLoaderRelocateImage (&ImageContext);
if (EFI_ERROR (Status)) {
PeCoffLoaderUnloadImage (&ImageContext);
gBS->FreePages (FfsBuffer, Pages);
return Status;
}
//
// Flush the instruction cache so the image data is written before we execute it
//
InvalidateInstructionCacheRange ((VOID *)(UINTN)ImageContext.ImageAddress, (UINTN)ImageContext.ImageSize);
Status = ((EFI_IMAGE_ENTRY_POINT)(UINTN)(ImageContext.EntryPoint)) (NewImageHandle, SystemTable);
if (EFI_ERROR (Status)) {
gBS->FreePages (FfsBuffer, Pages);
return Status;
}
//
// Additional step for BootScript integrity
// Save BootScriptExecutor image
//
Status = SaveLockBox (
&mBootScriptExecutorImageGuid,
(VOID *)(UINTN)ImageContext.ImageAddress,
(UINTN)ImageContext.ImageSize
);
ASSERT_EFI_ERROR (Status);
Status = SetLockBoxAttributes (&mBootScriptExecutorImageGuid, LOCK_BOX_ATTRIBUTE_RESTORE_IN_PLACE);
ASSERT_EFI_ERROR (Status);
} else {
//
// the entry point is invoked after reloading. following code only run in ACPI NVS
//
BufferSize = sizeof (BOOT_SCRIPT_EXECUTOR_VARIABLE);
BootScriptExecutorBuffer = 0xFFFFFFFF;
Pages = EFI_SIZE_TO_PAGES(BufferSize);
Status = gBS->AllocatePages (
AllocateMaxAddress,
EfiACPIMemoryNVS,
Pages,
&BootScriptExecutorBuffer
);
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
EfiBootScriptExecutorVariable = (BOOT_SCRIPT_EXECUTOR_VARIABLE *)(UINTN)BootScriptExecutorBuffer;
EfiBootScriptExecutorVariable->BootScriptExecutorEntrypoint = (UINTN) S3BootScriptExecutorEntryFunction ;
Status = SaveLockBox (
&gEfiBootScriptExecutorVariableGuid,
&BootScriptExecutorBuffer,
sizeof(BootScriptExecutorBuffer)
);
ASSERT_EFI_ERROR (Status);
//
// Additional step for BootScript integrity
// Save BootScriptExecutor context
//
Status = SaveLockBox (
&gEfiBootScriptExecutorContextGuid,
EfiBootScriptExecutorVariable,
sizeof(*EfiBootScriptExecutorVariable)
);
ASSERT_EFI_ERROR (Status);
Status = SetLockBoxAttributes (&gEfiBootScriptExecutorContextGuid, LOCK_BOX_ATTRIBUTE_RESTORE_IN_PLACE);
ASSERT_EFI_ERROR (Status);
}
return EFI_SUCCESS;
}
/**
Platform specific mechanism to transfer control to 16bit OS waking vector
@param[in] AcpiWakingVector The 16bit OS waking vector
@param[in] AcpiLowMemoryBase A buffer under 1M which could be used during the transfer
**/
VOID
PlatformTransferControl16 (
IN UINT32 AcpiWakingVector,
IN UINT32 AcpiLowMemoryBase
)
{
UINT32 NewValue;
UINT64 BaseAddress;
UINT64 SmramLength;
UINTN Index;
DEBUG (( EFI_D_INFO, "PlatformTransferControl - Entry\r\n"));
//
// Need to make sure the GDT is loaded with values that support long mode and real mode.
//
AsmWriteGdtr (&mGdt);
//
// Disable eSram block (this will also clear/zero eSRAM)
// We only use eSRAM in the PEI phase. Disable now that we are resuming the OS
//
NewValue = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK);
NewValue |= BLOCK_DISABLE_PG;
QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK, NewValue);
//
// Update HMBOUND to top of DDR3 memory and LOCK
// We disabled eSRAM so now we move HMBOUND down to top of DDR3
//
QNCGetTSEGMemoryRange (&BaseAddress, &SmramLength);
NewValue = (UINT32)(BaseAddress + SmramLength);
DEBUG ((EFI_D_INFO,"Locking HMBOUND at: = 0x%8x\n",NewValue));
QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_HMBOUND_REG, (NewValue | HMBOUND_LOCK));
//
// Lock all IMR regions now that HMBOUND is locked
//
for (Index = (QUARK_NC_MEMORY_MANAGER_IMR0+QUARK_NC_MEMORY_MANAGER_IMRXL); Index <= (QUARK_NC_MEMORY_MANAGER_IMR7+QUARK_NC_MEMORY_MANAGER_IMRXL); Index += 4) {
NewValue = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, Index);
NewValue |= IMR_LOCK;
QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, Index, NewValue);
}
//
// Call ASM routine to switch to real mode and jump to 16bit OS waking vector
//
AsmTransferControl(AcpiWakingVector, 0);
//
// Never run to here
//
CpuDeadLoop();
}

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/** @file
The header file for Boot Script Executer module.
This driver is dispatched by Dxe core and the driver will reload itself to ACPI NVS memory
in the entry point. The functionality is to interpret and restore the S3 boot script
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _SCRIPT_EXECUTE_H_
#define _SCRIPT_EXECUTE_H_
#include <PiDxe.h>
#include <Library/BaseLib.h>
#include <Library/UefiDriverEntryPoint.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/S3BootScriptLib.h>
#include <Library/PeCoffLib.h>
#include <Library/DxeServicesLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/PcdLib.h>
#include <Library/CacheMaintenanceLib.h>
#include <Library/TimerLib.h>
#include <Library/UefiLib.h>
#include <Library/DebugAgentLib.h>
#include <Library/LockBoxLib.h>
#include <Library/IntelQNCLib.h>
#include <Library/QNCAccessLib.h>
#include <Guid/AcpiS3Context.h>
#include <Guid/BootScriptExecutorVariable.h>
#include <Guid/EventGroup.h>
#include <IndustryStandard/Acpi.h>
/**
a ASM function to transfer control to OS.
@param S3WakingVector The S3 waking up vector saved in ACPI Facs table
@param AcpiLowMemoryBase a buffer under 1M which could be used during the transfer
**/
VOID
AsmTransferControl (
IN UINT32 S3WakingVector,
IN UINT32 AcpiLowMemoryBase
);
VOID
SetIdtEntry (
IN ACPI_S3_CONTEXT *AcpiS3Context
);
/**
Platform specific mechanism to transfer control to 16bit OS waking vector
@param[in] AcpiWakingVector The 16bit OS waking vector
@param[in] AcpiLowMemoryBase A buffer under 1M which could be used during the transfer
**/
VOID
PlatformTransferControl16 (
IN UINT32 AcpiWakingVector,
IN UINT32 AcpiLowMemoryBase
);
#endif //_SCRIPT_EXECUTE_H_