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QuarkPlatformPkg: Add new package for Galileo boards

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Changes for V4
==============
1) Move delete of QuarkSocPkg\QuarkNorthCluster\Binary\QuarkMicrocode
   from QuarkPlatformPkg commit to QuarkSocPkg commit
2) Fix incorrect license header in PlatformSecLibModStrs.uni

Changes for V3
==============
1) Set PcdResetOnMemoryTypeInformationChange FALSE in QuarkMin.dsc
   This is required because QuarkMin.dsc uses the emulated variable
   driver that does not preserve any non-volatile UEFI variables
   across reset.  If the condition is met where the memory type
   information variable needs to be updated, then the system will reset
   every time the UEFI Shell is run.  By setting this PCD to FALSE,
   then reset action is disabled.
2) Move one binary file to QuarkSocBinPkg
3) Change RMU.bin FILE statements to INF statement in DSC FD region
   to be compatible with PACKAGES_PATH search for QuarkSocBinPkg

Changes for V2
==============
1) Use new generic PCI serial driver PciSioSerialDxe in MdeModulePkg
2) Configure PcdPciSerialParameters for PCI serial driver for Quark
3) Use new MtrrLib API to reduce time to set MTRRs for all DRAM
4) Convert all UNI files to utf-8
5) Replace tabs with spaces and remove trailing spaces
6) Add License.txt

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19287 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Michael Kinney
2015-12-15 19:23:57 +00:00
committed by mdkinney
parent 9b6bbcdbfd
commit b303605e1b
190 changed files with 39436 additions and 0 deletions
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61
QuarkPlatformPkg/Library/PlatformPcieHelperLib/CommonHeader.h Normal file
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/** @file
Common header file shared by all source files in this component.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __COMMON_HEADER_H_
#define __COMMON_HEADER_H_
#include <Uefi.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/TimerLib.h>
#include <Library/QNCAccessLib.h>
#include <Library/IntelQNCLib.h>
#include <IntelQNCRegs.h>
#include <IntelQNCConfig.h>
#include <Pcal9555.h>
#include <Platform.h>
#include <PlatformBoards.h>
#include <Library/PlatformPcieHelperLib.h>
//
// Routines shared between souce modules in this component.
//
VOID
EFIAPI
PlatformPcieErratas (
VOID
);
EFI_STATUS
EFIAPI
SocUnitEarlyInitialisation (
VOID
);
EFI_STATUS
EFIAPI
SocUnitReleasePcieControllerPreWaitPllLock (
IN CONST EFI_PLATFORM_TYPE PlatformType
);
EFI_STATUS
EFIAPI
SocUnitReleasePcieControllerPostPllLock (
IN CONST EFI_PLATFORM_TYPE PlatformType
);
#endif

120
QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperLib.c Normal file
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/** @file
Platform Pcie Helper Lib.
Copyright (c) 2013 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "CommonHeader.h"
//
// Routines local to this source module.
//
VOID
LegacyGpioSetLevel (
IN CONST UINT32 LevelRegOffset,
IN CONST UINT32 GpioNum,
IN CONST BOOLEAN HighLevel
)
{
UINT32 RegValue;
UINT32 GpioBaseAddress;
UINT32 GpioNumMask;
GpioBaseAddress = LpcPciCfg32 (R_QNC_LPC_GBA_BASE) & B_QNC_LPC_GPA_BASE_MASK;
ASSERT (GpioBaseAddress > 0);
RegValue = IoRead32 (GpioBaseAddress + LevelRegOffset);
GpioNumMask = (1 << GpioNum);
if (HighLevel) {
RegValue |= (GpioNumMask);
} else {
RegValue &= ~(GpioNumMask);
}
IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGLVL_RESUME_WELL, RegValue);
}
//
// Routines exported by this component.
//
/**
Platform assert PCI express PERST# signal.
@param PlatformType See EFI_PLATFORM_TYPE enum definitions.
**/
VOID
EFIAPI
PlatformPERSTAssert (
IN CONST EFI_PLATFORM_TYPE PlatformType
)
{
if (PlatformType == GalileoGen2) {
LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_GEN2_PCIEXP_PERST_RESUMEWELL_GPIO, FALSE);
} else {
LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, PCIEXP_PERST_RESUMEWELL_GPIO, FALSE);
}
}
/**
Platform de assert PCI express PERST# signal.
@param PlatformType See EFI_PLATFORM_TYPE enum definitions.
**/
VOID
EFIAPI
PlatformPERSTDeAssert (
IN CONST EFI_PLATFORM_TYPE PlatformType
)
{
if (PlatformType == GalileoGen2) {
LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_GEN2_PCIEXP_PERST_RESUMEWELL_GPIO, TRUE);
} else {
LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, PCIEXP_PERST_RESUMEWELL_GPIO, TRUE);
}
}
/** Early initialisation of the PCIe controller.
@param PlatformType See EFI_PLATFORM_TYPE enum definitions.
@retval EFI_SUCCESS Operation success.
**/
EFI_STATUS
EFIAPI
PlatformPciExpressEarlyInit (
IN CONST EFI_PLATFORM_TYPE PlatformType
)
{
//
// Release and wait for PCI controller to come out of reset.
//
SocUnitReleasePcieControllerPreWaitPllLock (PlatformType);
MicroSecondDelay (PCIEXP_DELAY_US_WAIT_PLL_LOCK);
SocUnitReleasePcieControllerPostPllLock (PlatformType);
//
// Early PCIe initialisation
//
SocUnitEarlyInitialisation ();
//
// Do North cluster early PCIe init.
//
PciExpressEarlyInit ();
return EFI_SUCCESS;
}

131
QuarkPlatformPkg/Library/PlatformPcieHelperLib/SocUnit.c Normal file
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/** @file
System On Chip Unit (SOCUnit) routines.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "CommonHeader.h"
/** Early initialisation of the SOC Unit
@retval EFI_SUCCESS Operation success.
**/
EFI_STATUS
EFIAPI
SocUnitEarlyInitialisation (
VOID
)
{
UINT32 NewValue;
//
// Set the mixer load resistance
//
NewValue = QNCPortIORead (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0);
NewValue &= OCFGPIMIXLOAD_1_0_MASK;
QNCPortIOWrite (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0, NewValue);
NewValue = QNCPortIORead (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1);
NewValue &= OCFGPIMIXLOAD_1_0_MASK;
QNCPortIOWrite (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1, NewValue);
return EFI_SUCCESS;
}
/** Tasks to release PCI controller from reset pre wait for PLL Lock.
@retval EFI_SUCCESS Operation success.
**/
EFI_STATUS
EFIAPI
SocUnitReleasePcieControllerPreWaitPllLock (
IN CONST EFI_PLATFORM_TYPE PlatformType
)
{
UINT32 NewValue;
//
// Assert PERST# and validate time assertion time.
//
PlatformPERSTAssert (PlatformType);
ASSERT (PCIEXP_PERST_MIN_ASSERT_US <= (PCIEXP_DELAY_US_POST_CMNRESET_RESET + PCIEXP_DELAY_US_WAIT_PLL_LOCK + PCIEXP_DELAY_US_POST_SBI_RESET));
//
// PHY Common lane reset.
//
NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);
NewValue |= SOCCLKEN_CONFIG_PHY_I_CMNRESET_L;
QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);
//
// Wait post common lane reset.
//
MicroSecondDelay (PCIEXP_DELAY_US_POST_CMNRESET_RESET);
//
// PHY Sideband interface reset.
// Controller main reset
//
NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);
NewValue |= (SOCCLKEN_CONFIG_SBI_RST_100_CORE_B | SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L);
QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);
return EFI_SUCCESS;
}
/** Tasks to release PCI controller from reset after PLL has locked
@retval EFI_SUCCESS Operation success.
**/
EFI_STATUS
EFIAPI
SocUnitReleasePcieControllerPostPllLock (
IN CONST EFI_PLATFORM_TYPE PlatformType
)
{
UINT32 NewValue;
//
// Controller sideband interface reset.
//
NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);
NewValue |= SOCCLKEN_CONFIG_SBI_BB_RST_B;
QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);
//
// Wait post sideband interface reset.
//
MicroSecondDelay (PCIEXP_DELAY_US_POST_SBI_RESET);
//
// Deassert PERST#.
//
PlatformPERSTDeAssert (PlatformType);
//
// Wait post de assert PERST#.
//
MicroSecondDelay (PCIEXP_DELAY_US_POST_PERST_DEASSERT);
//
// Controller primary interface reset.
//
NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);
NewValue |= SOCCLKEN_CONFIG_BB_RST_B;
QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);
return EFI_SUCCESS;
}