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QuarkPlatformPkg: Add new package for Galileo boards

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Changes for V4
==============
1) Move delete of QuarkSocPkg\QuarkNorthCluster\Binary\QuarkMicrocode
   from QuarkPlatformPkg commit to QuarkSocPkg commit
2) Fix incorrect license header in PlatformSecLibModStrs.uni

Changes for V3
==============
1) Set PcdResetOnMemoryTypeInformationChange FALSE in QuarkMin.dsc
   This is required because QuarkMin.dsc uses the emulated variable
   driver that does not preserve any non-volatile UEFI variables
   across reset.  If the condition is met where the memory type
   information variable needs to be updated, then the system will reset
   every time the UEFI Shell is run.  By setting this PCD to FALSE,
   then reset action is disabled.
2) Move one binary file to QuarkSocBinPkg
3) Change RMU.bin FILE statements to INF statement in DSC FD region
   to be compatible with PACKAGES_PATH search for QuarkSocBinPkg

Changes for V2
==============
1) Use new generic PCI serial driver PciSioSerialDxe in MdeModulePkg
2) Configure PcdPciSerialParameters for PCI serial driver for Quark
3) Use new MtrrLib API to reduce time to set MTRRs for all DRAM
4) Convert all UNI files to utf-8
5) Replace tabs with spaces and remove trailing spaces
6) Add License.txt

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19287 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Michael Kinney
2015-12-15 19:23:57 +00:00
committed by mdkinney
parent 9b6bbcdbfd
commit b303605e1b
190 changed files with 39436 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

338
QuarkPlatformPkg/Platform/SpiFvbServices/FvbInfo.c Normal file
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/** @file
Defines data structure that is the volume header found.These data is intent
to decouple FVB driver with FV header.
Copyright (c) 2013 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <PiDxe.h>
#include "FwBlockService.h"
//#define FVB_MEDIA_BLOCK_SIZE PcdGet32(PcdFlashMinEraseSize)
#define FVB_MEDIA_BLOCK_SIZE 0x1000
typedef struct {
EFI_PHYSICAL_ADDRESS BaseAddress;
EFI_FIRMWARE_VOLUME_HEADER FvbInfo;
//
//EFI_FV_BLOCK_MAP_ENTRY ExtraBlockMap[n];//n=0
//
EFI_FV_BLOCK_MAP_ENTRY End[1];
} EFI_FVB2_MEDIA_INFO;
//
// This data structure contains a template of all correct FV headers, which is used to restore
// Fv header if it's corrupted.
//
EFI_FVB2_MEDIA_INFO mPlatformFvbMediaInfo[] = {
//
// Main BIOS FVB
//
{
0,
{
{0,}, //ZeroVector[16]
EFI_FIRMWARE_FILE_SYSTEM2_GUID,
0,
EFI_FVH_SIGNATURE,
0x0004feff, // check MdePkg/Include/Pi/PiFirmwareVolume.h for details on EFI_FVB_ATTRIBUTES_2
sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY),
0, //CheckSum, check the FD for the value.
0, //ExtHeaderOffset
{0,}, //Reserved[1]
2, //Revision
{
{
0,
0,
}
}
},
{
{
0,
0
}
}
},
//
// Systen NvStorage FVB
//
{
0,
{
{0,}, //ZeroVector[16]
EFI_SYSTEM_NV_DATA_FV_GUID,
0,
EFI_FVH_SIGNATURE,
0x0004feff, // check MdePkg/Include/Pi/PiFirmwareVolume.h for details on EFI_FVB_ATTRIBUTES_2
sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY),
0, //CheckSum which will be calucated dynamically.
0, //ExtHeaderOffset
{0,}, //Reserved[1]
2, //Revision
{
{
0,
0,
}
}
},
{
{
0,
0
}
}
},
//
// Recovery BIOS FVB
//
{
0,
{
{0,}, //ZeroVector[16]
EFI_FIRMWARE_FILE_SYSTEM2_GUID,
0,
EFI_FVH_SIGNATURE,
0x0004feff, // check MdePkg/Include/Pi/PiFirmwareVolume.h for details on EFI_FVB_ATTRIBUTES_2
sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY),
0, //CheckSum which will be calucated dynamically.
0, //ExtHeaderOffset
{0,}, //Reserved[1]
2, //Revision
{
{
0,
0,
}
}
},
{
{
0,
0
}
}
},
//
// Payload FVB
//
{
0,
{
{0,}, //ZeroVector[16]
EFI_FIRMWARE_FILE_SYSTEM2_GUID,
0,
EFI_FVH_SIGNATURE,
0x0004feff, // check MdePkg/Include/Pi/PiFirmwareVolume.h for details on EFI_FVB_ATTRIBUTES_2
sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY),
0, //CheckSum which will be calucated dynamically.
0x60, //ExtHeaderOffset
{0,}, //Reserved[1]
2, //Revision
{
{
0,
0,
}
}
},
{
{
0,
0
}
}
}
};
//
// FTW working space and FTW spare space don't have FV header.
// We need create one for them and use it for FVB protocol.
//
EFI_FVB2_MEDIA_INFO mPlatformFtwFvbInfo[] = {
//
// System variable FTW working FVB
//
{
0,
{
{0,}, //ZeroVector[16]
EFI_SYSTEM_NV_DATA_FV_GUID,
0,
EFI_FVH_SIGNATURE,
0x0004feff, // check MdePkg/Include/Pi/PiFirmwareVolume.h for details on EFI_FVB_ATTRIBUTES_2
sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY),
0, //CheckSum which will be calucated dynamically.
0, //ExtHeaderOffset
{0,}, //Reserved[1]
2, //Revision
{
{
0,
0,
}
}
},
{
{
0,
0
}
}
},
//
// Systen NV variable FTW spare FVB
//
{
0,
{
{0,}, //ZeroVector[16]
EFI_SYSTEM_NV_DATA_FV_GUID,
0,
EFI_FVH_SIGNATURE,
0x0004feff, // check MdePkg/Include/Pi/PiFirmwareVolume.h for details on EFI_FVB_ATTRIBUTES_2
sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY),
0, //CheckSum which will be calucated dynamically.
0, //ExtHeaderOffset
{0,}, //Reserved[1]
2, //Revision
{
{
0,
0,
}
}
},
{
{
0,
0
}
}
}
};
EFI_STATUS
GetFtwFvbInfo (
IN EFI_PHYSICAL_ADDRESS FvBaseAddress,
OUT EFI_FIRMWARE_VOLUME_HEADER **FvbInfo
)
{
UINTN Index;
EFI_FIRMWARE_VOLUME_HEADER *FvHeader;
//
// Init Fvb data
//
mPlatformFtwFvbInfo[0].BaseAddress = PcdGet32 (PcdFlashNvStorageFtwWorkingBase);
mPlatformFtwFvbInfo[0].FvbInfo.FvLength = PcdGet32 (PcdFlashNvStorageFtwWorkingSize);
mPlatformFtwFvbInfo[0].FvbInfo.BlockMap[0].NumBlocks = PcdGet32 (PcdFlashNvStorageFtwWorkingSize) / FVB_MEDIA_BLOCK_SIZE;
mPlatformFtwFvbInfo[0].FvbInfo.BlockMap[0].Length = FVB_MEDIA_BLOCK_SIZE;
ASSERT ((PcdGet32 (PcdFlashNvStorageFtwWorkingSize) % FVB_MEDIA_BLOCK_SIZE) == 0);
mPlatformFtwFvbInfo[1].BaseAddress = PcdGet32 (PcdFlashNvStorageFtwSpareBase);
mPlatformFtwFvbInfo[1].FvbInfo.FvLength = PcdGet32 (PcdFlashNvStorageFtwSpareSize);
mPlatformFtwFvbInfo[1].FvbInfo.BlockMap[0].NumBlocks = PcdGet32 (PcdFlashNvStorageFtwSpareSize) / FVB_MEDIA_BLOCK_SIZE;
mPlatformFtwFvbInfo[1].FvbInfo.BlockMap[0].Length = FVB_MEDIA_BLOCK_SIZE;
ASSERT ((PcdGet32 (PcdFlashNvStorageFtwSpareSize) % FVB_MEDIA_BLOCK_SIZE) == 0);
for (Index=0; Index < sizeof (mPlatformFtwFvbInfo)/sizeof (mPlatformFtwFvbInfo[0]); Index += 1) {
if (mPlatformFtwFvbInfo[Index].BaseAddress == FvBaseAddress) {
FvHeader = &mPlatformFtwFvbInfo[Index].FvbInfo;
//
// Update the checksum value of FV header.
//
FvHeader->Checksum = CalculateCheckSum16 ((UINT16 *) FvHeader, FvHeader->HeaderLength / sizeof (UINT16));
*FvbInfo = FvHeader;
DEBUG ((EFI_D_INFO, "\nFTW BaseAddr: 0x%lx \n", FvBaseAddress));
DEBUG ((EFI_D_INFO, "FvLength: 0x%lx \n", (*FvbInfo)->FvLength));
DEBUG ((EFI_D_INFO, "HeaderLength: 0x%x \n", (*FvbInfo)->HeaderLength));
DEBUG ((EFI_D_INFO, "FvBlockMap[0].NumBlocks: 0x%x \n", (*FvbInfo)->BlockMap[0].NumBlocks));
DEBUG ((EFI_D_INFO, "FvBlockMap[0].BlockLength: 0x%x \n", (*FvbInfo)->BlockMap[0].Length));
DEBUG ((EFI_D_INFO, "FvBlockMap[1].NumBlocks: 0x%x \n", (*FvbInfo)->BlockMap[1].NumBlocks));
DEBUG ((EFI_D_INFO, "FvBlockMap[1].BlockLength: 0x%x \n\n", (*FvbInfo)->BlockMap[1].Length));
return EFI_SUCCESS;
}
}
return EFI_NOT_FOUND;
}
EFI_STATUS
GetFvbInfo (
IN EFI_PHYSICAL_ADDRESS FvBaseAddress,
OUT EFI_FIRMWARE_VOLUME_HEADER **FvbInfo
)
{
UINTN Index;
EFI_FIRMWARE_VOLUME_HEADER *FvHeader;
//
// Init Fvb data
//
mPlatformFvbMediaInfo[0].BaseAddress = PcdGet32 (PcdFlashFvMainBase);
mPlatformFvbMediaInfo[0].FvbInfo.FvLength = PcdGet32 (PcdFlashFvMainSize);
mPlatformFvbMediaInfo[0].FvbInfo.BlockMap[0].NumBlocks = PcdGet32 (PcdFlashFvMainSize) / FVB_MEDIA_BLOCK_SIZE;
mPlatformFvbMediaInfo[0].FvbInfo.BlockMap[0].Length = FVB_MEDIA_BLOCK_SIZE;
ASSERT ((PcdGet32 (PcdFlashFvMainSize) % FVB_MEDIA_BLOCK_SIZE) == 0);
mPlatformFvbMediaInfo[1].BaseAddress = PcdGet32 (PcdFlashNvStorageVariableBase);
mPlatformFvbMediaInfo[1].FvbInfo.FvLength = PcdGet32 (PcdFlashNvStorageVariableSize);
mPlatformFvbMediaInfo[1].FvbInfo.BlockMap[0].NumBlocks = PcdGet32 (PcdFlashNvStorageVariableSize) / FVB_MEDIA_BLOCK_SIZE;
mPlatformFvbMediaInfo[1].FvbInfo.BlockMap[0].Length = FVB_MEDIA_BLOCK_SIZE;
ASSERT ((PcdGet32 (PcdFlashNvStorageVariableSize) % FVB_MEDIA_BLOCK_SIZE) == 0);
mPlatformFvbMediaInfo[2].BaseAddress = PcdGet32 (PcdFlashFvRecoveryBase);
mPlatformFvbMediaInfo[2].FvbInfo.FvLength = PcdGet32 (PcdFlashFvRecoverySize);
mPlatformFvbMediaInfo[2].FvbInfo.BlockMap[0].NumBlocks = PcdGet32 (PcdFlashFvRecoverySize) / FVB_MEDIA_BLOCK_SIZE;
mPlatformFvbMediaInfo[2].FvbInfo.BlockMap[0].Length = FVB_MEDIA_BLOCK_SIZE;
ASSERT ((PcdGet32 (PcdFlashFvRecoverySize) % FVB_MEDIA_BLOCK_SIZE) == 0);
mPlatformFvbMediaInfo[3].BaseAddress = PcdGet32 (PcdFlashFvPayloadBase);
mPlatformFvbMediaInfo[3].FvbInfo.FvLength = PcdGet32 (PcdFlashFvPayloadSize);
mPlatformFvbMediaInfo[3].FvbInfo.BlockMap[0].NumBlocks = PcdGet32 (PcdFlashFvPayloadSize) / FVB_MEDIA_BLOCK_SIZE;
mPlatformFvbMediaInfo[3].FvbInfo.BlockMap[0].Length = FVB_MEDIA_BLOCK_SIZE;
ASSERT ((PcdGet32 (PcdFlashFvPayloadSize) % FVB_MEDIA_BLOCK_SIZE) == 0);
for (Index=0; Index < sizeof (mPlatformFvbMediaInfo)/sizeof (mPlatformFvbMediaInfo[0]); Index += 1) {
if (mPlatformFvbMediaInfo[Index].BaseAddress == FvBaseAddress) {
FvHeader = &mPlatformFvbMediaInfo[Index].FvbInfo;
//
// Update the checksum value of FV header.
//
FvHeader->Checksum = CalculateCheckSum16 ((UINT16 *) FvHeader, FvHeader->HeaderLength / sizeof (UINT16));
*FvbInfo = FvHeader;
DEBUG ((EFI_D_INFO, "\nBaseAddr: 0x%lx \n", FvBaseAddress));
DEBUG ((EFI_D_INFO, "FvLength: 0x%lx \n", (*FvbInfo)->FvLength));
DEBUG ((EFI_D_INFO, "HeaderLength: 0x%x \n", (*FvbInfo)->HeaderLength));
DEBUG ((EFI_D_INFO, "FvBlockMap[0].NumBlocks: 0x%x \n", (*FvbInfo)->BlockMap[0].NumBlocks));
DEBUG ((EFI_D_INFO, "FvBlockMap[0].BlockLength: 0x%x \n", (*FvbInfo)->BlockMap[0].Length));
DEBUG ((EFI_D_INFO, "FvBlockMap[1].NumBlocks: 0x%x \n", (*FvbInfo)->BlockMap[1].NumBlocks));
DEBUG ((EFI_D_INFO, "FvBlockMap[1].BlockLength: 0x%x \n\n", (*FvbInfo)->BlockMap[1].Length));
return EFI_SUCCESS;
}
}
return EFI_NOT_FOUND;
}

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QuarkPlatformPkg/Platform/SpiFvbServices/FwBlockService.h Normal file
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/** @file
Firmware volume block driver for SPI device
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _FW_BLOCK_SERVICE_H
#define _FW_BLOCK_SERVICE_H
#include "SpiFlashDevice.h"
//
// Statements that include other header files
#include <Library/IoLib.h>
#include <Library/HobLib.h>
#include <Library/PcdLib.h>
#include <Library/UefiLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DevicePathLib.h>
#include <Library/UefiRuntimeLib.h>
#include <Library/UefiDriverEntryPoint.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/DxeServicesTableLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Guid/EventGroup.h>
#include <Guid/HobList.h>
#include <Guid/FirmwareFileSystem2.h>
#include <Guid/SystemNvDataGuid.h>
#include <Protocol/SmmBase2.h>
#include <Protocol/LoadedImage.h>
#include <Protocol/PlatformSmmSpiReady.h>
//
// Define two helper macro to extract the Capability field or Status field in FVB
// bit fields
//
#define EFI_FVB2_CAPABILITIES (EFI_FVB2_READ_DISABLED_CAP | \
EFI_FVB2_READ_ENABLED_CAP | \
EFI_FVB2_WRITE_DISABLED_CAP | \
EFI_FVB2_WRITE_ENABLED_CAP | \
EFI_FVB2_LOCK_CAP \
)
#define EFI_FVB2_STATUS (EFI_FVB2_READ_STATUS | EFI_FVB2_WRITE_STATUS | EFI_FVB2_LOCK_STATUS)
#define EFI_INTERNAL_POINTER 0x00000004
#define FVB_PHYSICAL 0
#define FVB_VIRTUAL 1
typedef struct {
EFI_LOCK FvbDevLock;
UINTN FvBase[2];
UINTN FvWriteBase[2];
UINTN NumOfBlocks;
BOOLEAN WriteEnabled;
EFI_FIRMWARE_VOLUME_HEADER VolumeHeader;
} EFI_FW_VOL_INSTANCE;
typedef struct {
UINT32 NumFv;
EFI_FW_VOL_INSTANCE *FvInstance[2];
UINT8 *FvbScratchSpace[2];
EFI_SPI_PROTOCOL *SpiProtocol;
EFI_SPI_PROTOCOL *SmmSpiProtocol;
} ESAL_FWB_GLOBAL;
//
// SPI default opcode slots
//
#define SPI_OPCODE_JEDEC_ID_INDEX 0
#define SPI_OPCODE_READ_ID_INDEX 1
#define SPI_OPCODE_WRITE_S_INDEX 2
#define SPI_OPCODE_WRITE_INDEX 3
#define SPI_OPCODE_READ_INDEX 4
#define SPI_OPCODE_ERASE_INDEX 5
#define SPI_OPCODE_READ_S_INDEX 6
#define SPI_OPCODE_CHIP_ERASE_INDEX 7
#define SPI_ERASE_SECTOR_SIZE SIZE_4KB //This is the chipset requirement
//
// Fvb Protocol instance data
//
#define FVB_DEVICE_FROM_THIS(a) CR (a, EFI_FW_VOL_BLOCK_DEVICE, FwVolBlockInstance, FVB_DEVICE_SIGNATURE)
#define FVB_EXTEND_DEVICE_FROM_THIS(a) CR (a, EFI_FW_VOL_BLOCK_DEVICE, FvbExtension, FVB_DEVICE_SIGNATURE)
#define FVB_DEVICE_SIGNATURE SIGNATURE_32 ('F', 'V', 'B', 'C')
//
// Device Path
//
#define EFI_END_ENTIRE_DEVICE_PATH_SUBTYPE 0xff
#define EfiDevicePathType(a) (((a)->Type) & 0x7f)
#define EfiIsDevicePathEndType(a) (EfiDevicePathType (a) == 0x7f)
#define EfiIsDevicePathEndSubType(a) ((a)->SubType == EFI_END_ENTIRE_DEVICE_PATH_SUBTYPE)
#define EfiIsDevicePathEnd(a) (EfiIsDevicePathEndType (a) && EfiIsDevicePathEndSubType (a))
typedef struct {
MEMMAP_DEVICE_PATH MemMapDevPath;
EFI_DEVICE_PATH_PROTOCOL EndDevPath;
} FV_DEVICE_PATH;
//
// UEFI Specification define FV device path format if FV provide name GUID in extension header
//
typedef struct {
MEDIA_FW_VOL_DEVICE_PATH FvDevPath;
EFI_DEVICE_PATH_PROTOCOL EndDevPath;
} UEFI_FV_DEVICE_PATH;
typedef struct {
UINTN Signature;
FV_DEVICE_PATH FvDevicePath;
UEFI_FV_DEVICE_PATH UefiFvDevicePath;
UINTN Instance;
EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL FwVolBlockInstance;
} EFI_FW_VOL_BLOCK_DEVICE;
typedef struct {
EFI_PHYSICAL_ADDRESS BaseAddress;
EFI_FIRMWARE_VOLUME_HEADER FvbInfo;
//
// EFI_FV_BLOCK_MAP_ENTRY ExtraBlockMap[n];//n=0
//
EFI_FV_BLOCK_MAP_ENTRY End[1];
} EFI_FVB_MEDIA_INFO;
VOID
FvbVirtualddressChangeEvent (
IN EFI_EVENT Event,
IN VOID *Context
);
EFI_STATUS
GetFvbInfo (
IN EFI_PHYSICAL_ADDRESS FvBaseAddress,
OUT EFI_FIRMWARE_VOLUME_HEADER **FvbInfo
);
BOOLEAN
SetPlatformFvbLock (
IN UINTN LbaAddress
);
EFI_STATUS
FvbReadBlock (
IN UINTN Instance,
IN EFI_LBA Lba,
IN UINTN BlockOffset,
IN OUT UINTN *NumBytes,
IN UINT8 *Buffer,
IN ESAL_FWB_GLOBAL *Global,
IN BOOLEAN Virtual
);
EFI_STATUS
FvbWriteBlock (
IN UINTN Instance,
IN EFI_LBA Lba,
IN UINTN BlockOffset,
IN OUT UINTN *NumBytes,
IN UINT8 *Buffer,
IN ESAL_FWB_GLOBAL *Global,
IN BOOLEAN Virtual
);
EFI_STATUS
FvbEraseBlock (
IN UINTN Instance,
IN EFI_LBA Lba,
IN ESAL_FWB_GLOBAL *Global,
IN BOOLEAN Virtual
);
EFI_STATUS
FvbSetVolumeAttributes (
IN UINTN Instance,
IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes,
IN ESAL_FWB_GLOBAL *Global,
IN BOOLEAN Virtual
);
EFI_STATUS
FvbGetVolumeAttributes (
IN UINTN Instance,
OUT EFI_FVB_ATTRIBUTES_2 *Attributes,
IN ESAL_FWB_GLOBAL *Global,
IN BOOLEAN Virtual
);
EFI_STATUS
FvbGetPhysicalAddress (
IN UINTN Instance,
OUT EFI_PHYSICAL_ADDRESS *Address,
IN ESAL_FWB_GLOBAL *Global,
IN BOOLEAN Virtual
);
EFI_STATUS
FvbInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
);
VOID
FvbClassAddressChangeEvent (
IN EFI_EVENT Event,
IN VOID *Context
);
EFI_STATUS
FvbSpecificInitialize (
IN ESAL_FWB_GLOBAL *mFvbModuleGlobal
);
EFI_STATUS
FvbGetLbaAddress (
IN UINTN Instance,
IN EFI_LBA Lba,
OUT UINTN *LbaAddress,
OUT UINTN *LbaWriteAddress,
OUT UINTN *LbaLength,
OUT UINTN *NumOfBlocks,
IN ESAL_FWB_GLOBAL *Global,
IN BOOLEAN Virtual
);
EFI_STATUS
FvbEraseCustomBlockRange (
IN UINTN Instance,
IN EFI_LBA StartLba,
IN UINTN OffsetStartLba,
IN EFI_LBA LastLba,
IN UINTN OffsetLastLba,
IN ESAL_FWB_GLOBAL *Global,
IN BOOLEAN Virtual
);
//
// Protocol APIs
//
EFI_STATUS
EFIAPI
FvbProtocolGetAttributes (
IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
OUT EFI_FVB_ATTRIBUTES_2 *Attributes
);
EFI_STATUS
EFIAPI
FvbProtocolSetAttributes (
IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
);
EFI_STATUS
EFIAPI
FvbProtocolGetPhysicalAddress (
IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
OUT EFI_PHYSICAL_ADDRESS *Address
);
EFI_STATUS
FvbProtocolGetBlockSize (
IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
IN EFI_LBA Lba,
OUT UINTN *BlockSize,
OUT UINTN *NumOfBlocks
);
EFI_STATUS
EFIAPI
FvbProtocolRead (
IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
IN EFI_LBA Lba,
IN UINTN Offset,
IN OUT UINTN *NumBytes,
IN UINT8 *Buffer
);
EFI_STATUS
EFIAPI
FvbProtocolWrite (
IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
IN EFI_LBA Lba,
IN UINTN Offset,
IN OUT UINTN *NumBytes,
IN UINT8 *Buffer
);
EFI_STATUS
EFIAPI
FvbProtocolEraseBlocks (
IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
...
);
extern SPI_INIT_TABLE mSpiInitTable[];
#endif

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/** @file
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "FwBlockService.h"
/**
This function allows the caller to determine if UEFI SetVirtualAddressMap() has been called.
This function returns TRUE after all the EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE functions have
executed as a result of the OS calling SetVirtualAddressMap(). Prior to this time FALSE
is returned. This function is used by runtime code to decide it is legal to access services
that go away after SetVirtualAddressMap().
@retval TRUE The system has finished executing the EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE event.
@retval FALSE The system has not finished executing the EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE event.
**/
BOOLEAN
EfiGoneVirtual (
VOID
)
{
return FALSE; //Hard coded to FALSE for SMM driver.
}

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QuarkPlatformPkg/Platform/SpiFvbServices/PlatformSmmSpi.inf Normal file
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## @file
# Component description file for SpiFvbServices Module
#
# Copyright (c) 2013-2015 Intel Corporation.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = FwBlockServiceSmm
FILE_GUID = A469DDBD-16D0-4535-BAE3-77274BD70B4C
MODULE_TYPE = DXE_SMM_DRIVER
VERSION_STRING = 1.0
PI_SPECIFICATION_VERSION = 0x0001000A
ENTRY_POINT = FvbInitialize
[Sources]
FwBlockService.c
FwBlockService.h
FvbInfo.c
SpiFlashDevice.c
SpiFlashDevice.h
PlatformSmmSpi.c
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
QuarkSocPkg/QuarkSocPkg.dec
QuarkPlatformPkg/QuarkPlatformPkg.dec
[LibraryClasses]
IoLib
PcdLib
HobLib
UefiLib
BaseMemoryLib
UefiDriverEntryPoint
MemoryAllocationLib
UefiRuntimeServicesTableLib
UefiBootServicesTableLib
DxeServicesTableLib
[Guids]
gEfiEventVirtualAddressChangeGuid
gEfiHobListGuid
[Protocols]
gEfiFirmwareVolumeBlockProtocolGuid ##Produces
gEfiSpiProtocolGuid
gEfiDevicePathProtocolGuid
gEfiLoadedImageProtocolGuid
gEfiSmmBase2ProtocolGuid
gEfiSmmSpiProtocolGuid
gEfiSmmFirmwareVolumeBlockProtocolGuid
gEfiSmmSpiReadyProtocolGuid
[FixedPcd]
gQuarkPlatformTokenSpaceGuid.PcdFlashAreaSize
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
gQuarkPlatformTokenSpaceGuid.PcdFlashAreaBaseAddress
gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainSize
gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainBase
gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoveryBase
gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoverySize
gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadBase
gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadSize
gQuarkPlatformTokenSpaceGuid.PcdSpiFlashDeviceSize
[Depex]
gEfiSpiProtocolGuid

85
QuarkPlatformPkg/Platform/SpiFvbServices/PlatformSpi.inf Normal file
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## @file
# Component description file for SpiFvbServices Module
#
# Copyright (c) 2013-2015 Intel Corporation.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = FwBlockService
FILE_GUID = 4D35A5A7-622E-4955-A5D2-CDA812940D74
MODULE_TYPE = DXE_RUNTIME_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = FvbInitialize
[Sources]
FwBlockService.c
FwBlockService.h
FvbInfo.c
SpiFlashDevice.c
SpiFlashDevice.h
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
QuarkSocPkg/QuarkSocPkg.dec
QuarkPlatformPkg/QuarkPlatformPkg.dec
[LibraryClasses]
IoLib
PcdLib
HobLib
UefiLib
BaseMemoryLib
UefiDriverEntryPoint
MemoryAllocationLib
UefiRuntimeLib
UefiRuntimeServicesTableLib
UefiBootServicesTableLib
DxeServicesTableLib
[Guids]
gEfiEventVirtualAddressChangeGuid
gEfiHobListGuid
[Protocols]
gEfiFirmwareVolumeBlockProtocolGuid ##Produces
gEfiSpiProtocolGuid
gEfiDevicePathProtocolGuid
gEfiLoadedImageProtocolGuid
gEfiSmmBase2ProtocolGuid
gEfiSmmSpiProtocolGuid
gEfiSmmFirmwareVolumeBlockProtocolGuid
gEfiSmmSpiReadyProtocolGuid
[FixedPcd]
gQuarkPlatformTokenSpaceGuid.PcdFlashAreaSize
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
gQuarkPlatformTokenSpaceGuid.PcdFlashAreaBaseAddress
gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainSize
gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainBase
gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoveryBase
gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoverySize
gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadBase
gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadSize
gQuarkPlatformTokenSpaceGuid.PcdSpiFlashDeviceSize
[Depex]
gEfiSpiProtocolGuid

337
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/** @file
Initializes Platform Specific Drivers.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "SpiFlashDevice.h"
#define FLASH_SIZE (FixedPcdGet32 (PcdFlashAreaSize))
SPI_INIT_TABLE mSpiInitTable[] = {
//
// Macronix 32Mbit part
//
{
SPI_MX25L3205_ID1,
SPI_MX25L3205_ID2,
SPI_MX25L3205_ID3,
{
SPI_COMMAND_WRITE_ENABLE,
SPI_COMMAND_WRITE_S_EN
},
{
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},
{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData},
{EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
},
0x400000 - FLASH_SIZE, // BIOS Start Offset
FLASH_SIZE // BIOS image size in flash
},
//
// Winbond 32Mbit part
//
{
SPI_W25X32_ID1,
SF_DEVICE_ID0_W25QXX,
SF_DEVICE_ID1_W25Q32,
{
SPI_COMMAND_WRITE_ENABLE,
SPI_COMMAND_WRITE_S_EN
},
{
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},
{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},
{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
},
0x400000 - FLASH_SIZE, // BIOS Start Offset
FLASH_SIZE // BIOS image size in flash
},
//
// Winbond 32Mbit part
//
{
SPI_W25X32_ID1,
SPI_W25X32_ID2,
SPI_W25X32_ID3,
{
SPI_COMMAND_WRITE_ENABLE,
SPI_COMMAND_WRITE_S_EN
},
{
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},
{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData},
{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_4K_Byte},
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
},
0x400000 - FLASH_SIZE, // BIOS Start Offset
FLASH_SIZE // BIOS image size in flash
},
//
// Atmel 32Mbit part
//
{
SPI_AT26DF321_ID1,
SPI_AT26DF321_ID2, // issue: byte 2 identifies family/density for Atmel
SPI_AT26DF321_ID3,
{
SPI_COMMAND_WRITE_ENABLE,
SPI_COMMAND_WRITE_S_EN
},
{
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},
{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData},
{EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
},
0x400000 - FLASH_SIZE, // BIOS Start Offset
FLASH_SIZE // BIOS image size in flash
},
//
// Intel 32Mbit part bottom boot
//
{
SPI_QH25F320_ID1,
SPI_QH25F320_ID2,
SPI_QH25F320_ID3,
{
SPI_COMMAND_WRITE_ENABLE,
SPI_COMMAND_WRITE_ENABLE
},
{
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},
{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData},
{EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
},
0, // BIOS Start Offset
FLASH_SIZE // BIOS image size in flash
},
//
// SST 64Mbit part
//
{
SPI_SST25VF080B_ID1, // VendorId
SF_DEVICE_ID0_25VF064C, // DeviceId 0
SF_DEVICE_ID1_25VF064C, // DeviceId 1
{
SPI_COMMAND_WRITE_ENABLE,
SPI_COMMAND_WRITE_S_EN
},
{
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},
{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},
{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
},
0x800000 - FLASH_SIZE, // BIOS Start Offset
FLASH_SIZE // BIOS image size in flash
},
//
// NUMONYX 64Mbit part
//
{
SF_VENDOR_ID_NUMONYX, // VendorId
SF_DEVICE_ID0_M25PX64, // DeviceId 0
SF_DEVICE_ID1_M25PX64, // DeviceId 1
{
SPI_COMMAND_WRITE_ENABLE,
SPI_COMMAND_WRITE_S_EN
},
{
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},
{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},
{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
},
0x800000 - FLASH_SIZE, // BIOS Start Offset
FLASH_SIZE // BIOS image size in flash
},
//
// Atmel 64Mbit part
//
{
SF_VENDOR_ID_ATMEL, // VendorId
SF_DEVICE_ID0_AT25DF641, // DeviceId 0
SF_DEVICE_ID1_AT25DF641, // DeviceId 1
{
SPI_COMMAND_WRITE_ENABLE,
SPI_COMMAND_WRITE_S_EN
},
{
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},
{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},
{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
},
0x800000 - FLASH_SIZE, // BIOS Start Offset
FLASH_SIZE // BIOS image size in flash
},
//
// Spansion 64Mbit part
//
{
SF_VENDOR_ID_SPANSION, // VendorId
SF_DEVICE_ID0_S25FL064K, // DeviceId 0
SF_DEVICE_ID1_S25FL064K, // DeviceId 1
{
SPI_COMMAND_WRITE_ENABLE,
SPI_COMMAND_WRITE_S_EN
},
{
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},
{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},
{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
},
0x800000 - FLASH_SIZE, // BIOS Start Offset
FLASH_SIZE // BIOS image size in flash
},
//
// Macronix 64Mbit part bottom boot
//
{
SF_VENDOR_ID_MX, // VendorId
SF_DEVICE_ID0_25L6405D, // DeviceId 0
SF_DEVICE_ID1_25L6405D, // DeviceId 1
{
SPI_COMMAND_WRITE_ENABLE,
SPI_COMMAND_WRITE_S_EN
},
{
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},
{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},
{EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte},
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
},
0x800000 - FLASH_SIZE, // BIOS Start Offset
FLASH_SIZE // BIOS image size in flash
},
//
// Winbond 64Mbit part bottom boot
//
{
SPI_W25X64_ID1,
SF_DEVICE_ID0_W25QXX,
SF_DEVICE_ID1_W25Q64,
{
SPI_COMMAND_WRITE_ENABLE,
SPI_COMMAND_WRITE_S_EN
},
{
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},
{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},
{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
},
0x800000 - FLASH_SIZE, // BIOS Start Offset
FLASH_SIZE // BIOS image size in flash
},
//
// Winbond 64Mbit part bottom boot
//
{
SPI_W25X64_ID1,
SPI_W25X64_ID2,
SPI_W25X64_ID3,
{
SPI_COMMAND_WRITE_ENABLE,
SPI_COMMAND_WRITE_S_EN
},
{
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},
{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},
{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
},
0x800000 - FLASH_SIZE, // BIOS Start Offset
FLASH_SIZE // BIOS image size in flash
},
//
// Intel 64Mbit part bottom boot
//
{
SPI_QH25F640_ID1,
SPI_QH25F640_ID2,
SPI_QH25F640_ID3,
{
SPI_COMMAND_WRITE_ENABLE,
SPI_COMMAND_WRITE_S_EN
},
{
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},
{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData},
{EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
},
0x800000 - FLASH_SIZE, // BIOS Start Offset
FLASH_SIZE // BIOS image size in flash
}
};

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/** @file
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _SPI_FLASH_DEVICE_H_
#define _SPI_FLASH_DEVICE_H_
#include <PiDxe.h>
#include <Protocol/Spi.h>
#include <Protocol/FirmwareVolumeBlock.h>
//
// Supported SPI Flash Devices
//
typedef enum {
EnumSpiFlash25L3205D, // Macronix 32Mbit part
EnumSpiFlashW25Q32, // Winbond 32Mbit part
EnumSpiFlashW25X32, // Winbond 32Mbit part
EnumSpiFlashAT25DF321, // Atmel 32Mbit part
EnumSpiFlashQH25F320, // Intel 32Mbit part
EnumSpiFlash25VF064C, // SST 64Mbit part
EnumSpiFlashM25PX64, // NUMONYX 64Mbit part
EnumSpiFlashAT25DF641, // Atmel 64Mbit part
EnumSpiFlashS25FL064K, // Spansion 64Mbit part
EnumSpiFlash25L6405D, // Macronix 64Mbit part
EnumSpiFlashW25Q64, // Winbond 64Mbit part
EnumSpiFlashW25X64, // Winbond 64Mbit part
EnumSpiFlashQH25F640, // Intel 64Mbit part
EnumSpiFlashMax
} SPI_FLASH_TYPES_SUPPORTED;
//
// Flash Device commands
//
// If a supported device uses a command different from the list below, a device specific command
// will be defined just below it's JEDEC id section.
//
#define SPI_COMMAND_WRITE 0x02
#define SPI_COMMAND_WRITE_AAI 0xAD
#define SPI_COMMAND_READ 0x03
#define SPI_COMMAND_ERASE 0x20
#define SPI_COMMAND_WRITE_DISABLE 0x04
#define SPI_COMMAND_READ_S 0x05
#define SPI_COMMAND_WRITE_ENABLE 0x06
#define SPI_COMMAND_READ_ID 0xAB
#define SPI_COMMAND_JEDEC_ID 0x9F
#define SPI_COMMAND_WRITE_S_EN 0x50
#define SPI_COMMAND_WRITE_S 0x01
#define SPI_COMMAND_CHIP_ERASE 0xC7
#define SPI_COMMAND_BLOCK_ERASE 0xD8
//
// Flash JEDEC device ids
//
// SST 8Mbit part
//
#define SPI_SST25VF080B_ID1 0xBF
#define SPI_SST25VF080B_ID2 0x25
#define SPI_SST25VF080B_ID3 0x8E
//
// SST 16Mbit part
//
#define SPI_SST25VF016B_ID1 0xBF
#define SPI_SST25VF016B_ID2 0x25
#define SPI_SST25V016BF_ID3 0x41
//
// Macronix 32Mbit part
//
// MX25 part does not support WRITE_AAI comand (0xAD)
//
#define SPI_MX25L3205_ID1 0xC2
#define SPI_MX25L3205_ID2 0x20
#define SPI_MX25L3205_ID3 0x16
//
// Intel 32Mbit part bottom boot
//
#define SPI_QH25F320_ID1 0x89
#define SPI_QH25F320_ID2 0x89
#define SPI_QH25F320_ID3 0x12 // 32Mbit bottom boot
//
// Intel 64Mbit part bottom boot
//
#define SPI_QH25F640_ID1 0x89
#define SPI_QH25F640_ID2 0x89
#define SPI_QH25F640_ID3 0x13 // 64Mbit bottom boot
//
// QH part does not support command 0x20 for erase; only 0xD8 (sector erase)
// QH part has 0x40 command for erase of parameter block (8 x 8K blocks at bottom of part)
// 0x40 command ignored if address outside of parameter block range
//
#define SPI_QH25F320_COMMAND_PBLOCK_ERASE 0x40
//
// Winbond 32Mbit part
//
#define SPI_W25X32_ID1 0xEF
#define SPI_W25X32_ID2 0x30 // Memory Type
#define SPI_W25X32_ID3 0x16 // Capacity
#define SF_DEVICE_ID1_W25Q32 0x16
//
// Winbond 64Mbit part
//
#define SPI_W25X64_ID1 0xEF
#define SPI_W25X64_ID2 0x30 // Memory Type
#define SPI_W25X64_ID3 0x17 // Capacity
#define SF_DEVICE_ID0_W25QXX 0x40
#define SF_DEVICE_ID1_W25Q64 0x17
//
// Winbond 128Mbit part
//
#define SF_DEVICE_ID0_W25Q128 0x40
#define SF_DEVICE_ID1_W25Q128 0x18
//
// Atmel 32Mbit part
//
#define SPI_AT26DF321_ID1 0x1F
#define SPI_AT26DF321_ID2 0x47 // [7:5]=Family, [4:0]=Density
#define SPI_AT26DF321_ID3 0x00
#define SF_VENDOR_ID_ATMEL 0x1F
#define SF_DEVICE_ID0_AT25DF641 0x48
#define SF_DEVICE_ID1_AT25DF641 0x00
//
// SST 8Mbit part
//
#define SPI_SST25VF080B_ID1 0xBF
#define SPI_SST25VF080B_ID2 0x25
#define SPI_SST25VF080B_ID3 0x8E
#define SF_DEVICE_ID0_25VF064C 0x25
#define SF_DEVICE_ID1_25VF064C 0x4B
//
// SST 16Mbit part
//
#define SPI_SST25VF016B_ID1 0xBF
#define SPI_SST25VF016B_ID2 0x25
#define SPI_SST25V016BF_ID3 0x41
//
// Winbond 32Mbit part
//
#define SPI_W25X32_ID1 0xEF
#define SPI_W25X32_ID2 0x30 // Memory Type
#define SPI_W25X32_ID3 0x16 // Capacity
#define SF_VENDOR_ID_MX 0xC2
#define SF_DEVICE_ID0_25L6405D 0x20
#define SF_DEVICE_ID1_25L6405D 0x17
#define SF_VENDOR_ID_NUMONYX 0x20
#define SF_DEVICE_ID0_M25PX64 0x71
#define SF_DEVICE_ID1_M25PX64 0x17
//
// Spansion 64Mbit part
//
#define SF_VENDOR_ID_SPANSION 0xEF
#define SF_DEVICE_ID0_S25FL064K 0x40
#define SF_DEVICE_ID1_S25FL064K 0x00
//
// index for prefix opcodes
//
#define SPI_WREN_INDEX 0 // Prefix Opcode 0: SPI_COMMAND_WRITE_ENABLE
#define SPI_EWSR_INDEX 1 // Prefix Opcode 1: SPI_COMMAND_WRITE_S_EN
#define BIOS_CTRL 0xDC
#define PFAB_CARD_DEVICE_ID 0x5150
#define PFAB_CARD_VENDOR_ID 0x8086
#define PFAB_CARD_SETUP_REGISTER 0x40
#define PFAB_CARD_SETUP_BYTE 0x0d
#endif