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MdeModulePkg/SdMmcPciHcDxe: Add SDMMC HC v4 and above Support.

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Add SDMA, ADMA2 and 26b data length support.

If V4 64 bit address mode is supported in capabilities register,
program controller to enable V4 host mode and use appropriate
SDMA registers supporting 64 bit addresses.

If V4 64 bit address mode is supported in capabilities register,
program controller to enable V4 host mode and use appropriate
ADMA descriptors supporting 64 bit addresses.

If host controller version is above V4.0, enable ADMA2 with 26b data
length support for better performance. HC 2 register is configured to
use 26 bit data lengths and ADMA2 descriptors are configured appropriately.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1359

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
This commit is contained in:
Ashish Singhal
2019-01-02 23:46:48 +08:00
committed by Hao Wu
parent 19b0fc0a6b
commit b5547b9ce9
6 changed files with 366 additions and 83 deletions
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7
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
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@@ -2,6 +2,7 @@
Provides some data structure definitions used by the SD/MMC host controller driver.
Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -116,8 +117,7 @@ typedef struct {
SD_MMC_HC_SLOT Slot[SD_MMC_HC_MAX_SLOT];
SD_MMC_HC_SLOT_CAP Capability[SD_MMC_HC_MAX_SLOT];
UINT64 MaxCurrent[SD_MMC_HC_MAX_SLOT];
UINT32 ControllerVersion;
UINT16 ControllerVersion[SD_MMC_HC_MAX_SLOT];
//
// Some controllers may require to override base clock frequency
@@ -150,7 +150,8 @@ typedef struct {
BOOLEAN Started;
UINT64 Timeout;
SD_MMC_HC_ADMA_DESC_LINE *AdmaDesc;
SD_MMC_HC_ADMA_32_DESC_LINE *Adma32Desc;
SD_MMC_HC_ADMA_64_DESC_LINE *Adma64Desc;
EFI_PHYSICAL_ADDRESS AdmaDescPhy;
VOID *AdmaMap;
UINT32 AdmaPages;