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MdeModulePkg/SdMmcPciHcDxe: Add SDMMC HC v4 and above Support.

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Add SDMA, ADMA2 and 26b data length support.

If V4 64 bit address mode is supported in capabilities register,
program controller to enable V4 host mode and use appropriate
SDMA registers supporting 64 bit addresses.

If V4 64 bit address mode is supported in capabilities register,
program controller to enable V4 host mode and use appropriate
ADMA descriptors supporting 64 bit addresses.

If host controller version is above V4.0, enable ADMA2 with 26b data
length support for better performance. HC 2 register is configured to
use 26 bit data lengths and ADMA2 descriptors are configured appropriately.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1359

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
This commit is contained in:
Ashish Singhal
2019-01-02 23:46:48 +08:00
committed by Hao Wu
parent 19b0fc0a6b
commit b5547b9ce9
6 changed files with 366 additions and 83 deletions
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84
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
View File

@@ -2,6 +2,7 @@
Provides some data structure definitions used by the SD/MMC host controller driver.
Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -91,18 +92,38 @@ typedef enum {
//
// The maximum data length of each descriptor line
//
#define ADMA_MAX_DATA_PER_LINE 0x10000
#define ADMA_MAX_DATA_PER_LINE_16B SIZE_64KB
#define ADMA_MAX_DATA_PER_LINE_26B SIZE_64MB
//
// ADMA descriptor for 32b addressing.
//
typedef struct {
UINT32 Valid:1;
UINT32 End:1;
UINT32 Int:1;
UINT32 Reserved:1;
UINT32 Act:2;
UINT32 Reserved1:10;
UINT32 Length:16;
UINT32 UpperLength:10;
UINT32 LowerLength:16;
UINT32 Address;
} SD_MMC_HC_ADMA_DESC_LINE;
} SD_MMC_HC_ADMA_32_DESC_LINE;
//
// ADMA descriptor for 64b addressing.
//
typedef struct {
UINT32 Valid:1;
UINT32 End:1;
UINT32 Int:1;
UINT32 Reserved:1;
UINT32 Act:2;
UINT32 UpperLength:10;
UINT32 LowerLength:16;
UINT32 LowerAddress;
UINT32 UpperAddress;
UINT32 Reserved1;
} SD_MMC_HC_ADMA_64_DESC_LINE;
#define SD_MMC_SDMA_BOUNDARY 512 * 1024
#define SD_MMC_SDMA_ROUND_UP(x, n) (((x) + n) & ~(n - 1))
@@ -129,36 +150,43 @@ typedef struct {
UINT32 Voltage33:1; // bit 24
UINT32 Voltage30:1; // bit 25
UINT32 Voltage18:1; // bit 26
UINT32 Reserved3:1; // bit 27
UINT32 SysBus64:1; // bit 28
UINT32 SysBus64V4:1; // bit 27
UINT32 SysBus64V3:1; // bit 28
UINT32 AsyncInt:1; // bit 29
UINT32 SlotType:2; // bit 30:31
UINT32 Sdr50:1; // bit 32
UINT32 Sdr104:1; // bit 33
UINT32 Ddr50:1; // bit 34
UINT32 Reserved4:1; // bit 35
UINT32 Reserved3:1; // bit 35
UINT32 DriverTypeA:1; // bit 36
UINT32 DriverTypeC:1; // bit 37
UINT32 DriverTypeD:1; // bit 38
UINT32 DriverType4:1; // bit 39
UINT32 TimerCount:4; // bit 40:43
UINT32 Reserved5:1; // bit 44
UINT32 Reserved4:1; // bit 44
UINT32 TuningSDR50:1; // bit 45
UINT32 RetuningMod:2; // bit 46:47
UINT32 ClkMultiplier:8; // bit 48:55
UINT32 Reserved6:7; // bit 56:62
UINT32 Reserved5:7; // bit 56:62
UINT32 Hs400:1; // bit 63
} SD_MMC_HC_SLOT_CAP;
//
// SD Host controller version
//
#define SD_MMC_HC_CTRL_VER_100 0x00
#define SD_MMC_HC_CTRL_VER_200 0x01
#define SD_MMC_HC_CTRL_VER_300 0x02
#define SD_MMC_HC_CTRL_VER_400 0x03
#define SD_MMC_HC_CTRL_VER_410 0x04
#define SD_MMC_HC_CTRL_VER_420 0x05
#define SD_MMC_HC_CTRL_VER_100 0x00
#define SD_MMC_HC_CTRL_VER_200 0x01
#define SD_MMC_HC_CTRL_VER_300 0x02
#define SD_MMC_HC_CTRL_VER_400 0x03
#define SD_MMC_HC_CTRL_VER_410 0x04
#define SD_MMC_HC_CTRL_VER_420 0x05
//
// SD Host controller V4 enhancements
//
#define SD_MMC_HC_V4_EN BIT12
#define SD_MMC_HC_64_ADDR_EN BIT13
#define SD_MMC_HC_26_DATA_LEN_ADMA_EN BIT10
/**
Dump the content of SD/MMC host controller's Capability Register.
@@ -322,6 +350,24 @@ SdMmcHcWaitMmioSet (
IN UINT64 Timeout
);
/**
Get the controller version information from the specified slot.
@param[in] PciIo The PCI IO protocol instance.
@param[in] Slot The slot number of the SD card to send the command to.
@param[out] Version The buffer to store the version information.
@retval EFI_SUCCESS The operation executes successfully.
@retval Others The operation fails.
**/
EFI_STATUS
SdMmcHcGetControllerVersion (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot,
OUT UINT16 *Version
);
/**
Set all interrupt status bits in Normal and Error Interrupt Status Enable
register.
@@ -424,6 +470,7 @@ SdMmcHcStopClock (
@param[in] Slot The slot number of the SD card to send the command to.
@param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
@param[in] BaseClkFreq The base clock frequency of host controller in MHz.
@param[in] ControllerVer The version of host controller.
@retval EFI_SUCCESS The clock is supplied successfully.
@retval Others The clock isn't supplied successfully.
@@ -434,7 +481,8 @@ SdMmcHcClockSupply (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot,
IN UINT64 ClockFreq,
IN UINT32 BaseClkFreq
IN UINT32 BaseClkFreq,
IN UINT16 ControllerVer
);
/**
@@ -483,6 +531,7 @@ SdMmcHcSetBusWidth (
@param[in] PciIo The PCI IO protocol instance.
@param[in] Slot The slot number of the SD card to send the command to.
@param[in] BaseClkFreq The base clock frequency of host controller in MHz.
@param[in] ControllerVer The version of host controller.
@retval EFI_SUCCESS The clock is supplied successfully.
@retval Others The clock isn't supplied successfully.
@@ -492,7 +541,8 @@ EFI_STATUS
SdMmcHcInitClockFreq (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot,
IN UINT32 BaseClkFreq
IN UINT32 BaseClkFreq,
IN UINT16 ControllerVer
);
/**