OvmfPkg/IndustryStandard: define macros for QEMU's CPU hotplug registers

In v1.5.0, QEMU's "pc" (i440fx) board gained a "CPU present bitmap"
register block. In v2.0.0, this was extended to the "q35" board.

In v2.7.0, a new (read/write) register interface was laid over the "CPU
present bitmap", with an option for the guest to switch the register block
to the new (a.k.a. modern) interface.

Both interfaces are documented in "docs/specs/acpi_cpu_hotplug.txt" in the
QEMU tree.

Add macros for a minimal subset of the modern interface, just so we can
count the possible CPUs (as opposed to boot CPUs) in a later patch in this
series.

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1515
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20191022221554.14963-3-lersek@redhat.com>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

OvmfPkg/Include/IndustryStandard/I440FxPiix4.h

@@ -46,4 +46,9 @@
 #define PIIX4_PMREGMISC        0x80
 #define PIIX4_PMREGMISC_PMIOSE   BIT0
 
+//
+// IO ports
+//
+#define PIIX4_CPU_HOTPLUG_BASE 0xAF00
+
 #endif

OvmfPkg/Include/IndustryStandard/Q35MchIch9.h

@@ -106,6 +106,8 @@
 #define ICH9_APM_CNT 0xB2
 #define ICH9_APM_STS 0xB3
 
+#define ICH9_CPU_HOTPLUG_BASE 0x0CD8
+
 //
 // IO ports relative to PMBASE
 //

OvmfPkg/Include/IndustryStandard/QemuCpuHotplug.h

@@ -0,0 +1,43 @@
+/** @file
+  Macros for accessing QEMU's CPU hotplug register block.
+
+  Copyright (C) 2019, Red Hat, Inc.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+
+  - "docs/specs/acpi_cpu_hotplug.txt" in the QEMU source tree.
+
+    The original (now "legacy") CPU hotplug interface appeared in QEMU v1.5.0.
+    The new ("modern") hotplug interface appeared in QEMU v2.7.0.
+
+    The macros in this header file map to the minimal subset of the modern
+    interface that OVMF needs.
+**/
+
+#ifndef QEMU_CPU_HOTPLUG_H_
+#define QEMU_CPU_HOTPLUG_H_
+
+#include <Base.h>
+
+//
+// Each register offset is:
+// - relative to the board-dependent IO base address of the register block,
+// - named QEMU_CPUHP_(R|W|RW)_*, according to the possible access modes of the
+//   register,
+// - followed by distinguished bitmasks or values in the register.
+//
+#define QEMU_CPUHP_R_CMD_DATA2               0x0
+
+#define QEMU_CPUHP_R_CPU_STAT                0x4
+#define QEMU_CPUHP_STAT_ENABLED                BIT0
+
+#define QEMU_CPUHP_RW_CMD_DATA               0x8
+
+#define QEMU_CPUHP_W_CPU_SEL                 0x0
+
+#define QEMU_CPUHP_W_CMD                     0x5
+#define QEMU_CPUHP_CMD_GET_PENDING             0x0
+
+#endif // QEMU_CPU_HOTPLUG_H_