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UefiCpuPkg/Include/Register/Msr: Update reference spec info.

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Latest SDM has moved MSR related content from volume 3 chapter 35 to volume 4
chapter 2. Current MSR's comments need to be updated to reference the new
chapter info.

Changes includes:
  1. Update referenced chapter info from some MSRs.
  2. Update referenced SDM version info.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
This commit is contained in:
Eric Dong
2018-08-27 16:20:26 +08:00
parent 447b08b3d2
commit ba1a2d1102
21 changed files with 359 additions and 372 deletions
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44
UefiCpuPkg/Include/Register/ArchitecturalMsr.h
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@@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,16 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.1.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Appendix A VMX Capability Reporting Facility, Section A.1.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Appendix A VMX Capability Reporting Facility, Section A.6.
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@@ -33,7 +25,7 @@
#define __ARCHITECTURAL_MSR_H__
/**
See Section 35.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).
See Section 2.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).
@param ECX MSR_IA32_P5_MC_ADDR (0x00000000)
@param EAX Lower 32-bits of MSR value.
@@ -52,7 +44,7 @@
/**
See Section 35.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.
See Section 2.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.
@param ECX MSR_IA32_P5_MC_TYPE (0x00000001)
@param EAX Lower 32-bits of MSR value.
@@ -91,7 +83,7 @@
/**
See Section 17.15, "Time-Stamp Counter.". Introduced at Display Family /
See Section 17.17, "Time-Stamp Counter.". Introduced at Display Family /
Display Model 05_01H.
@param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010)
@@ -493,9 +485,8 @@ typedef union {
UINT32 Valid:1;
UINT32 Reserved1:1;
///
/// [Bit 2] Determines whether executions of VMXOFF unblock SMIs under the
/// default treatment of SMIs and SMM. Executions of VMXOFF unblock SMIs
/// unless bit 2 is 1 (the value of bit 0 is irrelevant).
/// [Bit 2] Controls SMI unblocking by VMXOFF (see Section 34.14.4). If
/// IA32_VMX_MISC[28].
///
UINT32 BlockSmi:1;
UINT32 Reserved2:9;
@@ -1953,7 +1944,7 @@ typedef union {
/**
SMRR Range Mask. (Writeable only in SMM) Range Mask of SMM memory range. If
SMRR Range Mask (Writeable only in SMM) Range Mask of SMM memory range. If
IA32_MTRRCAP[SMRR] = 1.
@param ECX MSR_IA32_SMRR_PHYSMASK (0x000001F3)
@@ -4417,13 +4408,13 @@ typedef union {
///
struct {
///
/// [Bit 0] Lock. See Section 42.11.3, "Interactions with Authenticated
/// [Bit 0] Lock. See Section 41.11.3, "Interactions with Authenticated
/// Code Modules (ACMs)".
///
UINT32 Lock:1;
UINT32 Reserved1:15;
///
/// [Bits 23:16] SGX_SVN_SINIT. See Section 42.11.3, "Interactions with
/// [Bits 23:16] SGX_SVN_SINIT. See Section 41.11.3, "Interactions with
/// Authenticated Code Modules (ACMs)".
///
UINT32 SGX_SVN_SINIT:8;
@@ -4925,16 +4916,11 @@ typedef union {
/**
DS Save Area (R/W) Points to the linear address of the first byte of the DS
DS Save Area (R/W) Points to the linear address of the first byte of the DS
buffer management area, which is used to manage the BTS and PEBS buffers.
See Section 18.15.4, "Debug Store (DS) Mechanism.". If( CPUID.01H:EDX.DS[21]
= 1.
[Bits 31..0] The linear address of the first byte of the DS buffer
management area, if not in IA-32e mode.
[Bits 63..0] The linear address of the first byte of the DS buffer
management area, if IA-32e mode is active.
See Section 18.6.3.4, "Debug Store (DS) Mechanism.". If(
CPUID.01H:EDX.DS[21] = 1. The linear address of the first byte of the DS
buffer management area, if IA-32e mode is active.
@param ECX MSR_IA32_DS_AREA (0x00000600)
@param EAX Lower 32-bits of MSR value.