diff --git a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c
index 8d5d2e58a9..c13d4bb88f 100644
--- a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c
+++ b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c
@@ -52,35 +52,35 @@ STATIC LEGACY_MEMORY_SECTION_INFO   mSectionArray[] = {
 };
 
 STATIC PAM_REGISTER_VALUE  mRegisterValues440[] = {
-  {REG_PAM1_OFFSET_440, 0x01, 0x02},
-  {REG_PAM1_OFFSET_440, 0x10, 0x20},
-  {REG_PAM2_OFFSET_440, 0x01, 0x02},
-  {REG_PAM2_OFFSET_440, 0x10, 0x20},
-  {REG_PAM3_OFFSET_440, 0x01, 0x02},
-  {REG_PAM3_OFFSET_440, 0x10, 0x20},
-  {REG_PAM4_OFFSET_440, 0x01, 0x02},
-  {REG_PAM4_OFFSET_440, 0x10, 0x20},
-  {REG_PAM5_OFFSET_440, 0x01, 0x02},
-  {REG_PAM5_OFFSET_440, 0x10, 0x20},
-  {REG_PAM6_OFFSET_440, 0x01, 0x02},
-  {REG_PAM6_OFFSET_440, 0x10, 0x20},
-  {REG_PAM0_OFFSET_440, 0x10, 0x20}
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM1), 0x01, 0x02},
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM1), 0x10, 0x20},
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM2), 0x01, 0x02},
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM2), 0x10, 0x20},
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM3), 0x01, 0x02},
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM3), 0x10, 0x20},
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM4), 0x01, 0x02},
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM4), 0x10, 0x20},
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM5), 0x01, 0x02},
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM5), 0x10, 0x20},
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM6), 0x01, 0x02},
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM6), 0x10, 0x20},
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM0), 0x10, 0x20}
 };
 
 STATIC PAM_REGISTER_VALUE  mRegisterValuesQ35[] = {
-  {REG_PAM1_OFFSET_Q35, 0x01, 0x02},
-  {REG_PAM1_OFFSET_Q35, 0x10, 0x20},
-  {REG_PAM2_OFFSET_Q35, 0x01, 0x02},
-  {REG_PAM2_OFFSET_Q35, 0x10, 0x20},
-  {REG_PAM3_OFFSET_Q35, 0x01, 0x02},
-  {REG_PAM3_OFFSET_Q35, 0x10, 0x20},
-  {REG_PAM4_OFFSET_Q35, 0x01, 0x02},
-  {REG_PAM4_OFFSET_Q35, 0x10, 0x20},
-  {REG_PAM5_OFFSET_Q35, 0x01, 0x02},
-  {REG_PAM5_OFFSET_Q35, 0x10, 0x20},
-  {REG_PAM6_OFFSET_Q35, 0x01, 0x02},
-  {REG_PAM6_OFFSET_Q35, 0x10, 0x20},
-  {REG_PAM0_OFFSET_Q35, 0x10, 0x20}
+  {DRAMC_REGISTER_Q35 (MCH_PAM1), 0x01, 0x02},
+  {DRAMC_REGISTER_Q35 (MCH_PAM1), 0x10, 0x20},
+  {DRAMC_REGISTER_Q35 (MCH_PAM2), 0x01, 0x02},
+  {DRAMC_REGISTER_Q35 (MCH_PAM2), 0x10, 0x20},
+  {DRAMC_REGISTER_Q35 (MCH_PAM3), 0x01, 0x02},
+  {DRAMC_REGISTER_Q35 (MCH_PAM3), 0x10, 0x20},
+  {DRAMC_REGISTER_Q35 (MCH_PAM4), 0x01, 0x02},
+  {DRAMC_REGISTER_Q35 (MCH_PAM4), 0x10, 0x20},
+  {DRAMC_REGISTER_Q35 (MCH_PAM5), 0x01, 0x02},
+  {DRAMC_REGISTER_Q35 (MCH_PAM5), 0x10, 0x20},
+  {DRAMC_REGISTER_Q35 (MCH_PAM6), 0x01, 0x02},
+  {DRAMC_REGISTER_Q35 (MCH_PAM6), 0x10, 0x20},
+  {DRAMC_REGISTER_Q35 (MCH_PAM0), 0x10, 0x20}
 };
 
 STATIC PAM_REGISTER_VALUE *mRegisterValues;
@@ -145,12 +145,12 @@ LegacyRegionManipulationInternal (
     if (ReadEnable != NULL) {
       if (*ReadEnable) {
         PciOr8 (
-          PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset),
+          mRegisterValues[Index].PAMRegPciLibAddress,
           mRegisterValues[Index].ReadEnableData
           );
       } else {
         PciAnd8 (
-          PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset),
+          mRegisterValues[Index].PAMRegPciLibAddress,
           (UINT8) (~mRegisterValues[Index].ReadEnableData)
           );
       }
@@ -158,12 +158,12 @@ LegacyRegionManipulationInternal (
     if (WriteEnable != NULL) {
       if (*WriteEnable) {
         PciOr8 (
-          PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset),
+          mRegisterValues[Index].PAMRegPciLibAddress,
           mRegisterValues[Index].WriteEnableData
           );
       } else {
         PciAnd8 (
-          PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset),
+          mRegisterValues[Index].PAMRegPciLibAddress,
           (UINT8) (~mRegisterValues[Index].WriteEnableData)
           );
       }
@@ -204,7 +204,7 @@ LegacyRegionGetInfoInternal (
   //
   *DescriptorCount = sizeof(mSectionArray) / sizeof (mSectionArray[0]);
   for (Index = 0; Index < *DescriptorCount; Index++) {
-    PamValue = PciRead8 (PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset));
+    PamValue = PciRead8 (mRegisterValues[Index].PAMRegPciLibAddress);
     mSectionArray[Index].ReadEnabled = FALSE;
     if ((PamValue & mRegisterValues[Index].ReadEnableData) != 0) {
       mSectionArray[Index].ReadEnabled = TRUE;
diff --git a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h
index f755a2a359..01d3109a7d 100644
--- a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h
+++ b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h
@@ -30,26 +30,6 @@
 #include <Library/MemoryAllocationLib.h>
 #include <Library/UefiBootServicesTableLib.h>
 
-#define PAM_PCI_BUS        0
-#define PAM_PCI_DEV        0
-#define PAM_PCI_FUNC       0
-
-#define REG_PAM0_OFFSET_440    0x59    // Programmable Attribute Map 0
-#define REG_PAM1_OFFSET_440    0x5a    // Programmable Attribute Map 1
-#define REG_PAM2_OFFSET_440    0x5b    // Programmable Attribute Map 2
-#define REG_PAM3_OFFSET_440    0x5c    // Programmable Attribute Map 3
-#define REG_PAM4_OFFSET_440    0x5d    // Programmable Attribute Map 4
-#define REG_PAM5_OFFSET_440    0x5e    // Programmable Attribute Map 5
-#define REG_PAM6_OFFSET_440    0x5f    // Programmable Attribute Map 6
-
-#define REG_PAM0_OFFSET_Q35    0x90    // Programmable Attribute Map 0
-#define REG_PAM1_OFFSET_Q35    0x91    // Programmable Attribute Map 1
-#define REG_PAM2_OFFSET_Q35    0x92    // Programmable Attribute Map 2
-#define REG_PAM3_OFFSET_Q35    0x93    // Programmable Attribute Map 3
-#define REG_PAM4_OFFSET_Q35    0x94    // Programmable Attribute Map 4
-#define REG_PAM5_OFFSET_Q35    0x95    // Programmable Attribute Map 5
-#define REG_PAM6_OFFSET_Q35    0x96    // Programmable Attribute Map 6
-
 #define PAM_BASE_ADDRESS   0xc0000
 #define PAM_LIMIT_ADDRESS  BASE_1MB
 
@@ -67,7 +47,7 @@ typedef struct {
 // Provides a map of the PAM registers and bits used to set Read/Write access.
 //
 typedef struct {
-  UINT8   PAMRegOffset;
+  UINTN   PAMRegPciLibAddress;
   UINT8   ReadEnableData;
   UINT8   WriteEnableData;
 } PAM_REGISTER_VALUE;
diff --git a/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h b/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h
index baa4c063f1..efe6e5c278 100644
--- a/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h
+++ b/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h
@@ -27,6 +27,19 @@
 //
 #define INTEL_82441_DEVICE_ID 0x1237
 
+//
+// B/D/F/Type: 0/0/0/PCI
+//
+#define PMC_REGISTER_PIIX4(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))
+
+#define PIIX4_PAM0              0x59
+#define PIIX4_PAM1              0x5A
+#define PIIX4_PAM2              0x5B
+#define PIIX4_PAM3              0x5C
+#define PIIX4_PAM4              0x5D
+#define PIIX4_PAM5              0x5E
+#define PIIX4_PAM6              0x5F
+
 //
 // B/D/F/Type: 0/1/3/PCI
 //
diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
index 68485bec71..193a262e5b 100644
--- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
+++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
@@ -47,6 +47,14 @@
 #define MCH_PCIEXBAR_HIGH     0x64
 #define MCH_PCIEXBAR_HIGHMASK   0xFFFFFFF0
 
+#define MCH_PAM0              0x90
+#define MCH_PAM1              0x91
+#define MCH_PAM2              0x92
+#define MCH_PAM3              0x93
+#define MCH_PAM4              0x94
+#define MCH_PAM5              0x95
+#define MCH_PAM6              0x96
+
 #define MCH_SMRAM             0x9D
 #define MCH_SMRAM_D_LCK         BIT4
 #define MCH_SMRAM_G_SMRAME      BIT3