Cleanup MMU code to do book required sync. Update exception handler to clear fault registers.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10366 6f19259b-4bc3-4df7-8a09-765794883524
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@@ -1,6 +1,6 @@
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//------------------------------------------------------------------------------
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//
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// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
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// Copyright (c) 2008-2010 Apple Inc. All rights reserved.
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//
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// All rights reserved. This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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@@ -25,6 +25,7 @@
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EXPORT ArmSetTranslationTableBaseAddress
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EXPORT ArmGetTranslationTableBaseAddress
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EXPORT ArmSetDomainAccessControl
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EXPORT ArmUpdateTranslationTableEntry
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EXPORT CPSRMaskInsert
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EXPORT CPSRRead
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EXPORT ReadCCSIDR
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@@ -32,6 +33,9 @@
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AREA ArmLibSupport, CODE, READONLY
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//------------------------------------------------------------------------------
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Cp15IdCode
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mrc p15,0,R0,c0,c0,0
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bx LR
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@@ -41,11 +45,11 @@ Cp15CacheInfo
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bx LR
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ArmEnableInterrupts
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CPSIE i
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cpsie i
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bx LR
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ArmDisableInterrupts
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CPSID i
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cpsid i
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bx LR
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ArmGetInterruptState
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@@ -54,18 +58,18 @@ ArmGetInterruptState
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moveq R0,#1
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movne R0,#0
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bx LR
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ArmEnableFiq
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CPSIE f
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cpsie f
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bx LR
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ArmDisableFiq
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CPSID f
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cpsid f
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bx LR
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ArmGetFiqState
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mrs R0,CPSR
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tst R0,#0x40 ;Check if IRQ is enabled.
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tst R0,#0x40 ;Check if FIQ is enabled.
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moveq R0,#1
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movne R0,#0
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bx LR
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@@ -73,22 +77,40 @@ ArmGetFiqState
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ArmInvalidateTlb
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mov r0,#0
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mcr p15,0,r0,c8,c7,0
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ISB
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mcr p15,0,R9,c7,c5,6 ; BPIALL Invalidate Branch predictor array. R9 == NoOp
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dsb
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isb
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bx lr
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ArmSetTranslationTableBaseAddress
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mcr p15,0,r0,c2,c0,0
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ISB
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isb
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bx lr
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ArmGetTranslationTableBaseAddress
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mrc p15,0,r0,c2,c0,0
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ISB
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isb
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bx lr
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ArmSetDomainAccessControl
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mcr p15,0,r0,c3,c0,0
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ISB
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isb
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bx lr
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//
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//VOID
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//ArmUpdateTranslationTableEntry (
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// IN VOID *TranslationTableEntry // R0
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// IN VOID *MVA // R1
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// );
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ArmUpdateTranslationTableEntry
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mcr p15,0,R0,c7,c14,1 ; DCCIMVAC Clean data cache by MVA
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dsb
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mcr p15,0,R1,c8,c7,1 ; TLBIMVA TLB Invalidate MVA
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mcr p15,0,R9,c7,c5,6 ; BPIALL Invalidate Branch predictor array. R9 == NoOp
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dsb
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isb
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bx lr
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CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert
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@@ -99,7 +121,7 @@ CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to in
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and r1, r1, r0 ; clear bits outside the mask in the input
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orr r2, r2, r1 ; set field
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msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch)
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ISB
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isb
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mov sp, r3 ; restore stack pointer
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ldmfd sp!, {r4-r12, lr} ; restore registers
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bx lr ; return (hopefully thumb-safe!)
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@@ -114,10 +136,10 @@ CPSRRead
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// IN UINT32 CSSELR
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// )
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ReadCCSIDR
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MCR p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)
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ISB
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MRC p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
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BX lr
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mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)
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isb
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mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
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bx lr
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// UINT32
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@@ -125,7 +147,10 @@ ReadCCSIDR
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// IN UINT32 CSSELR
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// )
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ReadCLIDR
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MRC p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
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END
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mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
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bx lr
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END
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