From bb19b4bc301f71c03873b0797950f218607c30cf Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Sun, 20 Feb 2022 14:22:46 +0100 Subject: [PATCH] UefiPayloadPkg/Include/Coreboot: Add headers for SMMSTOREv2 table Since commit bc744f5893fc4d53275ed26dd8d968011c6a09c1 coreboot supports the SMMSTORE v2 feature. It implements a SMI handler that is able to write, read and erase pages in the boot media (SPI flash). The existence of this optional feature is advertised by a coreboot table. Add the tag and headers to parse the table. Cc: Guo Dong Cc: Ray Ni Cc: Maurice Ma Cc: Benjamin You Cc: Sean Rhodes Signed-off-by: Patrick Rudolph Change-Id: I02be3fa8d5d6ff47d56b81876590afef8f6c43c0 --- UefiPayloadPkg/Include/Coreboot.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/UefiPayloadPkg/Include/Coreboot.h b/UefiPayloadPkg/Include/Coreboot.h index a3e1109fe8..617e5e9bc0 100644 --- a/UefiPayloadPkg/Include/Coreboot.h +++ b/UefiPayloadPkg/Include/Coreboot.h @@ -236,6 +236,19 @@ struct cb_cbmem_tab { UINT64 cbmem_tab; }; +#define CB_TAG_SMMSTOREV2 0x0039 +struct cb_smmstorev2 { + UINT32 tag; + UINT32 size; + UINT32 num_blocks; /* Number of writeable blocks in Smm */ + UINT32 block_size; /* Size of a block in byte. Default: 64 KiB */ + UINT32 mmap_addr; /* MMIO address of the store for read only access */ + UINT32 com_buffer; /* Physical address of the communication buffer */ + UINT32 com_buffer_size; /* Size of the communication buffer in byte */ + UINT8 apm_cmd; /* The command byte to write to the APM I/O port */ + UINT8 unused[3]; /* Set to zero */ +}; + /* Helpful macros */ #define MEM_RANGE_COUNT(_rec) \