ArmPlatformPkg: Increase more ARM address Pcd entries to 64-bit.
Some AArch64 platforms have RAM and flash devices >4GB. Update some additional Pcd entries to 64-bit, and change the corresponding PcdGet32 calls to PcdGet64. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16325 6f19259b-4bc3-4df7-8a09-765794883524
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oliviermartin
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2a7e98a8cc
commit
bb5420bb2b
@@ -34,7 +34,7 @@ ArmPlatformGetGlobalVariable (
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// Ensure the Global Variable Size have been initialized
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ASSERT (VariableOffset < PcdGet32 (PcdPeiGlobalVariableSize));
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GlobalVariableBase = PcdGet32 (PcdCPUCoresStackBase) + PcdGet32 (PcdCPUCorePrimaryStackSize) - PcdGet32 (PcdPeiGlobalVariableSize);
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GlobalVariableBase = PcdGet64 (PcdCPUCoresStackBase) + PcdGet32 (PcdCPUCorePrimaryStackSize) - PcdGet32 (PcdPeiGlobalVariableSize);
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if (VariableSize == 4) {
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*(UINT32*)Variable = ReadUnaligned32 ((CONST UINT32*)(GlobalVariableBase + VariableOffset));
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@@ -57,7 +57,7 @@ ArmPlatformSetGlobalVariable (
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// Ensure the Global Variable Size have been initialized
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ASSERT (VariableOffset < PcdGet32 (PcdPeiGlobalVariableSize));
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GlobalVariableBase = PcdGet32 (PcdCPUCoresStackBase) + PcdGet32 (PcdCPUCorePrimaryStackSize) - PcdGet32 (PcdPeiGlobalVariableSize);
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GlobalVariableBase = PcdGet64 (PcdCPUCoresStackBase) + PcdGet32 (PcdCPUCorePrimaryStackSize) - PcdGet32 (PcdPeiGlobalVariableSize);
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if (VariableSize == 4) {
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WriteUnaligned32 ((UINT32*)(GlobalVariableBase + VariableOffset), *(UINT32*)Variable);
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@@ -78,7 +78,7 @@ ArmPlatformGetGlobalVariableAddress (
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// Ensure the Global Variable Size have been initialized
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ASSERT (VariableOffset < PcdGet32 (PcdPeiGlobalVariableSize));
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GlobalVariableBase = PcdGet32 (PcdCPUCoresStackBase) + PcdGet32 (PcdCPUCorePrimaryStackSize) - PcdGet32 (PcdPeiGlobalVariableSize);
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GlobalVariableBase = PcdGet64 (PcdCPUCoresStackBase) + PcdGet32 (PcdCPUCorePrimaryStackSize) - PcdGet32 (PcdPeiGlobalVariableSize);
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return (VOID*)(GlobalVariableBase + VariableOffset);
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}
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@@ -19,8 +19,8 @@
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#include <Library/PcdLib.h>
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#include <Library/DebugLib.h>
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#define IS_XIP() (((UINT32)PcdGet32 (PcdFdBaseAddress) > (UINT32)(PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize))) || \
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((PcdGet32 (PcdFdBaseAddress) + PcdGet32 (PcdFdSize)) < PcdGet64 (PcdSystemMemoryBase)))
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#define IS_XIP() (((UINT32)PcdGet64 (PcdFdBaseAddress) > (UINT32)(PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize))) || \
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((PcdGet64 (PcdFdBaseAddress) + PcdGet32 (PcdFdSize)) < PcdGet64 (PcdSystemMemoryBase)))
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// Declared by ArmPlatformPkg/PrePi Module
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extern UINTN mGlobalVariableBase;
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@@ -1,6 +1,6 @@
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/** @file
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*
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* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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@@ -70,5 +70,5 @@ ArmPlatformSecExtraAction (
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OUT UINTN* JumpAddress
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)
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{
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*JumpAddress = PcdGet32(PcdFvBaseAddress);
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*JumpAddress = PcdGet64 (PcdFvBaseAddress);
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}
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@@ -35,7 +35,7 @@ NonSecureWaitForFirmware (
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UINTN InterruptId;
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// The secondary cores will execute the firmware once wake from WFI.
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SecondaryStart = (VOID (*)())PcdGet32 (PcdFvBaseAddress);
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SecondaryStart = (VOID (*)())(UINTN)PcdGet64 (PcdFvBaseAddress);
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ArmCallWFI ();
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@@ -69,6 +69,7 @@ ArmPlatformSecExtraAction (
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{
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CHAR8 Buffer[100];
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UINTN CharCount;
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UINTN* StartAddress;
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if (FeaturePcdGet (PcdStandalone) == FALSE) {
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@@ -77,7 +78,7 @@ ArmPlatformSecExtraAction (
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//
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if (ArmPlatformIsPrimaryCore (MpId)) {
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UINTN* StartAddress = (UINTN*)PcdGet32(PcdFvBaseAddress);
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StartAddress = (UINTN*)(UINTN)PcdGet64 (PcdFvBaseAddress);
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// Patch the DRAM to make an infinite loop at the start address
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*StartAddress = 0xEAFFFFFE; // opcode for while(1)
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@@ -85,7 +86,7 @@ ArmPlatformSecExtraAction (
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CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Waiting for firmware at 0x%08X ...\n\r",StartAddress);
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SerialPortWrite ((UINT8 *) Buffer, CharCount);
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*JumpAddress = PcdGet32(PcdFvBaseAddress);
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*JumpAddress = PcdGet64 (PcdFvBaseAddress);
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} else {
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// When the primary core is stopped by the hardware debugger to copy the firmware
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// into DRAM. The secondary cores are still running. As soon as the first bytes of
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@@ -104,10 +105,10 @@ ArmPlatformSecExtraAction (
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if (ArmPlatformIsPrimaryCore (MpId)) {
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// Signal the secondary cores they can jump to PEI phase
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ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));
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ArmGicSendSgiTo (PcdGet32 (PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));
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// To enter into Non Secure state, we need to make a return from exception
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*JumpAddress = PcdGet32(PcdFvBaseAddress);
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*JumpAddress = PcdGet64 (PcdFvBaseAddress);
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} else {
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// We wait for the primary core to finish to initialize the System Memory. Otherwise the secondary
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// cores would make crash the system by setting their stacks in DRAM before the primary core has not
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@@ -115,6 +116,6 @@ ArmPlatformSecExtraAction (
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*JumpAddress = (UINTN)NonSecureWaitForFirmware;
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}
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} else {
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*JumpAddress = PcdGet32(PcdFvBaseAddress);
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*JumpAddress = PcdGet64 (PcdFvBaseAddress);
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}
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}
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