UefiPayloadPkg: Add PCI support from DuetPkg
In coreboot, we mark GPU prefmem above 4GB, because NVIDIA wants a lot
(16GB region on the 30 series), otherwise coreboot will obviously fail
to allocate the resources.
In EDK2, we then end up hitting this assert:
InitRootBridge: populated root bus 0, with room for 36 subordinate bus(es)
RootBridge: PciRoot(0x0)
Support/Attr: 7001F / 7001F
DmaAbove4G: No
NoExtConfSpace: No
AllocAttr: 0 ()
Bus: 0 - 24 Translation=0
Io: 1000 - EFFF Translation=0
Mem: 80400000 - 1001FFFFFF Translation=0
MemAbove4G: FFFFFFFFFFFFFFFF - 0 Translation=0
PMem: FFFFFFFFFFFFFFFF - 0 Translation=0
PMemAbove4G: FFFFFFFFFFFFFFFF - 0 Translation=0
ASSERT [PciHostBridgeDxe] .../edk2/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c(120): Bridge->Mem.Limit < 0x0000000100000000ULL
So, bring back Pci*NoEnumerationDxe from the deleted DuetPkg, which
doesn't check anything and let's us boot.
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
453
UefiPayloadPkg/PciBusNoEnumerationDxe/PciCommand.c
Normal file
453
UefiPayloadPkg/PciBusNoEnumerationDxe/PciCommand.c
Normal file
@@ -0,0 +1,453 @@
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/*++
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Copyright (c) 2005 - 2006, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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PciCommand.c
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Abstract:
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PCI Bus Driver
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Revision History
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--*/
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#include "PciBus.h"
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EFI_STATUS
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PciReadCommandRegister (
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IN PCI_IO_DEVICE *PciIoDevice,
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OUT UINT16 *Command
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)
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/*++
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Routine Description:
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Arguments:
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Returns:
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None
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--*/
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{
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EFI_PCI_IO_PROTOCOL *PciIo;
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*Command = 0;
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PciIo = &PciIoDevice->PciIo;
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return PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint16,
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PCI_COMMAND_OFFSET,
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1,
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Command
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);
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}
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EFI_STATUS
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PciSetCommandRegister (
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IN PCI_IO_DEVICE *PciIoDevice,
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IN UINT16 Command
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)
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/*++
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Routine Description:
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Arguments:
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Returns:
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None
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--*/
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{
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UINT16 Temp;
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EFI_PCI_IO_PROTOCOL *PciIo;
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Temp = Command;
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PciIo = &PciIoDevice->PciIo;
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return PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint16,
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PCI_COMMAND_OFFSET,
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1,
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&Temp
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);
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}
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EFI_STATUS
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PciEnableCommandRegister (
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IN PCI_IO_DEVICE *PciIoDevice,
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IN UINT16 Command
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)
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/*++
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Routine Description:
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Arguments:
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Returns:
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None
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--*/
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{
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UINT16 OldCommand;
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EFI_PCI_IO_PROTOCOL *PciIo;
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OldCommand = 0;
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PciIo = &PciIoDevice->PciIo;
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PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint16,
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PCI_COMMAND_OFFSET,
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1,
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&OldCommand
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);
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OldCommand = (UINT16) (OldCommand | Command);
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return PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint16,
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PCI_COMMAND_OFFSET,
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1,
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&OldCommand
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);
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}
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EFI_STATUS
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PciDisableCommandRegister (
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IN PCI_IO_DEVICE *PciIoDevice,
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IN UINT16 Command
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)
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/*++
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Routine Description:
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Arguments:
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Returns:
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None
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--*/
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{
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UINT16 OldCommand;
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EFI_PCI_IO_PROTOCOL *PciIo;
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OldCommand = 0;
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PciIo = &PciIoDevice->PciIo;
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PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint16,
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PCI_COMMAND_OFFSET,
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1,
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&OldCommand
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);
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OldCommand = (UINT16) (OldCommand & ~(Command));
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return PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint16,
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PCI_COMMAND_OFFSET,
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1,
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&OldCommand
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);
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}
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EFI_STATUS
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PciSetBridgeControlRegister (
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IN PCI_IO_DEVICE *PciIoDevice,
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IN UINT16 Command
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)
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/*++
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Routine Description:
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Arguments:
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Returns:
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None
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--*/
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{
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UINT16 Temp;
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EFI_PCI_IO_PROTOCOL *PciIo;
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Temp = Command;
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PciIo = &PciIoDevice->PciIo;
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return PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint16,
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PCI_BRIDGE_CONTROL_REGISTER_OFFSET,
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1,
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&Temp
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);
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}
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EFI_STATUS
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PciEnableBridgeControlRegister (
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IN PCI_IO_DEVICE *PciIoDevice,
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IN UINT16 Command
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)
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/*++
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Routine Description:
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Arguments:
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Returns:
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None
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--*/
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{
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UINT16 OldCommand;
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EFI_PCI_IO_PROTOCOL *PciIo;
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OldCommand = 0;
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PciIo = &PciIoDevice->PciIo;
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PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint16,
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PCI_BRIDGE_CONTROL_REGISTER_OFFSET,
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1,
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&OldCommand
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);
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OldCommand = (UINT16) (OldCommand | Command);
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return PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint16,
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PCI_BRIDGE_CONTROL_REGISTER_OFFSET,
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1,
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&OldCommand
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);
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}
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EFI_STATUS
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PciDisableBridgeControlRegister (
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IN PCI_IO_DEVICE *PciIoDevice,
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IN UINT16 Command
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)
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/*++
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Routine Description:
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Arguments:
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Returns:
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None
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--*/
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{
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UINT16 OldCommand;
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EFI_PCI_IO_PROTOCOL *PciIo;
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OldCommand = 0;
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PciIo = &PciIoDevice->PciIo;
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PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint16,
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PCI_BRIDGE_CONTROL_REGISTER_OFFSET,
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1,
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&OldCommand
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);
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OldCommand = (UINT16) (OldCommand & ~(Command));
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return PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint16,
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PCI_BRIDGE_CONTROL_REGISTER_OFFSET,
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1,
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&OldCommand
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);
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}
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EFI_STATUS
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PciReadBridgeControlRegister (
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IN PCI_IO_DEVICE *PciIoDevice,
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OUT UINT16 *Command
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)
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/*++
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Routine Description:
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Arguments:
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Returns:
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None
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--*/
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{
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EFI_PCI_IO_PROTOCOL *PciIo;
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*Command = 0;
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PciIo = &PciIoDevice->PciIo;
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return PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint16,
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PCI_BRIDGE_CONTROL_REGISTER_OFFSET,
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1,
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Command
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);
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}
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BOOLEAN
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PciCapabilitySupport (
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IN PCI_IO_DEVICE *PciIoDevice
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)
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/*++
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Routine Description:
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Arguments:
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Returns:
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None
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--*/
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// TODO: PciIoDevice - add argument and description to function comment
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{
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if (PciIoDevice->Pci.Hdr.Status & EFI_PCI_STATUS_CAPABILITY) {
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return TRUE;
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}
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return FALSE;
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}
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EFI_STATUS
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LocateCapabilityRegBlock (
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IN PCI_IO_DEVICE *PciIoDevice,
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IN UINT8 CapId,
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IN OUT UINT8 *Offset,
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OUT UINT8 *NextRegBlock OPTIONAL
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)
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/*++
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Routine Description:
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Locate Capability register.
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Arguments:
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PciIoDevice - A pointer to the PCI_IO_DEVICE.
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CapId - The capability ID.
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Offset - A pointer to the offset.
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As input: the default offset;
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As output: the offset of the found block.
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NextRegBlock - An optional pointer to return the value of next block.
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Returns:
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EFI_UNSUPPORTED - The Pci Io device is not supported.
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EFI_NOT_FOUND - The Pci Io device cannot be found.
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EFI_SUCCESS - The Pci Io device is successfully located.
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--*/
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{
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UINT8 CapabilityPtr;
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UINT16 CapabilityEntry;
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UINT8 CapabilityID;
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//
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// To check the capability of this device supports
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//
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if (!PciCapabilitySupport (PciIoDevice)) {
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return EFI_UNSUPPORTED;
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}
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if (*Offset != 0) {
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CapabilityPtr = *Offset;
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} else {
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CapabilityPtr = 0;
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if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
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PciIoDevice->PciIo.Pci.Read (
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&PciIoDevice->PciIo,
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EfiPciIoWidthUint8,
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EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR,
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1,
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&CapabilityPtr
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);
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} else {
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PciIoDevice->PciIo.Pci.Read (
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&PciIoDevice->PciIo,
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EfiPciIoWidthUint8,
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PCI_CAPBILITY_POINTER_OFFSET,
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1,
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&CapabilityPtr
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);
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}
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}
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while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {
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PciIoDevice->PciIo.Pci.Read (
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&PciIoDevice->PciIo,
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EfiPciIoWidthUint16,
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CapabilityPtr,
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1,
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&CapabilityEntry
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);
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CapabilityID = (UINT8) CapabilityEntry;
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if (CapabilityID == CapId) {
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*Offset = CapabilityPtr;
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if (NextRegBlock != NULL) {
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*NextRegBlock = (UINT8) (CapabilityEntry >> 8);
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}
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return EFI_SUCCESS;
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}
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CapabilityPtr = (UINT8) (CapabilityEntry >> 8);
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}
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return EFI_NOT_FOUND;
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}
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