ArmPkg/ArmLib: Clean ArmV7Lib
- Move the non specific ArmV7 functions to ArmLib. - Clean the ARM Platform common components to not depend on ArmV7 if not required git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12453 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
@@ -1,357 +1,334 @@
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//------------------------------------------------------------------------------
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//
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// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//------------------------------------------------------------------------------
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EXPORT ArmInvalidateInstructionCache
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EXPORT ArmInvalidateDataCacheEntryByMVA
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EXPORT ArmCleanDataCacheEntryByMVA
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EXPORT ArmCleanInvalidateDataCacheEntryByMVA
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EXPORT ArmInvalidateDataCacheEntryBySetWay
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EXPORT ArmCleanDataCacheEntryBySetWay
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EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
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EXPORT ArmDrainWriteBuffer
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EXPORT ArmEnableMmu
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EXPORT ArmDisableMmu
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EXPORT ArmDisableCachesAndMmu
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EXPORT ArmMmuEnabled
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EXPORT ArmEnableDataCache
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EXPORT ArmDisableDataCache
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EXPORT ArmEnableInstructionCache
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EXPORT ArmDisableInstructionCache
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EXPORT ArmEnableSWPInstruction
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EXPORT ArmEnableBranchPrediction
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EXPORT ArmDisableBranchPrediction
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EXPORT ArmSetLowVectors
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EXPORT ArmSetHighVectors
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EXPORT ArmV7AllDataCachesOperation
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EXPORT ArmDataMemoryBarrier
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EXPORT ArmDataSyncronizationBarrier
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EXPORT ArmInstructionSynchronizationBarrier
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EXPORT ArmWriteNsacr
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EXPORT ArmWriteScr
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EXPORT ArmWriteVMBar
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EXPORT ArmWriteVBar
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EXPORT ArmReadVBar
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EXPORT ArmWriteCPACR
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EXPORT ArmEnableVFP
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EXPORT ArmCallWFI
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EXPORT ArmWriteAuxCr
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EXPORT ArmReadAuxCr
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EXPORT ArmReadCbar
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EXPORT ArmInvalidateInstructionAndDataTlb
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EXPORT ArmReadMpidr
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EXPORT ArmReadTpidrurw
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EXPORT ArmWriteTpidrurw
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AREA ArmCacheLib, CODE, READONLY
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PRESERVE8
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DC_ON EQU ( 0x1:SHL:2 )
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IC_ON EQU ( 0x1:SHL:12 )
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CTRL_M_BIT EQU (1 << 0)
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CTRL_C_BIT EQU (1 << 2)
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CTRL_B_BIT EQU (1 << 7)
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CTRL_I_BIT EQU (1 << 12)
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ArmInvalidateDataCacheEntryByMVA
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mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
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dsb
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isb
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bx lr
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ArmCleanDataCacheEntryByMVA
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mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
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dsb
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isb
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bx lr
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ArmCleanInvalidateDataCacheEntryByMVA
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mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
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dsb
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isb
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bx lr
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ArmInvalidateDataCacheEntryBySetWay
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mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
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dsb
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isb
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bx lr
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ArmCleanInvalidateDataCacheEntryBySetWay
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mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
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dsb
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isb
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bx lr
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ArmCleanDataCacheEntryBySetWay
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mcr p15, 0, r0, c7, c10, 2 ; Clean this line
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dsb
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isb
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bx lr
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ArmInvalidateInstructionCache
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mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
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isb
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bx LR
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ArmEnableMmu
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mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
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orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU
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mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
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dsb
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isb
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bx LR
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ArmMmuEnabled
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mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
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and R0,R0,#1
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bx LR
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ArmDisableMmu
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mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
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bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU
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mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
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mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB
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mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array
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dsb
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isb
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bx LR
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ArmDisableCachesAndMmu
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mrc p15, 0, r0, c1, c0, 0 ; Get control register
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bic r0, r0, #CTRL_M_BIT ; Disable MMU
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bic r0, r0, #CTRL_C_BIT ; Disable D Cache
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bic r0, r0, #CTRL_I_BIT ; Disable I Cache
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mcr p15, 0, r0, c1, c0, 0 ; Write control register
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dsb
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isb
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bx LR
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ArmEnableDataCache
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ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
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mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
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orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled
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mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
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dsb
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isb
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bx LR
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ArmDisableDataCache
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ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
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mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
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bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled
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mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
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isb
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bx LR
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ArmEnableInstructionCache
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ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
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mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
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orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled
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mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
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dsb
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isb
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bx LR
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ArmDisableInstructionCache
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ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
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mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
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BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled
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mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
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isb
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bx LR
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ArmEnableSWPInstruction
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #0x00000400
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mcr p15, 0, r0, c1, c0, 0
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isb
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bx LR
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ArmEnableBranchPrediction
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mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
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orr r0, r0, #0x00000800 ;
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mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
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isb
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bx LR
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ArmDisableBranchPrediction
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mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
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bic r0, r0, #0x00000800 ;
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mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
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isb
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bx LR
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ArmSetLowVectors
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mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
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bic r0, r0, #0x00002000 ; clear V bit
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mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
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isb
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bx LR
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ArmSetHighVectors
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mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
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orr r0, r0, #0x00002000 ; clear V bit
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mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
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isb
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bx LR
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ArmV7AllDataCachesOperation
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stmfd SP!,{r4-r12, LR}
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mov R1, R0 ; Save Function call in R1
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mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR
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ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)
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mov R3, R3, LSR #23 ; Cache level value (naturally aligned)
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beq Finished
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mov R10, #0
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Loop1
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add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
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mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
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and R12, R12, #7 ; get those 3 bits alone
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cmp R12, #2
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blt Skip ; no cache or only instruction cache at this level
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mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
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isb ; isb to sync the change to the CacheSizeID reg
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mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
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and R2, R12, #&7 ; extract the line length field
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add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
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ldr R4, =0x3FF
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ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
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clz R5, R4 ; R5 is the bit position of the way size increment
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ldr R7, =0x00007FFF
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ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
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Loop2
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mov R9, R4 ; R9 working copy of the max way size (right aligned)
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Loop3
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orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11
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orr R0, R0, R7, LSL R2 ; factor in the index number
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blx R1
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subs R9, R9, #1 ; decrement the way number
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bge Loop3
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subs R7, R7, #1 ; decrement the index
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bge Loop2
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Skip
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add R10, R10, #2 ; increment the cache number
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cmp R3, R10
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bgt Loop1
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Finished
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dsb
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ldmfd SP!, {r4-r12, lr}
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bx LR
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ArmDataMemoryBarrier
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dmb
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bx LR
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ArmDataSyncronizationBarrier
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ArmDrainWriteBuffer
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dsb
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bx LR
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ArmInstructionSynchronizationBarrier
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isb
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bx LR
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ArmWriteNsacr
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mcr p15, 0, r0, c1, c1, 2
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bx lr
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ArmWriteScr
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mcr p15, 0, r0, c1, c1, 0
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bx lr
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ArmWriteAuxCr
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mcr p15, 0, r0, c1, c0, 1
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bx lr
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ArmReadAuxCr
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mrc p15, 0, r0, c1, c0, 1
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bx lr
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ArmWriteVMBar
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mcr p15, 0, r0, c12, c0, 1
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bx lr
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ArmWriteVBar
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// Set the Address of the Vector Table in the VBAR register
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mcr p15, 0, r0, c12, c0, 0
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// Ensure the SCTLR.V bit is clear
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mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
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bic r0, r0, #0x00002000 ; clear V bit
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mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
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isb
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bx lr
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ArmReadVBar
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mrc p15, 0, r0, c12, c0, 0
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bx lr
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ArmWriteCPACR
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mcr p15, 0, r0, c1, c0, 2
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bx lr
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ArmEnableVFP
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// Read CPACR (Coprocessor Access Control Register)
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mrc p15, 0, r0, c1, c0, 2
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// Enable VPF access (Full Access to CP10, CP11) (V* instructions)
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orr r0, r0, #0x00f00000
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// Write back CPACR (Coprocessor Access Control Register)
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mcr p15, 0, r0, c1, c0, 2
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// Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
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mov r0, #0x40000000
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mcr p10,#0x7,r0,c8,c0,#0
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bx lr
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ArmCallWFI
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wfi
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bx lr
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//Note: Return 0 in Uniprocessor implementation
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ArmReadCbar
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mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register
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bx lr
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ArmInvalidateInstructionAndDataTlb
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mcr p15, 0, r0, c8, c7, 0 ; Invalidate Inst TLB and Data TLB
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dsb
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bx lr
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ArmReadMpidr
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mrc p15, 0, r0, c0, c0, 5 ; read MPIDR
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bx lr
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ArmReadTpidrurw
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mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW
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bx lr
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ArmWriteTpidrurw
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mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW
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bx lr
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END
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//------------------------------------------------------------------------------
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//
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// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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||||
// Copyright (c) 2011, ARM Limited. All rights reserved.
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||||
//
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// This program and the accompanying materials
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||||
// are licensed and made available under the terms and conditions of the BSD License
|
||||
// which accompanies this distribution. The full text of the license may be found at
|
||||
// http://opensource.org/licenses/bsd-license.php
|
||||
//
|
||||
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
//
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//------------------------------------------------------------------------------
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EXPORT ArmInvalidateInstructionCache
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EXPORT ArmInvalidateDataCacheEntryByMVA
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EXPORT ArmCleanDataCacheEntryByMVA
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EXPORT ArmCleanInvalidateDataCacheEntryByMVA
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EXPORT ArmInvalidateDataCacheEntryBySetWay
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EXPORT ArmCleanDataCacheEntryBySetWay
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EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
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EXPORT ArmDrainWriteBuffer
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EXPORT ArmEnableMmu
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EXPORT ArmDisableMmu
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EXPORT ArmDisableCachesAndMmu
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EXPORT ArmMmuEnabled
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EXPORT ArmEnableDataCache
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EXPORT ArmDisableDataCache
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EXPORT ArmEnableInstructionCache
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EXPORT ArmDisableInstructionCache
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EXPORT ArmEnableSWPInstruction
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EXPORT ArmEnableBranchPrediction
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EXPORT ArmDisableBranchPrediction
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EXPORT ArmSetLowVectors
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EXPORT ArmSetHighVectors
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EXPORT ArmV7AllDataCachesOperation
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EXPORT ArmDataMemoryBarrier
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EXPORT ArmDataSyncronizationBarrier
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EXPORT ArmInstructionSynchronizationBarrier
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EXPORT ArmWriteVBar
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EXPORT ArmEnableVFP
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EXPORT ArmCallWFI
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EXPORT ArmReadCbar
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EXPORT ArmInvalidateInstructionAndDataTlb
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EXPORT ArmReadMpidr
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EXPORT ArmReadTpidrurw
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EXPORT ArmWriteTpidrurw
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EXPORT ArmIsArchTimerImplemented
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EXPORT ArmReadIdPfr1
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AREA ArmV7Support, CODE, READONLY
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PRESERVE8
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DC_ON EQU ( 0x1:SHL:2 )
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IC_ON EQU ( 0x1:SHL:12 )
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CTRL_M_BIT EQU (1 << 0)
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CTRL_C_BIT EQU (1 << 2)
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CTRL_B_BIT EQU (1 << 7)
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CTRL_I_BIT EQU (1 << 12)
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ArmInvalidateDataCacheEntryByMVA
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mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
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dsb
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isb
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bx lr
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||||
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ArmCleanDataCacheEntryByMVA
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mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
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dsb
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isb
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bx lr
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ArmCleanInvalidateDataCacheEntryByMVA
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mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
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dsb
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isb
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bx lr
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ArmInvalidateDataCacheEntryBySetWay
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mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
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dsb
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isb
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bx lr
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ArmCleanInvalidateDataCacheEntryBySetWay
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mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
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dsb
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isb
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bx lr
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ArmCleanDataCacheEntryBySetWay
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mcr p15, 0, r0, c7, c10, 2 ; Clean this line
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||||
dsb
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isb
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bx lr
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||||
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ArmInvalidateInstructionCache
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mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
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||||
isb
|
||||
bx LR
|
||||
|
||||
ArmEnableMmu
|
||||
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||
orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU
|
||||
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||
dsb
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ArmDisableMmu
|
||||
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||
bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU
|
||||
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||
|
||||
mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB
|
||||
mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array
|
||||
dsb
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ArmDisableCachesAndMmu
|
||||
mrc p15, 0, r0, c1, c0, 0 ; Get control register
|
||||
bic r0, r0, #CTRL_M_BIT ; Disable MMU
|
||||
bic r0, r0, #CTRL_C_BIT ; Disable D Cache
|
||||
bic r0, r0, #CTRL_I_BIT ; Disable I Cache
|
||||
mcr p15, 0, r0, c1, c0, 0 ; Write control register
|
||||
dsb
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ArmMmuEnabled
|
||||
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||
and R0,R0,#1
|
||||
bx LR
|
||||
|
||||
ArmEnableDataCache
|
||||
ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
|
||||
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||
orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled
|
||||
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||
dsb
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ArmDisableDataCache
|
||||
ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
|
||||
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||
bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled
|
||||
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||
dsb
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ArmEnableInstructionCache
|
||||
ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
|
||||
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||
orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled
|
||||
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||
dsb
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ArmDisableInstructionCache
|
||||
ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
|
||||
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||
BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled
|
||||
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ArmEnableSWPInstruction
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
orr r0, r0, #0x00000400
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ArmEnableBranchPrediction
|
||||
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||
orr r0, r0, #0x00000800 ;
|
||||
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||
dsb
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ArmDisableBranchPrediction
|
||||
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||
bic r0, r0, #0x00000800 ;
|
||||
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||
dsb
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ArmSetLowVectors
|
||||
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||
bic r0, r0, #0x00002000 ; clear V bit
|
||||
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ArmSetHighVectors
|
||||
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||
orr r0, r0, #0x00002000 ; clear V bit
|
||||
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ArmV7AllDataCachesOperation
|
||||
stmfd SP!,{r4-r12, LR}
|
||||
mov R1, R0 ; Save Function call in R1
|
||||
mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR
|
||||
ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)
|
||||
mov R3, R3, LSR #23 ; Cache level value (naturally aligned)
|
||||
beq Finished
|
||||
mov R10, #0
|
||||
|
||||
Loop1
|
||||
add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
|
||||
mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
|
||||
and R12, R12, #7 ; get those 3 bits alone
|
||||
cmp R12, #2
|
||||
blt Skip ; no cache or only instruction cache at this level
|
||||
mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
|
||||
isb ; isb to sync the change to the CacheSizeID reg
|
||||
mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
|
||||
and R2, R12, #&7 ; extract the line length field
|
||||
add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
|
||||
ldr R4, =0x3FF
|
||||
ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
|
||||
clz R5, R4 ; R5 is the bit position of the way size increment
|
||||
ldr R7, =0x00007FFF
|
||||
ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
|
||||
|
||||
Loop2
|
||||
mov R9, R4 ; R9 working copy of the max way size (right aligned)
|
||||
|
||||
Loop3
|
||||
orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11
|
||||
orr R0, R0, R7, LSL R2 ; factor in the index number
|
||||
|
||||
blx R1
|
||||
|
||||
subs R9, R9, #1 ; decrement the way number
|
||||
bge Loop3
|
||||
subs R7, R7, #1 ; decrement the index
|
||||
bge Loop2
|
||||
Skip
|
||||
add R10, R10, #2 ; increment the cache number
|
||||
cmp R3, R10
|
||||
bgt Loop1
|
||||
|
||||
Finished
|
||||
dsb
|
||||
ldmfd SP!, {r4-r12, lr}
|
||||
bx LR
|
||||
|
||||
ArmDataMemoryBarrier
|
||||
dmb
|
||||
bx LR
|
||||
|
||||
ArmDataSyncronizationBarrier
|
||||
ArmDrainWriteBuffer
|
||||
dsb
|
||||
bx LR
|
||||
|
||||
ArmInstructionSynchronizationBarrier
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ArmWriteVBar
|
||||
// Set the Address of the Vector Table in the VBAR register
|
||||
mcr p15, 0, r0, c12, c0, 0
|
||||
// Ensure the SCTLR.V bit is clear
|
||||
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||
bic r0, r0, #0x00002000 ; clear V bit
|
||||
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||
isb
|
||||
bx lr
|
||||
|
||||
ArmEnableVFP
|
||||
// Read CPACR (Coprocessor Access Control Register)
|
||||
mrc p15, 0, r0, c1, c0, 2
|
||||
// Enable VPF access (Full Access to CP10, CP11) (V* instructions)
|
||||
orr r0, r0, #0x00f00000
|
||||
// Write back CPACR (Coprocessor Access Control Register)
|
||||
mcr p15, 0, r0, c1, c0, 2
|
||||
// Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
|
||||
mov r0, #0x40000000
|
||||
mcr p10,#0x7,r0,c8,c0,#0
|
||||
bx lr
|
||||
|
||||
ArmCallWFI
|
||||
wfi
|
||||
bx lr
|
||||
|
||||
//Note: Return 0 in Uniprocessor implementation
|
||||
ArmReadCbar
|
||||
mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register
|
||||
bx lr
|
||||
|
||||
ArmInvalidateInstructionAndDataTlb
|
||||
mcr p15, 0, r0, c8, c7, 0 ; Invalidate Inst TLB and Data TLB
|
||||
dsb
|
||||
bx lr
|
||||
|
||||
ArmReadMpidr
|
||||
mrc p15, 0, r0, c0, c0, 5 ; read MPIDR
|
||||
bx lr
|
||||
|
||||
ArmReadTpidrurw
|
||||
mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW
|
||||
bx lr
|
||||
|
||||
ArmWriteTpidrurw
|
||||
mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW
|
||||
bx lr
|
||||
|
||||
ArmIsArchTimerImplemented
|
||||
mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1
|
||||
and r0, r0, #0x000F0000
|
||||
bx lr
|
||||
|
||||
ArmReadIdPfr1
|
||||
mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register
|
||||
bx lr
|
||||
|
||||
END
|
||||
|
Reference in New Issue
Block a user