ArmPkg/ArmLib: Clean ArmV7Lib
- Move the non specific ArmV7 functions to ArmLib. - Clean the ARM Platform common components to not depend on ArmV7 if not required git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12453 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
@@ -15,8 +15,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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--*/
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--*/
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#include "CpuDxe.h"
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#include "CpuDxe.h"
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//FIXME: Remove this ARMv7 specific header
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#include <Chipset/ArmV7.h>
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// First Level Descriptors
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// First Level Descriptors
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typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR;
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typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR;
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@@ -1,6 +1,7 @@
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/** @file
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/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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are licensed and made available under the terms and conditions of the BSD License
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@@ -24,28 +25,6 @@
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#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))
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#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))
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#define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))
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#define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))
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// Cortex A9 feature bit definitions
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#define A9_FEATURE_PARITY (1<<9)
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#define A9_FEATURE_AOW (1<<8)
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#define A9_FEATURE_EXCL (1<<7)
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#define A9_FEATURE_SMP (1<<6)
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#define A9_FEATURE_FOZ (1<<3)
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#define A9_FEATURE_DPREF (1<<2)
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#define A9_FEATURE_HINT (1<<1)
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#define A9_FEATURE_FWD (1<<0)
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// SCU register offsets & masks
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#define SCU_CONTROL_OFFSET 0x0
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#define SCU_CONFIG_OFFSET 0x4
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#define SCU_INVALL_OFFSET 0xC
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#define SCU_FILT_START_OFFSET 0x40
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#define SCU_FILT_END_OFFSET 0x44
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#define SCU_SACR_OFFSET 0x50
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#define SCU_SSACR_OFFSET 0x54
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#define SMP_GIC_CPUIF_BASE 0x100
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#define SMP_GIC_DIST_BASE 0x1000
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// CPACR - Coprocessor Access Control Register definitions
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// CPACR - Coprocessor Access Control Register definitions
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#define CPACR_CP_DENIED(cp) 0x00
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#define CPACR_CP_DENIED(cp) 0x00
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#define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)
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#define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)
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@@ -71,121 +50,24 @@
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#define SCR_FW (1 << 4)
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#define SCR_FW (1 << 4)
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#define SCR_AW (1 << 5)
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#define SCR_AW (1 << 5)
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// MIDR - Main ID Register definitions
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#define ARM_CPU_TYPE_MASK 0xFFF
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#define ARM_CPU_TYPE_A15 0xC0F
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#define ARM_CPU_TYPE_A9 0xC09
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#define ARM_CPU_TYPE_A5 0xC05
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VOID
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VOID
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EFIAPI
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EFIAPI
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ArmEnableSWPInstruction (
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ArmEnableSWPInstruction (
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VOID
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VOID
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);
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);
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VOID
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EFIAPI
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ArmWriteNsacr (
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IN UINT32 SetWayFormat
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);
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VOID
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EFIAPI
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ArmWriteScr (
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IN UINT32 SetWayFormat
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);
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VOID
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EFIAPI
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ArmWriteVMBar (
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IN UINT32 SetWayFormat
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);
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VOID
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EFIAPI
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ArmWriteVBar (
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IN UINT32 SetWayFormat
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);
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UINT32
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EFIAPI
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ArmReadVBar (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteCPACR (
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IN UINT32 SetWayFormat
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);
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VOID
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EFIAPI
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ArmEnableVFP (
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VOID
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);
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VOID
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EFIAPI
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ArmCallWFI (
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VOID
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);
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VOID
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EFIAPI
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ArmInvalidScu (
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VOID
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);
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UINTN
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EFIAPI
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ArmGetScuBaseAddress (
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VOID
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);
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UINT32
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EFIAPI
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ArmIsScuEnable (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteAuxCr (
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IN UINT32 Bit
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);
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UINT32
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EFIAPI
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ArmReadAuxCr (
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VOID
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);
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VOID
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EFIAPI
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ArmSetAuxCrBit (
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IN UINT32 Bits
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);
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VOID
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EFIAPI
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ArmSetupSmpNonSecure (
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IN UINTN CoreId
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);
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UINTN
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UINTN
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EFIAPI
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EFIAPI
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ArmReadCbar (
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ArmReadCbar (
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VOID
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VOID
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);
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);
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VOID
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EFIAPI
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ArmInvalidateInstructionAndDataTlb (
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VOID
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);
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UINTN
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EFIAPI
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ArmReadMpidr (
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VOID
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);
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UINTN
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UINTN
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EFIAPI
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EFIAPI
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ArmReadTpidrurw (
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ArmReadTpidrurw (
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@@ -198,4 +80,10 @@ ArmWriteTpidrurw (
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UINTN Value
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UINTN Value
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);
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);
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UINTN
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EFIAPI
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ArmReadIdPfr1 (
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VOID
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);
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#endif // __ARM_V7_H__
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#endif // __ARM_V7_H__
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@@ -15,6 +15,12 @@
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#ifndef __ARM_LIB__
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#ifndef __ARM_LIB__
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#define __ARM_LIB__
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#define __ARM_LIB__
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#ifdef ARM_CPU_ARMv6
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#include <Chipset/ARM1176JZ-S.h>
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#else
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#include <Chipset/ArmV7.h>
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#endif
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typedef enum {
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typedef enum {
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ARM_CACHE_TYPE_WRITE_BACK,
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ARM_CACHE_TYPE_WRITE_BACK,
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ARM_CACHE_TYPE_UNKNOWN
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ARM_CACHE_TYPE_UNKNOWN
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@@ -250,6 +256,12 @@ ArmDisableCachesAndMmu (
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VOID
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VOID
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);
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);
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VOID
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EFIAPI
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ArmInvalidateInstructionAndDataTlb (
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VOID
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);
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VOID
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VOID
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EFIAPI
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EFIAPI
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ArmEnableInterrupts (
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ArmEnableInterrupts (
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@@ -384,6 +396,77 @@ EFIAPI
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ArmInstructionSynchronizationBarrier (
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ArmInstructionSynchronizationBarrier (
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VOID
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VOID
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);
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);
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VOID
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EFIAPI
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ArmWriteVBar (
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IN UINT32 VectorBase
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);
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UINT32
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EFIAPI
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ArmReadVBar (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteAuxCr (
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IN UINT32 Bit
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);
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UINT32
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EFIAPI
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ArmReadAuxCr (
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VOID
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);
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VOID
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EFIAPI
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ArmSetAuxCrBit (
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IN UINT32 Bits
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);
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VOID
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EFIAPI
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ArmCallWFI (
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VOID
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);
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UINTN
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EFIAPI
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ArmReadMpidr (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteCPACR (
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IN UINT32 Access
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);
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VOID
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EFIAPI
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|
ArmEnableVFP (
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|
VOID
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);
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VOID
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EFIAPI
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|
ArmWriteNsacr (
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IN UINT32 SetWayFormat
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);
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VOID
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EFIAPI
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ArmWriteScr (
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IN UINT32 SetWayFormat
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);
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VOID
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EFIAPI
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ArmWriteVMBar (
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IN UINT32 VectorMonitorBase
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);
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#endif // __ARM_LIB__
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#endif // __ARM_LIB__
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@@ -1,193 +0,0 @@
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#------------------------------------------------------------------------------
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#
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# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
|
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#
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# This program and the accompanying materials
|
|
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# are licensed and made available under the terms and conditions of the BSD License
|
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# which accompanies this distribution. The full text of the license may be found at
|
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# http://opensource.org/licenses/bsd-license.php
|
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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#include <AsmMacroIoLib.h>
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.text
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.align 2
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|
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GCC_ASM_EXPORT(Cp15IdCode)
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GCC_ASM_EXPORT(Cp15CacheInfo)
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GCC_ASM_EXPORT(ArmIsMPCore)
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GCC_ASM_EXPORT(ArmEnableAsynchronousAbort)
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GCC_ASM_EXPORT(ArmDisableAsynchronousAbort)
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GCC_ASM_EXPORT(ArmEnableIrq)
|
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GCC_ASM_EXPORT(ArmDisableIrq)
|
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GCC_ASM_EXPORT(ArmGetInterruptState)
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GCC_ASM_EXPORT(ArmEnableFiq)
|
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GCC_ASM_EXPORT(ArmDisableFiq)
|
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GCC_ASM_EXPORT(ArmEnableInterrupts)
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GCC_ASM_EXPORT(ArmDisableInterrupts)
|
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GCC_ASM_EXPORT(ArmGetFiqState)
|
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GCC_ASM_EXPORT(ArmInvalidateTlb)
|
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GCC_ASM_EXPORT(ArmSetTTBR0)
|
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GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)
|
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GCC_ASM_EXPORT(ArmSetDomainAccessControl)
|
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GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
|
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GCC_ASM_EXPORT(CPSRMaskInsert)
|
|
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GCC_ASM_EXPORT(CPSRRead)
|
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GCC_ASM_EXPORT(ReadCCSIDR)
|
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GCC_ASM_EXPORT(ReadCLIDR)
|
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|
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|
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|
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#------------------------------------------------------------------------------
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|
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ASM_PFX(Cp15IdCode):
|
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mrc p15,0,R0,c0,c0,0
|
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bx LR
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|
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ASM_PFX(Cp15CacheInfo):
|
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mrc p15,0,R0,c0,c0,1
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ASM_PFX(ArmIsMPCore):
|
|
||||||
mrc p15,0,R0,c0,c0,5
|
|
||||||
// Get Multiprocessing extension (bit31) & U bit (bit30)
|
|
||||||
and R0, R0, #0xC0000000
|
|
||||||
// if bit30 == 0 then the processor is part of a multiprocessor system)
|
|
||||||
and R0, R0, #0x80000000
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ASM_PFX(ArmEnableAsynchronousAbort):
|
|
||||||
cpsie a
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
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||||||
ASM_PFX(ArmDisableAsynchronousAbort):
|
|
||||||
cpsid a
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ASM_PFX(ArmEnableIrq):
|
|
||||||
cpsie i
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ASM_PFX(ArmDisableIrq):
|
|
||||||
cpsid i
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ASM_PFX(ArmGetInterruptState):
|
|
||||||
mrs R0,CPSR
|
|
||||||
tst R0,#0x80 @Check if IRQ is enabled.
|
|
||||||
moveq R0,#1
|
|
||||||
movne R0,#0
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ASM_PFX(ArmEnableFiq):
|
|
||||||
cpsie f
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ASM_PFX(ArmDisableFiq):
|
|
||||||
cpsid f
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ASM_PFX(ArmEnableInterrupts):
|
|
||||||
cpsie if
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ASM_PFX(ArmDisableInterrupts):
|
|
||||||
cpsid if
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ASM_PFX(ArmGetFiqState):
|
|
||||||
mrs R0,CPSR
|
|
||||||
tst R0,#0x40 @Check if FIQ is enabled.
|
|
||||||
moveq R0,#1
|
|
||||||
movne R0,#0
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ASM_PFX(ArmInvalidateTlb):
|
|
||||||
mov r0,#0
|
|
||||||
mcr p15,0,r0,c8,c7,0
|
|
||||||
mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
|
|
||||||
dsb
|
|
||||||
isb
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
ASM_PFX(ArmSetTTBR0):
|
|
||||||
mcr p15,0,r0,c2,c0,0
|
|
||||||
isb
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
ASM_PFX(ArmGetTTBR0BaseAddress):
|
|
||||||
mrc p15,0,r0,c2,c0,0
|
|
||||||
LoadConstantToReg(0xFFFFC000, r1)
|
|
||||||
and r0, r0, r1
|
|
||||||
isb
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
|
|
||||||
ASM_PFX(ArmSetDomainAccessControl):
|
|
||||||
mcr p15,0,r0,c3,c0,0
|
|
||||||
isb
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
//
|
|
||||||
//VOID
|
|
||||||
//ArmUpdateTranslationTableEntry (
|
|
||||||
// IN VOID *TranslationTableEntry // R0
|
|
||||||
// IN VOID *MVA // R1
|
|
||||||
// );
|
|
||||||
ASM_PFX(ArmUpdateTranslationTableEntry):
|
|
||||||
mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA
|
|
||||||
dsb
|
|
||||||
mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA
|
|
||||||
mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
|
|
||||||
dsb
|
|
||||||
isb
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert
|
|
||||||
stmfd sp!, {r4-r12, lr} @ save all the banked registers
|
|
||||||
mov r3, sp @ copy the stack pointer into a non-banked register
|
|
||||||
mrs r2, cpsr @ read the cpsr
|
|
||||||
bic r2, r2, r0 @ clear mask in the cpsr
|
|
||||||
and r1, r1, r0 @ clear bits outside the mask in the input
|
|
||||||
orr r2, r2, r1 @ set field
|
|
||||||
msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)
|
|
||||||
isb
|
|
||||||
mov sp, r3 @ restore stack pointer
|
|
||||||
ldmfd sp!, {r4-r12, lr} @ restore registers
|
|
||||||
bx lr @ return (hopefully thumb-safe!)
|
|
||||||
|
|
||||||
ASM_PFX(CPSRRead):
|
|
||||||
mrs r0, cpsr
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
// UINT32
|
|
||||||
// ReadCCSIDR (
|
|
||||||
// IN UINT32 CSSELR
|
|
||||||
// )
|
|
||||||
ASM_PFX(ReadCCSIDR):
|
|
||||||
mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)
|
|
||||||
isb
|
|
||||||
mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
// UINT32
|
|
||||||
// ReadCLIDR (
|
|
||||||
// IN UINT32 CSSELR
|
|
||||||
// )
|
|
||||||
ASM_PFX(ReadCLIDR):
|
|
||||||
mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
|
|
||||||
@@ -1,192 +0,0 @@
|
|||||||
//------------------------------------------------------------------------------
|
|
||||||
//
|
|
||||||
// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
|
|
||||||
//
|
|
||||||
// This program and the accompanying materials
|
|
||||||
// are licensed and made available under the terms and conditions of the BSD License
|
|
||||||
// which accompanies this distribution. The full text of the license may be found at
|
|
||||||
// http://opensource.org/licenses/bsd-license.php
|
|
||||||
//
|
|
||||||
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
||||||
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
||||||
//
|
|
||||||
//------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
|
|
||||||
EXPORT Cp15IdCode
|
|
||||||
EXPORT Cp15CacheInfo
|
|
||||||
EXPORT ArmIsMPCore
|
|
||||||
EXPORT ArmEnableAsynchronousAbort
|
|
||||||
EXPORT ArmDisableAsynchronousAbort
|
|
||||||
EXPORT ArmEnableIrq
|
|
||||||
EXPORT ArmDisableIrq
|
|
||||||
EXPORT ArmGetInterruptState
|
|
||||||
EXPORT ArmEnableFiq
|
|
||||||
EXPORT ArmDisableFiq
|
|
||||||
EXPORT ArmEnableInterrupts
|
|
||||||
EXPORT ArmDisableInterrupts
|
|
||||||
EXPORT ArmGetFiqState
|
|
||||||
EXPORT ArmInvalidateTlb
|
|
||||||
EXPORT ArmSetTTBR0
|
|
||||||
EXPORT ArmGetTTBR0BaseAddress
|
|
||||||
EXPORT ArmSetDomainAccessControl
|
|
||||||
EXPORT ArmUpdateTranslationTableEntry
|
|
||||||
EXPORT CPSRMaskInsert
|
|
||||||
EXPORT CPSRRead
|
|
||||||
EXPORT ReadCCSIDR
|
|
||||||
EXPORT ReadCLIDR
|
|
||||||
|
|
||||||
AREA ArmLibSupport, CODE, READONLY
|
|
||||||
|
|
||||||
|
|
||||||
//------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
Cp15IdCode
|
|
||||||
mrc p15,0,R0,c0,c0,0
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
Cp15CacheInfo
|
|
||||||
mrc p15,0,R0,c0,c0,1
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ArmIsMPCore
|
|
||||||
mrc p15,0,R0,c0,c0,5
|
|
||||||
// Get Multiprocessing extension (bit31) & U bit (bit30)
|
|
||||||
and R0, R0, #0xC0000000
|
|
||||||
// if bit30 == 0 then the processor is part of a multiprocessor system)
|
|
||||||
and R0, R0, #0x80000000
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ArmEnableAsynchronousAbort
|
|
||||||
cpsie a
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ArmDisableAsynchronousAbort
|
|
||||||
cpsid a
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ArmEnableIrq
|
|
||||||
cpsie i
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ArmDisableIrq
|
|
||||||
cpsid i
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ArmEnableFiq
|
|
||||||
cpsie f
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ArmDisableFiq
|
|
||||||
cpsid f
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ArmEnableInterrupts
|
|
||||||
cpsie if
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ArmDisableInterrupts
|
|
||||||
cpsid if
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ArmGetInterruptState
|
|
||||||
mrs R0,CPSR
|
|
||||||
tst R0,#0x80 ;Check if IRQ is enabled.
|
|
||||||
moveq R0,#1
|
|
||||||
movne R0,#0
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ArmGetFiqState
|
|
||||||
mrs R0,CPSR
|
|
||||||
tst R0,#0x40 ;Check if FIQ is enabled.
|
|
||||||
moveq R0,#1
|
|
||||||
movne R0,#0
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ArmInvalidateTlb
|
|
||||||
mov r0,#0
|
|
||||||
mcr p15,0,r0,c8,c7,0
|
|
||||||
mcr p15,0,R9,c7,c5,6 ; BPIALL Invalidate Branch predictor array. R9 == NoOp
|
|
||||||
dsb
|
|
||||||
isb
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
ArmSetTTBR0
|
|
||||||
mcr p15,0,r0,c2,c0,0
|
|
||||||
isb
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
ArmGetTTBR0BaseAddress
|
|
||||||
mrc p15,0,r0,c2,c0,0
|
|
||||||
ldr r1, = 0xFFFFC000
|
|
||||||
and r0, r0, r1
|
|
||||||
isb
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
|
|
||||||
ArmSetDomainAccessControl
|
|
||||||
mcr p15,0,r0,c3,c0,0
|
|
||||||
isb
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
//
|
|
||||||
//VOID
|
|
||||||
//ArmUpdateTranslationTableEntry (
|
|
||||||
// IN VOID *TranslationTableEntry // R0
|
|
||||||
// IN VOID *MVA // R1
|
|
||||||
// );
|
|
||||||
ArmUpdateTranslationTableEntry
|
|
||||||
mcr p15,0,R0,c7,c14,1 ; DCCIMVAC Clean data cache by MVA
|
|
||||||
dsb
|
|
||||||
mcr p15,0,R1,c8,c7,1 ; TLBIMVA TLB Invalidate MVA
|
|
||||||
mcr p15,0,R9,c7,c5,6 ; BPIALL Invalidate Branch predictor array. R9 == NoOp
|
|
||||||
dsb
|
|
||||||
isb
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert
|
|
||||||
stmfd sp!, {r4-r12, lr} ; save all the banked registers
|
|
||||||
mov r3, sp ; copy the stack pointer into a non-banked register
|
|
||||||
mrs r2, cpsr ; read the cpsr
|
|
||||||
bic r2, r2, r0 ; clear mask in the cpsr
|
|
||||||
and r1, r1, r0 ; clear bits outside the mask in the input
|
|
||||||
orr r2, r2, r1 ; set field
|
|
||||||
msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch)
|
|
||||||
isb
|
|
||||||
mov sp, r3 ; restore stack pointer
|
|
||||||
ldmfd sp!, {r4-r12, lr} ; restore registers
|
|
||||||
bx lr ; return (hopefully thumb-safe!)
|
|
||||||
|
|
||||||
CPSRRead
|
|
||||||
mrs r0, cpsr
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
|
|
||||||
// UINT32
|
|
||||||
// ReadCCSIDR (
|
|
||||||
// IN UINT32 CSSELR
|
|
||||||
// )
|
|
||||||
ReadCCSIDR
|
|
||||||
mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)
|
|
||||||
isb
|
|
||||||
mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
|
|
||||||
// UINT32
|
|
||||||
// ReadCLIDR (
|
|
||||||
// IN UINT32 CSSELR
|
|
||||||
// )
|
|
||||||
ReadCLIDR
|
|
||||||
mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
END
|
|
||||||
101
ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S
Normal file
101
ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S
Normal file
@@ -0,0 +1,101 @@
|
|||||||
|
#------------------------------------------------------------------------------
|
||||||
|
#
|
||||||
|
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||||
|
# Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||||
|
#
|
||||||
|
# This program and the accompanying materials
|
||||||
|
# are licensed and made available under the terms and conditions of the BSD License
|
||||||
|
# which accompanies this distribution. The full text of the license may be found at
|
||||||
|
# http://opensource.org/licenses/bsd-license.php
|
||||||
|
#
|
||||||
|
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||||
|
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||||
|
#
|
||||||
|
#------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
#include <AsmMacroIoLib.h>
|
||||||
|
|
||||||
|
.text
|
||||||
|
.align 2
|
||||||
|
|
||||||
|
GCC_ASM_EXPORT(ArmIsMpCore)
|
||||||
|
GCC_ASM_EXPORT(ArmEnableAsynchronousAbort)
|
||||||
|
GCC_ASM_EXPORT(ArmDisableAsynchronousAbort)
|
||||||
|
GCC_ASM_EXPORT(ArmEnableIrq)
|
||||||
|
GCC_ASM_EXPORT(ArmDisableIrq)
|
||||||
|
GCC_ASM_EXPORT(ArmEnableFiq)
|
||||||
|
GCC_ASM_EXPORT(ArmDisableFiq)
|
||||||
|
GCC_ASM_EXPORT(ArmEnableInterrupts)
|
||||||
|
GCC_ASM_EXPORT(ArmDisableInterrupts)
|
||||||
|
GCC_ASM_EXPORT(ReadCCSIDR)
|
||||||
|
GCC_ASM_EXPORT(ReadCLIDR)
|
||||||
|
|
||||||
|
#------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
ASM_PFX(ArmIsMpCore):
|
||||||
|
mrc p15,0,R0,c0,c0,5
|
||||||
|
// Get Multiprocessing extension (bit31) & U bit (bit30)
|
||||||
|
and R0, R0, #0xC0000000
|
||||||
|
// if bit30 == 0 then the processor is part of a multiprocessor system)
|
||||||
|
and R0, R0, #0x80000000
|
||||||
|
bx LR
|
||||||
|
|
||||||
|
ASM_PFX(ArmEnableAsynchronousAbort):
|
||||||
|
cpsie a
|
||||||
|
isb
|
||||||
|
bx LR
|
||||||
|
|
||||||
|
ASM_PFX(ArmDisableAsynchronousAbort):
|
||||||
|
cpsid a
|
||||||
|
isb
|
||||||
|
bx LR
|
||||||
|
|
||||||
|
ASM_PFX(ArmEnableIrq):
|
||||||
|
cpsie i
|
||||||
|
isb
|
||||||
|
bx LR
|
||||||
|
|
||||||
|
ASM_PFX(ArmDisableIrq):
|
||||||
|
cpsid i
|
||||||
|
isb
|
||||||
|
bx LR
|
||||||
|
|
||||||
|
ASM_PFX(ArmEnableFiq):
|
||||||
|
cpsie f
|
||||||
|
isb
|
||||||
|
bx LR
|
||||||
|
|
||||||
|
ASM_PFX(ArmDisableFiq):
|
||||||
|
cpsid f
|
||||||
|
isb
|
||||||
|
bx LR
|
||||||
|
|
||||||
|
ASM_PFX(ArmEnableInterrupts):
|
||||||
|
cpsie if
|
||||||
|
isb
|
||||||
|
bx LR
|
||||||
|
|
||||||
|
ASM_PFX(ArmDisableInterrupts):
|
||||||
|
cpsid if
|
||||||
|
isb
|
||||||
|
bx LR
|
||||||
|
|
||||||
|
// UINT32
|
||||||
|
// ReadCCSIDR (
|
||||||
|
// IN UINT32 CSSELR
|
||||||
|
// )
|
||||||
|
ASM_PFX(ReadCCSIDR):
|
||||||
|
mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)
|
||||||
|
isb
|
||||||
|
mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)
|
||||||
|
bx lr
|
||||||
|
|
||||||
|
// UINT32
|
||||||
|
// ReadCLIDR (
|
||||||
|
// IN UINT32 CSSELR
|
||||||
|
// )
|
||||||
|
ASM_PFX(ReadCLIDR):
|
||||||
|
mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
|
||||||
|
bx lr
|
||||||
|
|
||||||
|
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
|
||||||
100
ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm
Normal file
100
ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm
Normal file
@@ -0,0 +1,100 @@
|
|||||||
|
//------------------------------------------------------------------------------
|
||||||
|
//
|
||||||
|
// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
|
||||||
|
// Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||||
|
//
|
||||||
|
// This program and the accompanying materials
|
||||||
|
// are licensed and made available under the terms and conditions of the BSD License
|
||||||
|
// which accompanies this distribution. The full text of the license may be found at
|
||||||
|
// http://opensource.org/licenses/bsd-license.php
|
||||||
|
//
|
||||||
|
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||||
|
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||||
|
//
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
|
||||||
|
EXPORT ArmIsMpCore
|
||||||
|
EXPORT ArmEnableAsynchronousAbort
|
||||||
|
EXPORT ArmDisableAsynchronousAbort
|
||||||
|
EXPORT ArmEnableIrq
|
||||||
|
EXPORT ArmDisableIrq
|
||||||
|
EXPORT ArmEnableFiq
|
||||||
|
EXPORT ArmDisableFiq
|
||||||
|
EXPORT ArmEnableInterrupts
|
||||||
|
EXPORT ArmDisableInterrupts
|
||||||
|
EXPORT ReadCCSIDR
|
||||||
|
EXPORT ReadCLIDR
|
||||||
|
|
||||||
|
AREA ArmLibSupportV7, CODE, READONLY
|
||||||
|
|
||||||
|
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
ArmIsMpCore
|
||||||
|
mrc p15,0,R0,c0,c0,5
|
||||||
|
// Get Multiprocessing extension (bit31) & U bit (bit30)
|
||||||
|
and R0, R0, #0xC0000000
|
||||||
|
// if bit30 == 0 then the processor is part of a multiprocessor system)
|
||||||
|
and R0, R0, #0x80000000
|
||||||
|
bx LR
|
||||||
|
|
||||||
|
ArmEnableAsynchronousAbort
|
||||||
|
cpsie a
|
||||||
|
isb
|
||||||
|
bx LR
|
||||||
|
|
||||||
|
ArmDisableAsynchronousAbort
|
||||||
|
cpsid a
|
||||||
|
isb
|
||||||
|
bx LR
|
||||||
|
|
||||||
|
ArmEnableIrq
|
||||||
|
cpsie i
|
||||||
|
isb
|
||||||
|
bx LR
|
||||||
|
|
||||||
|
ArmDisableIrq
|
||||||
|
cpsid i
|
||||||
|
isb
|
||||||
|
bx LR
|
||||||
|
|
||||||
|
ArmEnableFiq
|
||||||
|
cpsie f
|
||||||
|
isb
|
||||||
|
bx LR
|
||||||
|
|
||||||
|
ArmDisableFiq
|
||||||
|
cpsid f
|
||||||
|
isb
|
||||||
|
bx LR
|
||||||
|
|
||||||
|
ArmEnableInterrupts
|
||||||
|
cpsie if
|
||||||
|
isb
|
||||||
|
bx LR
|
||||||
|
|
||||||
|
ArmDisableInterrupts
|
||||||
|
cpsid if
|
||||||
|
isb
|
||||||
|
bx LR
|
||||||
|
|
||||||
|
// UINT32
|
||||||
|
// ReadCCSIDR (
|
||||||
|
// IN UINT32 CSSELR
|
||||||
|
// )
|
||||||
|
ReadCCSIDR
|
||||||
|
mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)
|
||||||
|
isb
|
||||||
|
mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
|
||||||
|
bx lr
|
||||||
|
|
||||||
|
// UINT32
|
||||||
|
// ReadCLIDR (
|
||||||
|
// IN UINT32 CSSELR
|
||||||
|
// )
|
||||||
|
ReadCLIDR
|
||||||
|
mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
|
||||||
|
bx lr
|
||||||
|
|
||||||
|
END
|
||||||
@@ -235,13 +235,3 @@ ArmCleanDataCache (
|
|||||||
ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
|
ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
|
||||||
}
|
}
|
||||||
|
|
||||||
VOID
|
|
||||||
EFIAPI
|
|
||||||
ArmSetAuxCrBit (
|
|
||||||
IN UINT32 Bits
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 val = ArmReadAuxCr();
|
|
||||||
val |= Bits;
|
|
||||||
ArmWriteAuxCr(val);
|
|
||||||
}
|
|
||||||
|
|||||||
@@ -1,80 +1,80 @@
|
|||||||
/** @file
|
/** @file
|
||||||
|
|
||||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||||
|
|
||||||
This program and the accompanying materials
|
This program and the accompanying materials
|
||||||
are licensed and made available under the terms and conditions of the BSD License
|
are licensed and made available under the terms and conditions of the BSD License
|
||||||
which accompanies this distribution. The full text of the license may be found at
|
which accompanies this distribution. The full text of the license may be found at
|
||||||
http://opensource.org/licenses/bsd-license.php
|
http://opensource.org/licenses/bsd-license.php
|
||||||
|
|
||||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef __ARM_V7_LIB_H__
|
#ifndef __ARM_V7_LIB_H__
|
||||||
#define __ARM_V7_LIB_H__
|
#define __ARM_V7_LIB_H__
|
||||||
|
|
||||||
|
|
||||||
VOID
|
VOID
|
||||||
EFIAPI
|
EFIAPI
|
||||||
ArmDrainWriteBuffer (
|
ArmDrainWriteBuffer (
|
||||||
VOID
|
VOID
|
||||||
);
|
);
|
||||||
|
|
||||||
VOID
|
VOID
|
||||||
EFIAPI
|
EFIAPI
|
||||||
ArmInvalidateDataCacheEntryBySetWay (
|
ArmInvalidateDataCacheEntryBySetWay (
|
||||||
IN UINT32 SetWayFormat
|
IN UINT32 SetWayFormat
|
||||||
);
|
);
|
||||||
|
|
||||||
VOID
|
VOID
|
||||||
EFIAPI
|
EFIAPI
|
||||||
ArmCleanDataCacheEntryBySetWay (
|
ArmCleanDataCacheEntryBySetWay (
|
||||||
IN UINT32 SetWayFormat
|
IN UINT32 SetWayFormat
|
||||||
);
|
);
|
||||||
|
|
||||||
VOID
|
VOID
|
||||||
EFIAPI
|
EFIAPI
|
||||||
ArmCleanInvalidateDataCacheEntryBySetWay (
|
ArmCleanInvalidateDataCacheEntryBySetWay (
|
||||||
IN UINT32 SetWayFormat
|
IN UINT32 SetWayFormat
|
||||||
);
|
);
|
||||||
|
|
||||||
VOID
|
VOID
|
||||||
EFIAPI
|
EFIAPI
|
||||||
ArmEnableAsynchronousAbort (
|
ArmEnableAsynchronousAbort (
|
||||||
VOID
|
VOID
|
||||||
);
|
);
|
||||||
|
|
||||||
UINTN
|
UINTN
|
||||||
EFIAPI
|
EFIAPI
|
||||||
ArmDisableAsynchronousAbort (
|
ArmDisableAsynchronousAbort (
|
||||||
VOID
|
VOID
|
||||||
);
|
);
|
||||||
|
|
||||||
VOID
|
VOID
|
||||||
EFIAPI
|
EFIAPI
|
||||||
ArmEnableIrq (
|
ArmEnableIrq (
|
||||||
VOID
|
VOID
|
||||||
);
|
);
|
||||||
|
|
||||||
UINTN
|
UINTN
|
||||||
EFIAPI
|
EFIAPI
|
||||||
ArmDisableIrq (
|
ArmDisableIrq (
|
||||||
VOID
|
VOID
|
||||||
);
|
);
|
||||||
|
|
||||||
VOID
|
VOID
|
||||||
EFIAPI
|
EFIAPI
|
||||||
ArmEnableFiq (
|
ArmEnableFiq (
|
||||||
VOID
|
VOID
|
||||||
);
|
);
|
||||||
|
|
||||||
UINTN
|
UINTN
|
||||||
EFIAPI
|
EFIAPI
|
||||||
ArmDisableFiq (
|
ArmDisableFiq (
|
||||||
VOID
|
VOID
|
||||||
);
|
);
|
||||||
|
|
||||||
#endif // __ARM_V7_LIB_H__
|
#endif // __ARM_V7_LIB_H__
|
||||||
|
|
||||||
|
|||||||
@@ -1,7 +1,7 @@
|
|||||||
#/** @file
|
#/** @file
|
||||||
# Semihosting serail port lib
|
|
||||||
#
|
#
|
||||||
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
|
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
|
||||||
|
# Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||||
#
|
#
|
||||||
# This program and the accompanying materials
|
# This program and the accompanying materials
|
||||||
# are licensed and made available under the terms and conditions of the BSD License
|
# are licensed and made available under the terms and conditions of the BSD License
|
||||||
@@ -22,13 +22,16 @@
|
|||||||
LIBRARY_CLASS = ArmLib
|
LIBRARY_CLASS = ArmLib
|
||||||
|
|
||||||
[Sources.common]
|
[Sources.common]
|
||||||
ArmLibSupport.S | GCC
|
ArmLibSupportV7.S | GCC
|
||||||
ArmLibSupport.asm | RVCT
|
ArmLibSupportV7.asm | RVCT
|
||||||
|
|
||||||
|
../Common/ArmLibSupport.S | GCC
|
||||||
|
../Common/ArmLibSupport.asm | RVCT
|
||||||
../Common/ArmLib.c
|
../Common/ArmLib.c
|
||||||
|
|
||||||
ArmV7Support.S | GCC
|
ArmV7Support.S | GCC
|
||||||
ArmV7Support.asm | RVCT
|
ArmV7Support.asm | RVCT
|
||||||
|
|
||||||
ArmV7Lib.c
|
ArmV7Lib.c
|
||||||
ArmV7Mmu.c
|
ArmV7Mmu.c
|
||||||
|
|
||||||
|
|||||||
@@ -22,13 +22,16 @@
|
|||||||
LIBRARY_CLASS = ArmLib
|
LIBRARY_CLASS = ArmLib
|
||||||
|
|
||||||
[Sources.common]
|
[Sources.common]
|
||||||
ArmLibSupport.S | GCC
|
ArmLibSupportV7.S | GCC
|
||||||
ArmLibSupport.asm | RVCT
|
ArmLibSupportV7.asm | RVCT
|
||||||
|
|
||||||
|
../Common/ArmLibSupport.S | GCC
|
||||||
|
../Common/ArmLibSupport.asm | RVCT
|
||||||
../Common/ArmLib.c
|
../Common/ArmLib.c
|
||||||
|
|
||||||
ArmV7Support.S | GCC
|
ArmV7Support.S | GCC
|
||||||
ArmV7Support.asm | RVCT
|
ArmV7Support.asm | RVCT
|
||||||
|
|
||||||
ArmV7Lib.c
|
ArmV7Lib.c
|
||||||
ArmV7Mmu.c
|
ArmV7Mmu.c
|
||||||
|
|
||||||
|
|||||||
@@ -20,8 +20,11 @@
|
|||||||
LIBRARY_CLASS = ArmLib
|
LIBRARY_CLASS = ArmLib
|
||||||
|
|
||||||
[Sources.common]
|
[Sources.common]
|
||||||
ArmLibSupport.S | GCC
|
ArmLibSupportV7.S | GCC
|
||||||
ArmLibSupport.asm | RVCT
|
ArmLibSupportV7.asm | RVCT
|
||||||
|
|
||||||
|
../Common/ArmLibSupport.S | GCC
|
||||||
|
../Common/ArmLibSupport.asm | RVCT
|
||||||
../Common/ArmLib.c
|
../Common/ArmLib.c
|
||||||
|
|
||||||
ArmV7Support.S | GCC
|
ArmV7Support.S | GCC
|
||||||
|
|||||||
@@ -29,7 +29,8 @@ PopulateLevel2PageTable (
|
|||||||
IN UINT32 PhysicalBase,
|
IN UINT32 PhysicalBase,
|
||||||
IN UINT32 RemainLength,
|
IN UINT32 RemainLength,
|
||||||
IN ARM_MEMORY_REGION_ATTRIBUTES Attributes
|
IN ARM_MEMORY_REGION_ATTRIBUTES Attributes
|
||||||
) {
|
)
|
||||||
|
{
|
||||||
UINT32* PageEntry;
|
UINT32* PageEntry;
|
||||||
UINT32 Pages;
|
UINT32 Pages;
|
||||||
UINT32 Index;
|
UINT32 Index;
|
||||||
@@ -173,14 +174,14 @@ FillTranslationTable (
|
|||||||
PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
|
PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
|
||||||
} else {
|
} else {
|
||||||
// Case: Physical address aligned on the Section Size (1MB) && the length does not fill a section
|
// Case: Physical address aligned on the Section Size (1MB) && the length does not fill a section
|
||||||
PopulateLevel2PageTable(SectionEntry++,PhysicalBase,RemainLength,MemoryRegion->Attributes);
|
PopulateLevel2PageTable (SectionEntry++, PhysicalBase, RemainLength, MemoryRegion->Attributes);
|
||||||
|
|
||||||
// It must be the last entry
|
// It must be the last entry
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
// Case: Physical address NOT aligned on the Section Size (1MB)
|
// Case: Physical address NOT aligned on the Section Size (1MB)
|
||||||
PopulateLevel2PageTable(SectionEntry++,PhysicalBase,RemainLength,MemoryRegion->Attributes);
|
PopulateLevel2PageTable (SectionEntry++, PhysicalBase, RemainLength, MemoryRegion->Attributes);
|
||||||
// Aligned the address
|
// Aligned the address
|
||||||
PhysicalBase = (PhysicalBase + TT_DESCRIPTOR_SECTION_SIZE) & ~(TT_DESCRIPTOR_SECTION_SIZE-1);
|
PhysicalBase = (PhysicalBase + TT_DESCRIPTOR_SECTION_SIZE) & ~(TT_DESCRIPTOR_SECTION_SIZE-1);
|
||||||
|
|
||||||
@@ -206,7 +207,7 @@ ArmConfigureMmu (
|
|||||||
UINT32 TTBRAttributes;
|
UINT32 TTBRAttributes;
|
||||||
|
|
||||||
// Allocate pages for translation table.
|
// Allocate pages for translation table.
|
||||||
TranslationTable = (UINTN)AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SECTION_SIZE + TRANSLATION_TABLE_SECTION_ALIGNMENT));
|
TranslationTable = (UINTN)AllocatePages (EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SECTION_SIZE + TRANSLATION_TABLE_SECTION_ALIGNMENT));
|
||||||
TranslationTable = ((UINTN)TranslationTable + TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK;
|
TranslationTable = ((UINTN)TranslationTable + TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK;
|
||||||
|
|
||||||
if (TranslationTableBase != NULL) {
|
if (TranslationTableBase != NULL) {
|
||||||
@@ -219,17 +220,17 @@ ArmConfigureMmu (
|
|||||||
|
|
||||||
ZeroMem ((VOID *)TranslationTable, TRANSLATION_TABLE_SECTION_SIZE);
|
ZeroMem ((VOID *)TranslationTable, TRANSLATION_TABLE_SECTION_SIZE);
|
||||||
|
|
||||||
ArmCleanInvalidateDataCache();
|
ArmCleanInvalidateDataCache ();
|
||||||
ArmInvalidateInstructionCache();
|
ArmInvalidateInstructionCache ();
|
||||||
ArmInvalidateTlb();
|
ArmInvalidateTlb ();
|
||||||
|
|
||||||
ArmDisableDataCache();
|
ArmDisableDataCache ();
|
||||||
ArmDisableInstructionCache();
|
ArmDisableInstructionCache();
|
||||||
ArmDisableMmu();
|
ArmDisableMmu ();
|
||||||
|
|
||||||
// Make sure nothing sneaked into the cache
|
// Make sure nothing sneaked into the cache
|
||||||
ArmCleanInvalidateDataCache();
|
ArmCleanInvalidateDataCache ();
|
||||||
ArmInvalidateInstructionCache();
|
ArmInvalidateInstructionCache ();
|
||||||
|
|
||||||
TranslationTableAttribute = (ARM_MEMORY_REGION_ATTRIBUTES)0;
|
TranslationTableAttribute = (ARM_MEMORY_REGION_ATTRIBUTES)0;
|
||||||
while (MemoryTable->Length != 0) {
|
while (MemoryTable->Length != 0) {
|
||||||
|
|||||||
@@ -1,358 +1,340 @@
|
|||||||
#------------------------------------------------------------------------------
|
#------------------------------------------------------------------------------
|
||||||
#
|
#
|
||||||
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
|
||||||
#
|
# Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||||
# This program and the accompanying materials
|
#
|
||||||
# are licensed and made available under the terms and conditions of the BSD License
|
# This program and the accompanying materials
|
||||||
# which accompanies this distribution. The full text of the license may be found at
|
# are licensed and made available under the terms and conditions of the BSD License
|
||||||
# http://opensource.org/licenses/bsd-license.php
|
# which accompanies this distribution. The full text of the license may be found at
|
||||||
#
|
# http://opensource.org/licenses/bsd-license.php
|
||||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
#
|
||||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||||
#
|
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||||
#------------------------------------------------------------------------------
|
#
|
||||||
|
#------------------------------------------------------------------------------
|
||||||
.text
|
|
||||||
.align 2
|
.text
|
||||||
|
.align 2
|
||||||
GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
|
|
||||||
GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
|
GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
|
||||||
GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
|
GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
|
||||||
GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
|
GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
|
||||||
GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
|
GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
|
||||||
GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
|
GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
|
||||||
GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)
|
GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
|
||||||
GCC_ASM_EXPORT (ArmDrainWriteBuffer)
|
GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)
|
||||||
GCC_ASM_EXPORT (ArmEnableMmu)
|
GCC_ASM_EXPORT (ArmDrainWriteBuffer)
|
||||||
GCC_ASM_EXPORT (ArmDisableMmu)
|
GCC_ASM_EXPORT (ArmEnableMmu)
|
||||||
GCC_ASM_EXPORT (ArmDisableCachesAndMmu)
|
GCC_ASM_EXPORT (ArmDisableMmu)
|
||||||
GCC_ASM_EXPORT (ArmMmuEnabled)
|
GCC_ASM_EXPORT (ArmDisableCachesAndMmu)
|
||||||
GCC_ASM_EXPORT (ArmEnableDataCache)
|
GCC_ASM_EXPORT (ArmMmuEnabled)
|
||||||
GCC_ASM_EXPORT (ArmDisableDataCache)
|
GCC_ASM_EXPORT (ArmEnableDataCache)
|
||||||
GCC_ASM_EXPORT (ArmEnableInstructionCache)
|
GCC_ASM_EXPORT (ArmDisableDataCache)
|
||||||
GCC_ASM_EXPORT (ArmDisableInstructionCache)
|
GCC_ASM_EXPORT (ArmEnableInstructionCache)
|
||||||
GCC_ASM_EXPORT (ArmEnableSWPInstruction)
|
GCC_ASM_EXPORT (ArmDisableInstructionCache)
|
||||||
GCC_ASM_EXPORT (ArmEnableBranchPrediction)
|
GCC_ASM_EXPORT (ArmEnableSWPInstruction)
|
||||||
GCC_ASM_EXPORT (ArmDisableBranchPrediction)
|
GCC_ASM_EXPORT (ArmEnableBranchPrediction)
|
||||||
GCC_ASM_EXPORT (ArmSetLowVectors)
|
GCC_ASM_EXPORT (ArmDisableBranchPrediction)
|
||||||
GCC_ASM_EXPORT (ArmSetHighVectors)
|
GCC_ASM_EXPORT (ArmSetLowVectors)
|
||||||
GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)
|
GCC_ASM_EXPORT (ArmSetHighVectors)
|
||||||
GCC_ASM_EXPORT (ArmDataMemoryBarrier)
|
GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)
|
||||||
GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)
|
GCC_ASM_EXPORT (ArmDataMemoryBarrier)
|
||||||
GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
|
GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)
|
||||||
GCC_ASM_EXPORT (ArmWriteNsacr)
|
GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
|
||||||
GCC_ASM_EXPORT (ArmWriteScr)
|
GCC_ASM_EXPORT (ArmWriteVBar)
|
||||||
GCC_ASM_EXPORT (ArmWriteVMBar)
|
GCC_ASM_EXPORT (ArmEnableVFP)
|
||||||
GCC_ASM_EXPORT (ArmWriteVBar)
|
GCC_ASM_EXPORT (ArmCallWFI)
|
||||||
GCC_ASM_EXPORT (ArmWriteCPACR)
|
GCC_ASM_EXPORT (ArmReadCbar)
|
||||||
GCC_ASM_EXPORT (ArmEnableVFP)
|
GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb)
|
||||||
GCC_ASM_EXPORT (ArmCallWFI)
|
GCC_ASM_EXPORT (ArmReadMpidr)
|
||||||
GCC_ASM_EXPORT (ArmWriteAuxCr)
|
GCC_ASM_EXPORT (ArmReadTpidrurw)
|
||||||
GCC_ASM_EXPORT (ArmReadAuxCr)
|
GCC_ASM_EXPORT (ArmWriteTpidrurw)
|
||||||
GCC_ASM_EXPORT (ArmReadCbar)
|
GCC_ASM_EXPORT (ArmIsArchTimerImplemented)
|
||||||
GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb)
|
GCC_ASM_EXPORT (ArmReadIdPfr1)
|
||||||
GCC_ASM_EXPORT (ArmReadMpidr)
|
|
||||||
GCC_ASM_EXPORT (ArmReadTpidrurw)
|
.set DC_ON, (0x1<<2)
|
||||||
GCC_ASM_EXPORT (ArmWriteTpidrurw)
|
.set IC_ON, (0x1<<12)
|
||||||
|
.set CTRL_M_BIT, (1 << 0)
|
||||||
.set DC_ON, (0x1<<2)
|
.set CTRL_C_BIT, (1 << 2)
|
||||||
.set IC_ON, (0x1<<12)
|
.set CTRL_B_BIT, (1 << 7)
|
||||||
.set CTRL_M_BIT, (1 << 0)
|
.set CTRL_I_BIT, (1 << 12)
|
||||||
.set CTRL_C_BIT, (1 << 2)
|
|
||||||
.set CTRL_B_BIT, (1 << 7)
|
|
||||||
.set CTRL_I_BIT, (1 << 12)
|
ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
|
||||||
|
mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
|
||||||
|
dsb
|
||||||
ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
|
isb
|
||||||
mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
|
bx lr
|
||||||
dsb
|
|
||||||
isb
|
ASM_PFX(ArmCleanDataCacheEntryByMVA):
|
||||||
bx lr
|
mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
|
||||||
|
dsb
|
||||||
ASM_PFX(ArmCleanDataCacheEntryByMVA):
|
isb
|
||||||
mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
|
bx lr
|
||||||
dsb
|
|
||||||
isb
|
|
||||||
bx lr
|
ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
|
||||||
|
mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
|
||||||
|
dsb
|
||||||
ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
|
isb
|
||||||
mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
|
bx lr
|
||||||
dsb
|
|
||||||
isb
|
|
||||||
bx lr
|
ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
|
||||||
|
mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line
|
||||||
|
dsb
|
||||||
ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
|
isb
|
||||||
mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line
|
bx lr
|
||||||
dsb
|
|
||||||
isb
|
|
||||||
bx lr
|
ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
|
||||||
|
mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line
|
||||||
|
dsb
|
||||||
ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
|
isb
|
||||||
mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line
|
bx lr
|
||||||
dsb
|
|
||||||
isb
|
|
||||||
bx lr
|
ASM_PFX(ArmCleanDataCacheEntryBySetWay):
|
||||||
|
mcr p15, 0, r0, c7, c10, 2 @ Clean this line
|
||||||
|
dsb
|
||||||
ASM_PFX(ArmCleanDataCacheEntryBySetWay):
|
isb
|
||||||
mcr p15, 0, r0, c7, c10, 2 @ Clean this line
|
bx lr
|
||||||
dsb
|
|
||||||
isb
|
ASM_PFX(ArmInvalidateInstructionCache):
|
||||||
bx lr
|
mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache
|
||||||
|
dsb
|
||||||
ASM_PFX(ArmInvalidateInstructionCache):
|
isb
|
||||||
mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache
|
bx LR
|
||||||
dsb
|
|
||||||
isb
|
ASM_PFX(ArmEnableMmu):
|
||||||
bx LR
|
mrc p15,0,R0,c1,c0,0
|
||||||
|
orr R0,R0,#1
|
||||||
ASM_PFX(ArmEnableMmu):
|
mcr p15,0,R0,c1,c0,0
|
||||||
mrc p15,0,R0,c1,c0,0
|
dsb
|
||||||
orr R0,R0,#1
|
isb
|
||||||
mcr p15,0,R0,c1,c0,0
|
bx LR
|
||||||
dsb
|
|
||||||
isb
|
|
||||||
bx LR
|
ASM_PFX(ArmDisableMmu):
|
||||||
|
mrc p15,0,R0,c1,c0,0
|
||||||
|
bic R0,R0,#1
|
||||||
ASM_PFX(ArmDisableMmu):
|
mcr p15,0,R0,c1,c0,0 @Disable MMU
|
||||||
mrc p15,0,R0,c1,c0,0
|
|
||||||
bic R0,R0,#1
|
mcr p15,0,R0,c8,c7,0 @Invalidate TLB
|
||||||
mcr p15,0,R0,c1,c0,0 @Disable MMU
|
mcr p15,0,R0,c7,c5,6 @Invalidate Branch predictor array
|
||||||
|
dsb
|
||||||
mcr p15,0,R0,c8,c7,0 @Invalidate TLB
|
isb
|
||||||
mcr p15,0,R0,c7,c5,6 @Invalidate Branch predictor array
|
bx LR
|
||||||
dsb
|
|
||||||
isb
|
ASM_PFX(ArmDisableCachesAndMmu):
|
||||||
bx LR
|
mrc p15, 0, r0, c1, c0, 0 @ Get control register
|
||||||
|
bic r0, r0, #CTRL_M_BIT @ Disable MMU
|
||||||
ASM_PFX(ArmDisableCachesAndMmu):
|
bic r0, r0, #CTRL_C_BIT @ Disable D Cache
|
||||||
mrc p15, 0, r0, c1, c0, 0 @ Get control register
|
bic r0, r0, #CTRL_I_BIT @ Disable I Cache
|
||||||
bic r0, r0, #CTRL_M_BIT @ Disable MMU
|
mcr p15, 0, r0, c1, c0, 0 @ Write control register
|
||||||
bic r0, r0, #CTRL_C_BIT @ Disable D Cache
|
dsb
|
||||||
bic r0, r0, #CTRL_I_BIT @ Disable I Cache
|
isb
|
||||||
mcr p15, 0, r0, c1, c0, 0 @ Write control register
|
bx LR
|
||||||
dsb
|
|
||||||
isb
|
ASM_PFX(ArmMmuEnabled):
|
||||||
bx LR
|
mrc p15,0,R0,c1,c0,0
|
||||||
|
and R0,R0,#1
|
||||||
ASM_PFX(ArmMmuEnabled):
|
bx LR
|
||||||
mrc p15,0,R0,c1,c0,0
|
|
||||||
and R0,R0,#1
|
ASM_PFX(ArmEnableDataCache):
|
||||||
bx LR
|
ldr R1,=DC_ON
|
||||||
|
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
||||||
ASM_PFX(ArmEnableDataCache):
|
orr R0,R0,R1 @Set C bit
|
||||||
ldr R1,=DC_ON
|
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
dsb
|
||||||
orr R0,R0,R1 @Set C bit
|
isb
|
||||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
bx LR
|
||||||
dsb
|
|
||||||
isb
|
ASM_PFX(ArmDisableDataCache):
|
||||||
bx LR
|
ldr R1,=DC_ON
|
||||||
|
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
||||||
ASM_PFX(ArmDisableDataCache):
|
bic R0,R0,R1 @Clear C bit
|
||||||
ldr R1,=DC_ON
|
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
dsb
|
||||||
bic R0,R0,R1 @Clear C bit
|
isb
|
||||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
bx LR
|
||||||
dsb
|
|
||||||
isb
|
ASM_PFX(ArmEnableInstructionCache):
|
||||||
bx LR
|
ldr R1,=IC_ON
|
||||||
|
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
||||||
ASM_PFX(ArmEnableInstructionCache):
|
orr R0,R0,R1 @Set I bit
|
||||||
ldr R1,=IC_ON
|
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
dsb
|
||||||
orr R0,R0,R1 @Set I bit
|
isb
|
||||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
bx LR
|
||||||
dsb
|
|
||||||
isb
|
ASM_PFX(ArmDisableInstructionCache):
|
||||||
bx LR
|
ldr R1,=IC_ON
|
||||||
|
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
||||||
ASM_PFX(ArmDisableInstructionCache):
|
bic R0,R0,R1 @Clear I bit.
|
||||||
ldr R1,=IC_ON
|
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
dsb
|
||||||
bic R0,R0,R1 @Clear I bit.
|
isb
|
||||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
bx LR
|
||||||
dsb
|
|
||||||
isb
|
ASM_PFX(ArmEnableSWPInstruction):
|
||||||
bx LR
|
mrc p15, 0, r0, c1, c0, 0
|
||||||
|
orr r0, r0, #0x00000400
|
||||||
ASM_PFX(ArmEnableSWPInstruction):
|
mcr p15, 0, r0, c1, c0, 0
|
||||||
mrc p15, 0, r0, c1, c0, 0
|
isb
|
||||||
orr r0, r0, #0x00000400
|
bx LR
|
||||||
mcr p15, 0, r0, c1, c0, 0
|
|
||||||
isb
|
ASM_PFX(ArmEnableBranchPrediction):
|
||||||
bx LR
|
mrc p15, 0, r0, c1, c0, 0
|
||||||
|
orr r0, r0, #0x00000800
|
||||||
ASM_PFX(ArmEnableBranchPrediction):
|
mcr p15, 0, r0, c1, c0, 0
|
||||||
mrc p15, 0, r0, c1, c0, 0
|
dsb
|
||||||
orr r0, r0, #0x00000800
|
isb
|
||||||
mcr p15, 0, r0, c1, c0, 0
|
bx LR
|
||||||
dsb
|
|
||||||
isb
|
ASM_PFX(ArmDisableBranchPrediction):
|
||||||
bx LR
|
mrc p15, 0, r0, c1, c0, 0
|
||||||
|
bic r0, r0, #0x00000800
|
||||||
ASM_PFX(ArmDisableBranchPrediction):
|
mcr p15, 0, r0, c1, c0, 0
|
||||||
mrc p15, 0, r0, c1, c0, 0
|
dsb
|
||||||
bic r0, r0, #0x00000800
|
isb
|
||||||
mcr p15, 0, r0, c1, c0, 0
|
bx LR
|
||||||
dsb
|
|
||||||
isb
|
ASM_PFX(ArmSetLowVectors):
|
||||||
bx LR
|
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
|
||||||
|
bic r0, r0, #0x00002000 @ clear V bit
|
||||||
ASM_PFX(ArmSetLowVectors):
|
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
|
||||||
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
|
isb
|
||||||
bic r0, r0, #0x00002000 @ clear V bit
|
bx LR
|
||||||
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
|
|
||||||
isb
|
ASM_PFX(ArmSetHighVectors):
|
||||||
bx LR
|
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
|
||||||
|
orr r0, r0, #0x00002000 @ clear V bit
|
||||||
ASM_PFX(ArmSetHighVectors):
|
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
|
||||||
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
|
isb
|
||||||
orr r0, r0, #0x00002000 @ clear V bit
|
bx LR
|
||||||
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
|
|
||||||
isb
|
ASM_PFX(ArmV7AllDataCachesOperation):
|
||||||
bx LR
|
stmfd SP!,{r4-r12, LR}
|
||||||
|
mov R1, R0 @ Save Function call in R1
|
||||||
ASM_PFX(ArmV7AllDataCachesOperation):
|
mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR
|
||||||
stmfd SP!,{r4-r12, LR}
|
ands R3, R6, #0x7000000 @ Mask out all but Level of Coherency (LoC)
|
||||||
mov R1, R0 @ Save Function call in R1
|
mov R3, R3, LSR #23 @ Cache level value (naturally aligned)
|
||||||
mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR
|
beq L_Finished
|
||||||
ands R3, R6, #0x7000000 @ Mask out all but Level of Coherency (LoC)
|
mov R10, #0
|
||||||
mov R3, R3, LSR #23 @ Cache level value (naturally aligned)
|
|
||||||
beq L_Finished
|
Loop1:
|
||||||
mov R10, #0
|
add R2, R10, R10, LSR #1 @ Work out 3xcachelevel
|
||||||
|
mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level
|
||||||
Loop1:
|
and R12, R12, #7 @ get those 3 bits alone
|
||||||
add R2, R10, R10, LSR #1 @ Work out 3xcachelevel
|
cmp R12, #2
|
||||||
mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level
|
blt L_Skip @ no cache or only instruction cache at this level
|
||||||
and R12, R12, #7 @ get those 3 bits alone
|
mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
|
||||||
cmp R12, #2
|
isb @ isb to sync the change to the CacheSizeID reg
|
||||||
blt L_Skip @ no cache or only instruction cache at this level
|
mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)
|
||||||
mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
|
and R2, R12, #0x7 @ extract the line length field
|
||||||
isb @ isb to sync the change to the CacheSizeID reg
|
add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes)
|
||||||
mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)
|
@ ldr R4, =0x3FF
|
||||||
and R2, R12, #0x7 @ extract the line length field
|
mov R4, #0x400
|
||||||
add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes)
|
sub R4, R4, #1
|
||||||
@ ldr R4, =0x3FF
|
ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned)
|
||||||
mov R4, #0x400
|
clz R5, R4 @ R5 is the bit position of the way size increment
|
||||||
sub R4, R4, #1
|
@ ldr R7, =0x00007FFF
|
||||||
ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned)
|
mov R7, #0x00008000
|
||||||
clz R5, R4 @ R5 is the bit position of the way size increment
|
sub R7, R7, #1
|
||||||
@ ldr R7, =0x00007FFF
|
ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned)
|
||||||
mov R7, #0x00008000
|
|
||||||
sub R7, R7, #1
|
Loop2:
|
||||||
ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned)
|
mov R9, R4 @ R9 working copy of the max way size (right aligned)
|
||||||
|
|
||||||
Loop2:
|
Loop3:
|
||||||
mov R9, R4 @ R9 working copy of the max way size (right aligned)
|
orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11
|
||||||
|
orr R0, R0, R7, LSL R2 @ factor in the index number
|
||||||
Loop3:
|
|
||||||
orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11
|
blx R1
|
||||||
orr R0, R0, R7, LSL R2 @ factor in the index number
|
|
||||||
|
subs R9, R9, #1 @ decrement the way number
|
||||||
blx R1
|
bge Loop3
|
||||||
|
subs R7, R7, #1 @ decrement the index
|
||||||
subs R9, R9, #1 @ decrement the way number
|
bge Loop2
|
||||||
bge Loop3
|
L_Skip:
|
||||||
subs R7, R7, #1 @ decrement the index
|
add R10, R10, #2 @ increment the cache number
|
||||||
bge Loop2
|
cmp R3, R10
|
||||||
L_Skip:
|
bgt Loop1
|
||||||
add R10, R10, #2 @ increment the cache number
|
|
||||||
cmp R3, R10
|
L_Finished:
|
||||||
bgt Loop1
|
dsb
|
||||||
|
ldmfd SP!, {r4-r12, lr}
|
||||||
L_Finished:
|
bx LR
|
||||||
dsb
|
|
||||||
ldmfd SP!, {r4-r12, lr}
|
ASM_PFX(ArmDataMemoryBarrier):
|
||||||
bx LR
|
dmb
|
||||||
|
bx LR
|
||||||
ASM_PFX(ArmDataMemoryBarrier):
|
|
||||||
dmb
|
ASM_PFX(ArmDataSyncronizationBarrier):
|
||||||
bx LR
|
ASM_PFX(ArmDrainWriteBuffer):
|
||||||
|
dsb
|
||||||
ASM_PFX(ArmDataSyncronizationBarrier):
|
bx LR
|
||||||
ASM_PFX(ArmDrainWriteBuffer):
|
|
||||||
dsb
|
ASM_PFX(ArmInstructionSynchronizationBarrier):
|
||||||
bx LR
|
isb
|
||||||
|
bx LR
|
||||||
ASM_PFX(ArmInstructionSynchronizationBarrier):
|
|
||||||
isb
|
ASM_PFX(ArmWriteVBar):
|
||||||
bx LR
|
# Set the Address of the Vector Table in the VBAR register
|
||||||
|
mcr p15, 0, r0, c12, c0, 0
|
||||||
ASM_PFX(ArmWriteNsacr):
|
# Ensure the SCTLR.V bit is clear
|
||||||
mcr p15, 0, r0, c1, c1, 2
|
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
|
||||||
bx lr
|
bic r0, r0, #0x00002000 @ clear V bit
|
||||||
|
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
|
||||||
ASM_PFX(ArmWriteScr):
|
isb
|
||||||
mcr p15, 0, r0, c1, c1, 0
|
bx lr
|
||||||
bx lr
|
|
||||||
|
ASM_PFX(ArmEnableVFP):
|
||||||
ASM_PFX(ArmWriteAuxCr):
|
# Read CPACR (Coprocessor Access Control Register)
|
||||||
mcr p15, 0, r0, c1, c0, 1
|
mrc p15, 0, r0, c1, c0, 2
|
||||||
bx lr
|
# Enable VPF access (Full Access to CP10, CP11) (V* instructions)
|
||||||
|
orr r0, r0, #0x00f00000
|
||||||
ASM_PFX(ArmReadAuxCr):
|
# Write back CPACR (Coprocessor Access Control Register)
|
||||||
mrc p15, 0, r0, c1, c0, 1
|
mcr p15, 0, r0, c1, c0, 2
|
||||||
bx lr
|
# Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
|
||||||
|
mov r0, #0x40000000
|
||||||
ASM_PFX(ArmWriteVMBar):
|
mcr p10,#0x7,r0,c8,c0,#0
|
||||||
mcr p15, 0, r0, c12, c0, 1
|
bx lr
|
||||||
bx lr
|
|
||||||
|
ASM_PFX(ArmCallWFI):
|
||||||
ASM_PFX(ArmWriteVBar):
|
wfi
|
||||||
# Set the Address of the Vector Table in the VBAR register
|
bx lr
|
||||||
mcr p15, 0, r0, c12, c0, 0
|
|
||||||
# Ensure the SCTLR.V bit is clear
|
#Note: Return 0 in Uniprocessor implementation
|
||||||
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
|
ASM_PFX(ArmReadCbar):
|
||||||
bic r0, r0, #0x00002000 @ clear V bit
|
mrc p15, 4, r0, c15, c0, 0 @ Read Configuration Base Address Register
|
||||||
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
|
bx lr
|
||||||
isb
|
|
||||||
bx lr
|
ASM_PFX(ArmInvalidateInstructionAndDataTlb):
|
||||||
|
mcr p15, 0, r0, c8, c7, 0 @ Invalidate Inst TLB and Data TLB
|
||||||
ASM_PFX(ArmWriteCPACR):
|
dsb
|
||||||
mcr p15, 0, r0, c1, c0, 2
|
bx lr
|
||||||
bx lr
|
|
||||||
|
ASM_PFX(ArmReadMpidr):
|
||||||
ASM_PFX(ArmEnableVFP):
|
mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
|
||||||
# Read CPACR (Coprocessor Access Control Register)
|
bx lr
|
||||||
mrc p15, 0, r0, c1, c0, 2
|
|
||||||
# Enable VPF access (Full Access to CP10, CP11) (V* instructions)
|
ASM_PFX(ArmReadTpidrurw):
|
||||||
orr r0, r0, #0x00f00000
|
mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW
|
||||||
# Write back CPACR (Coprocessor Access Control Register)
|
bx lr
|
||||||
mcr p15, 0, r0, c1, c0, 2
|
|
||||||
# Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
|
ASM_PFX(ArmWriteTpidrurw):
|
||||||
mov r0, #0x40000000
|
mcr p15, 0, r0, c13, c0, 2 @ write TPIDRURW
|
||||||
mcr p10,#0x7,r0,c8,c0,#0
|
bx lr
|
||||||
bx lr
|
|
||||||
|
ASM_PFX(ArmIsArchTimerImplemented):
|
||||||
ASM_PFX(ArmCallWFI):
|
mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1
|
||||||
wfi
|
and r0, r0, #0x000F0000
|
||||||
bx lr
|
bx lr
|
||||||
|
|
||||||
#Note: Return 0 in Uniprocessor implementation
|
ASM_PFX(ArmReadIdPfr1):
|
||||||
ASM_PFX(ArmReadCbar):
|
mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1 Register
|
||||||
mrc p15, 4, r0, c15, c0, 0 @ Read Configuration Base Address Register
|
bx lr
|
||||||
bx lr
|
|
||||||
|
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
|
||||||
ASM_PFX(ArmInvalidateInstructionAndDataTlb):
|
|
||||||
mcr p15, 0, r0, c8, c7, 0 @ Invalidate Inst TLB and Data TLB
|
|
||||||
dsb
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
ASM_PFX(ArmReadMpidr):
|
|
||||||
mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
ASM_PFX(ArmReadTpidrurw):
|
|
||||||
mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
ASM_PFX(ArmWriteTpidrurw):
|
|
||||||
mcr p15, 0, r0, c13, c0, 2 @ write TPIDRURW
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
|
|
||||||
|
|||||||
@@ -1,357 +1,334 @@
|
|||||||
//------------------------------------------------------------------------------
|
//------------------------------------------------------------------------------
|
||||||
//
|
//
|
||||||
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
|
||||||
//
|
// Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||||
// This program and the accompanying materials
|
//
|
||||||
// are licensed and made available under the terms and conditions of the BSD License
|
// This program and the accompanying materials
|
||||||
// which accompanies this distribution. The full text of the license may be found at
|
// are licensed and made available under the terms and conditions of the BSD License
|
||||||
// http://opensource.org/licenses/bsd-license.php
|
// which accompanies this distribution. The full text of the license may be found at
|
||||||
//
|
// http://opensource.org/licenses/bsd-license.php
|
||||||
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
//
|
||||||
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||||
//
|
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||||
//------------------------------------------------------------------------------
|
//
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
EXPORT ArmInvalidateInstructionCache
|
|
||||||
EXPORT ArmInvalidateDataCacheEntryByMVA
|
EXPORT ArmInvalidateInstructionCache
|
||||||
EXPORT ArmCleanDataCacheEntryByMVA
|
EXPORT ArmInvalidateDataCacheEntryByMVA
|
||||||
EXPORT ArmCleanInvalidateDataCacheEntryByMVA
|
EXPORT ArmCleanDataCacheEntryByMVA
|
||||||
EXPORT ArmInvalidateDataCacheEntryBySetWay
|
EXPORT ArmCleanInvalidateDataCacheEntryByMVA
|
||||||
EXPORT ArmCleanDataCacheEntryBySetWay
|
EXPORT ArmInvalidateDataCacheEntryBySetWay
|
||||||
EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
|
EXPORT ArmCleanDataCacheEntryBySetWay
|
||||||
EXPORT ArmDrainWriteBuffer
|
EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
|
||||||
EXPORT ArmEnableMmu
|
EXPORT ArmDrainWriteBuffer
|
||||||
EXPORT ArmDisableMmu
|
EXPORT ArmEnableMmu
|
||||||
EXPORT ArmDisableCachesAndMmu
|
EXPORT ArmDisableMmu
|
||||||
EXPORT ArmMmuEnabled
|
EXPORT ArmDisableCachesAndMmu
|
||||||
EXPORT ArmEnableDataCache
|
EXPORT ArmMmuEnabled
|
||||||
EXPORT ArmDisableDataCache
|
EXPORT ArmEnableDataCache
|
||||||
EXPORT ArmEnableInstructionCache
|
EXPORT ArmDisableDataCache
|
||||||
EXPORT ArmDisableInstructionCache
|
EXPORT ArmEnableInstructionCache
|
||||||
EXPORT ArmEnableSWPInstruction
|
EXPORT ArmDisableInstructionCache
|
||||||
EXPORT ArmEnableBranchPrediction
|
EXPORT ArmEnableSWPInstruction
|
||||||
EXPORT ArmDisableBranchPrediction
|
EXPORT ArmEnableBranchPrediction
|
||||||
EXPORT ArmSetLowVectors
|
EXPORT ArmDisableBranchPrediction
|
||||||
EXPORT ArmSetHighVectors
|
EXPORT ArmSetLowVectors
|
||||||
EXPORT ArmV7AllDataCachesOperation
|
EXPORT ArmSetHighVectors
|
||||||
EXPORT ArmDataMemoryBarrier
|
EXPORT ArmV7AllDataCachesOperation
|
||||||
EXPORT ArmDataSyncronizationBarrier
|
EXPORT ArmDataMemoryBarrier
|
||||||
EXPORT ArmInstructionSynchronizationBarrier
|
EXPORT ArmDataSyncronizationBarrier
|
||||||
EXPORT ArmWriteNsacr
|
EXPORT ArmInstructionSynchronizationBarrier
|
||||||
EXPORT ArmWriteScr
|
EXPORT ArmWriteVBar
|
||||||
EXPORT ArmWriteVMBar
|
EXPORT ArmEnableVFP
|
||||||
EXPORT ArmWriteVBar
|
EXPORT ArmCallWFI
|
||||||
EXPORT ArmReadVBar
|
EXPORT ArmReadCbar
|
||||||
EXPORT ArmWriteCPACR
|
EXPORT ArmInvalidateInstructionAndDataTlb
|
||||||
EXPORT ArmEnableVFP
|
EXPORT ArmReadMpidr
|
||||||
EXPORT ArmCallWFI
|
EXPORT ArmReadTpidrurw
|
||||||
EXPORT ArmWriteAuxCr
|
EXPORT ArmWriteTpidrurw
|
||||||
EXPORT ArmReadAuxCr
|
EXPORT ArmIsArchTimerImplemented
|
||||||
EXPORT ArmReadCbar
|
EXPORT ArmReadIdPfr1
|
||||||
EXPORT ArmInvalidateInstructionAndDataTlb
|
|
||||||
EXPORT ArmReadMpidr
|
AREA ArmV7Support, CODE, READONLY
|
||||||
EXPORT ArmReadTpidrurw
|
PRESERVE8
|
||||||
EXPORT ArmWriteTpidrurw
|
|
||||||
|
DC_ON EQU ( 0x1:SHL:2 )
|
||||||
AREA ArmCacheLib, CODE, READONLY
|
IC_ON EQU ( 0x1:SHL:12 )
|
||||||
PRESERVE8
|
CTRL_M_BIT EQU (1 << 0)
|
||||||
|
CTRL_C_BIT EQU (1 << 2)
|
||||||
DC_ON EQU ( 0x1:SHL:2 )
|
CTRL_B_BIT EQU (1 << 7)
|
||||||
IC_ON EQU ( 0x1:SHL:12 )
|
CTRL_I_BIT EQU (1 << 12)
|
||||||
CTRL_M_BIT EQU (1 << 0)
|
|
||||||
CTRL_C_BIT EQU (1 << 2)
|
|
||||||
CTRL_B_BIT EQU (1 << 7)
|
ArmInvalidateDataCacheEntryByMVA
|
||||||
CTRL_I_BIT EQU (1 << 12)
|
mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
|
||||||
|
dsb
|
||||||
|
isb
|
||||||
ArmInvalidateDataCacheEntryByMVA
|
bx lr
|
||||||
mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
|
|
||||||
dsb
|
ArmCleanDataCacheEntryByMVA
|
||||||
isb
|
mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
|
||||||
bx lr
|
dsb
|
||||||
|
isb
|
||||||
|
bx lr
|
||||||
ArmCleanDataCacheEntryByMVA
|
|
||||||
mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
|
|
||||||
dsb
|
ArmCleanInvalidateDataCacheEntryByMVA
|
||||||
isb
|
mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
|
||||||
bx lr
|
dsb
|
||||||
|
isb
|
||||||
|
bx lr
|
||||||
ArmCleanInvalidateDataCacheEntryByMVA
|
|
||||||
mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
|
|
||||||
dsb
|
ArmInvalidateDataCacheEntryBySetWay
|
||||||
isb
|
mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
|
||||||
bx lr
|
dsb
|
||||||
|
isb
|
||||||
|
bx lr
|
||||||
ArmInvalidateDataCacheEntryBySetWay
|
|
||||||
mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
|
|
||||||
dsb
|
ArmCleanInvalidateDataCacheEntryBySetWay
|
||||||
isb
|
mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
|
||||||
bx lr
|
dsb
|
||||||
|
isb
|
||||||
|
bx lr
|
||||||
ArmCleanInvalidateDataCacheEntryBySetWay
|
|
||||||
mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
|
|
||||||
dsb
|
ArmCleanDataCacheEntryBySetWay
|
||||||
isb
|
mcr p15, 0, r0, c7, c10, 2 ; Clean this line
|
||||||
bx lr
|
dsb
|
||||||
|
isb
|
||||||
|
bx lr
|
||||||
ArmCleanDataCacheEntryBySetWay
|
|
||||||
mcr p15, 0, r0, c7, c10, 2 ; Clean this line
|
|
||||||
dsb
|
ArmInvalidateInstructionCache
|
||||||
isb
|
mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
|
||||||
bx lr
|
isb
|
||||||
|
bx LR
|
||||||
|
|
||||||
ArmInvalidateInstructionCache
|
ArmEnableMmu
|
||||||
mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
|
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||||
isb
|
orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU
|
||||||
bx LR
|
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||||
|
dsb
|
||||||
ArmEnableMmu
|
isb
|
||||||
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
|
bx LR
|
||||||
orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU
|
|
||||||
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
|
ArmDisableMmu
|
||||||
dsb
|
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||||
isb
|
bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU
|
||||||
bx LR
|
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||||
|
|
||||||
ArmMmuEnabled
|
mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB
|
||||||
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
|
mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array
|
||||||
and R0,R0,#1
|
dsb
|
||||||
bx LR
|
isb
|
||||||
|
bx LR
|
||||||
ArmDisableMmu
|
|
||||||
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
|
ArmDisableCachesAndMmu
|
||||||
bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU
|
mrc p15, 0, r0, c1, c0, 0 ; Get control register
|
||||||
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
|
bic r0, r0, #CTRL_M_BIT ; Disable MMU
|
||||||
|
bic r0, r0, #CTRL_C_BIT ; Disable D Cache
|
||||||
mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB
|
bic r0, r0, #CTRL_I_BIT ; Disable I Cache
|
||||||
mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array
|
mcr p15, 0, r0, c1, c0, 0 ; Write control register
|
||||||
dsb
|
dsb
|
||||||
isb
|
isb
|
||||||
bx LR
|
bx LR
|
||||||
|
|
||||||
ArmDisableCachesAndMmu
|
ArmMmuEnabled
|
||||||
mrc p15, 0, r0, c1, c0, 0 ; Get control register
|
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||||
bic r0, r0, #CTRL_M_BIT ; Disable MMU
|
and R0,R0,#1
|
||||||
bic r0, r0, #CTRL_C_BIT ; Disable D Cache
|
bx LR
|
||||||
bic r0, r0, #CTRL_I_BIT ; Disable I Cache
|
|
||||||
mcr p15, 0, r0, c1, c0, 0 ; Write control register
|
ArmEnableDataCache
|
||||||
dsb
|
ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
|
||||||
isb
|
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||||
bx LR
|
orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled
|
||||||
|
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||||
ArmEnableDataCache
|
dsb
|
||||||
ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
|
isb
|
||||||
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
|
bx LR
|
||||||
orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled
|
|
||||||
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
|
ArmDisableDataCache
|
||||||
dsb
|
ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
|
||||||
isb
|
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||||
bx LR
|
bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled
|
||||||
|
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||||
ArmDisableDataCache
|
dsb
|
||||||
ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
|
isb
|
||||||
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
|
bx LR
|
||||||
bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled
|
|
||||||
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
|
ArmEnableInstructionCache
|
||||||
isb
|
ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
|
||||||
bx LR
|
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||||
|
orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled
|
||||||
ArmEnableInstructionCache
|
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||||
ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
|
dsb
|
||||||
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
|
isb
|
||||||
orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled
|
bx LR
|
||||||
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
|
|
||||||
dsb
|
ArmDisableInstructionCache
|
||||||
isb
|
ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
|
||||||
bx LR
|
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||||
|
BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled
|
||||||
ArmDisableInstructionCache
|
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||||
ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
|
isb
|
||||||
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
|
bx LR
|
||||||
BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled
|
|
||||||
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
|
ArmEnableSWPInstruction
|
||||||
isb
|
mrc p15, 0, r0, c1, c0, 0
|
||||||
bx LR
|
orr r0, r0, #0x00000400
|
||||||
|
mcr p15, 0, r0, c1, c0, 0
|
||||||
ArmEnableSWPInstruction
|
isb
|
||||||
mrc p15, 0, r0, c1, c0, 0
|
bx LR
|
||||||
orr r0, r0, #0x00000400
|
|
||||||
mcr p15, 0, r0, c1, c0, 0
|
ArmEnableBranchPrediction
|
||||||
isb
|
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||||
bx LR
|
orr r0, r0, #0x00000800 ;
|
||||||
|
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||||
ArmEnableBranchPrediction
|
dsb
|
||||||
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
|
isb
|
||||||
orr r0, r0, #0x00000800 ;
|
bx LR
|
||||||
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
|
|
||||||
isb
|
ArmDisableBranchPrediction
|
||||||
bx LR
|
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||||
|
bic r0, r0, #0x00000800 ;
|
||||||
ArmDisableBranchPrediction
|
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||||
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
|
dsb
|
||||||
bic r0, r0, #0x00000800 ;
|
isb
|
||||||
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
|
bx LR
|
||||||
isb
|
|
||||||
bx LR
|
ArmSetLowVectors
|
||||||
|
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||||
ArmSetLowVectors
|
bic r0, r0, #0x00002000 ; clear V bit
|
||||||
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
|
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||||
bic r0, r0, #0x00002000 ; clear V bit
|
isb
|
||||||
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
|
bx LR
|
||||||
isb
|
|
||||||
bx LR
|
ArmSetHighVectors
|
||||||
|
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||||
ArmSetHighVectors
|
orr r0, r0, #0x00002000 ; clear V bit
|
||||||
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
|
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||||
orr r0, r0, #0x00002000 ; clear V bit
|
isb
|
||||||
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
|
bx LR
|
||||||
isb
|
|
||||||
bx LR
|
ArmV7AllDataCachesOperation
|
||||||
|
stmfd SP!,{r4-r12, LR}
|
||||||
ArmV7AllDataCachesOperation
|
mov R1, R0 ; Save Function call in R1
|
||||||
stmfd SP!,{r4-r12, LR}
|
mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR
|
||||||
mov R1, R0 ; Save Function call in R1
|
ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)
|
||||||
mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR
|
mov R3, R3, LSR #23 ; Cache level value (naturally aligned)
|
||||||
ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)
|
beq Finished
|
||||||
mov R3, R3, LSR #23 ; Cache level value (naturally aligned)
|
mov R10, #0
|
||||||
beq Finished
|
|
||||||
mov R10, #0
|
Loop1
|
||||||
|
add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
|
||||||
Loop1
|
mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
|
||||||
add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
|
and R12, R12, #7 ; get those 3 bits alone
|
||||||
mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
|
cmp R12, #2
|
||||||
and R12, R12, #7 ; get those 3 bits alone
|
blt Skip ; no cache or only instruction cache at this level
|
||||||
cmp R12, #2
|
mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
|
||||||
blt Skip ; no cache or only instruction cache at this level
|
isb ; isb to sync the change to the CacheSizeID reg
|
||||||
mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
|
mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
|
||||||
isb ; isb to sync the change to the CacheSizeID reg
|
and R2, R12, #&7 ; extract the line length field
|
||||||
mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
|
add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
|
||||||
and R2, R12, #&7 ; extract the line length field
|
ldr R4, =0x3FF
|
||||||
add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
|
ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
|
||||||
ldr R4, =0x3FF
|
clz R5, R4 ; R5 is the bit position of the way size increment
|
||||||
ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
|
ldr R7, =0x00007FFF
|
||||||
clz R5, R4 ; R5 is the bit position of the way size increment
|
ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
|
||||||
ldr R7, =0x00007FFF
|
|
||||||
ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
|
Loop2
|
||||||
|
mov R9, R4 ; R9 working copy of the max way size (right aligned)
|
||||||
Loop2
|
|
||||||
mov R9, R4 ; R9 working copy of the max way size (right aligned)
|
Loop3
|
||||||
|
orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11
|
||||||
Loop3
|
orr R0, R0, R7, LSL R2 ; factor in the index number
|
||||||
orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11
|
|
||||||
orr R0, R0, R7, LSL R2 ; factor in the index number
|
blx R1
|
||||||
|
|
||||||
blx R1
|
subs R9, R9, #1 ; decrement the way number
|
||||||
|
bge Loop3
|
||||||
subs R9, R9, #1 ; decrement the way number
|
subs R7, R7, #1 ; decrement the index
|
||||||
bge Loop3
|
bge Loop2
|
||||||
subs R7, R7, #1 ; decrement the index
|
Skip
|
||||||
bge Loop2
|
add R10, R10, #2 ; increment the cache number
|
||||||
Skip
|
cmp R3, R10
|
||||||
add R10, R10, #2 ; increment the cache number
|
bgt Loop1
|
||||||
cmp R3, R10
|
|
||||||
bgt Loop1
|
Finished
|
||||||
|
dsb
|
||||||
Finished
|
ldmfd SP!, {r4-r12, lr}
|
||||||
dsb
|
bx LR
|
||||||
ldmfd SP!, {r4-r12, lr}
|
|
||||||
bx LR
|
ArmDataMemoryBarrier
|
||||||
|
dmb
|
||||||
|
bx LR
|
||||||
ArmDataMemoryBarrier
|
|
||||||
dmb
|
ArmDataSyncronizationBarrier
|
||||||
bx LR
|
ArmDrainWriteBuffer
|
||||||
|
dsb
|
||||||
ArmDataSyncronizationBarrier
|
bx LR
|
||||||
ArmDrainWriteBuffer
|
|
||||||
dsb
|
ArmInstructionSynchronizationBarrier
|
||||||
bx LR
|
isb
|
||||||
|
bx LR
|
||||||
ArmInstructionSynchronizationBarrier
|
|
||||||
isb
|
ArmWriteVBar
|
||||||
bx LR
|
// Set the Address of the Vector Table in the VBAR register
|
||||||
|
mcr p15, 0, r0, c12, c0, 0
|
||||||
ArmWriteNsacr
|
// Ensure the SCTLR.V bit is clear
|
||||||
mcr p15, 0, r0, c1, c1, 2
|
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||||
bx lr
|
bic r0, r0, #0x00002000 ; clear V bit
|
||||||
|
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||||
ArmWriteScr
|
isb
|
||||||
mcr p15, 0, r0, c1, c1, 0
|
bx lr
|
||||||
bx lr
|
|
||||||
|
ArmEnableVFP
|
||||||
ArmWriteAuxCr
|
// Read CPACR (Coprocessor Access Control Register)
|
||||||
mcr p15, 0, r0, c1, c0, 1
|
mrc p15, 0, r0, c1, c0, 2
|
||||||
bx lr
|
// Enable VPF access (Full Access to CP10, CP11) (V* instructions)
|
||||||
|
orr r0, r0, #0x00f00000
|
||||||
ArmReadAuxCr
|
// Write back CPACR (Coprocessor Access Control Register)
|
||||||
mrc p15, 0, r0, c1, c0, 1
|
mcr p15, 0, r0, c1, c0, 2
|
||||||
bx lr
|
// Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
|
||||||
|
mov r0, #0x40000000
|
||||||
ArmWriteVMBar
|
mcr p10,#0x7,r0,c8,c0,#0
|
||||||
mcr p15, 0, r0, c12, c0, 1
|
bx lr
|
||||||
bx lr
|
|
||||||
|
ArmCallWFI
|
||||||
ArmWriteVBar
|
wfi
|
||||||
// Set the Address of the Vector Table in the VBAR register
|
bx lr
|
||||||
mcr p15, 0, r0, c12, c0, 0
|
|
||||||
// Ensure the SCTLR.V bit is clear
|
//Note: Return 0 in Uniprocessor implementation
|
||||||
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
|
ArmReadCbar
|
||||||
bic r0, r0, #0x00002000 ; clear V bit
|
mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register
|
||||||
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
|
bx lr
|
||||||
isb
|
|
||||||
bx lr
|
ArmInvalidateInstructionAndDataTlb
|
||||||
|
mcr p15, 0, r0, c8, c7, 0 ; Invalidate Inst TLB and Data TLB
|
||||||
ArmReadVBar
|
dsb
|
||||||
mrc p15, 0, r0, c12, c0, 0
|
bx lr
|
||||||
bx lr
|
|
||||||
|
ArmReadMpidr
|
||||||
ArmWriteCPACR
|
mrc p15, 0, r0, c0, c0, 5 ; read MPIDR
|
||||||
mcr p15, 0, r0, c1, c0, 2
|
bx lr
|
||||||
bx lr
|
|
||||||
|
ArmReadTpidrurw
|
||||||
ArmEnableVFP
|
mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW
|
||||||
// Read CPACR (Coprocessor Access Control Register)
|
bx lr
|
||||||
mrc p15, 0, r0, c1, c0, 2
|
|
||||||
// Enable VPF access (Full Access to CP10, CP11) (V* instructions)
|
ArmWriteTpidrurw
|
||||||
orr r0, r0, #0x00f00000
|
mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW
|
||||||
// Write back CPACR (Coprocessor Access Control Register)
|
bx lr
|
||||||
mcr p15, 0, r0, c1, c0, 2
|
|
||||||
// Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
|
ArmIsArchTimerImplemented
|
||||||
mov r0, #0x40000000
|
mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1
|
||||||
mcr p10,#0x7,r0,c8,c0,#0
|
and r0, r0, #0x000F0000
|
||||||
bx lr
|
bx lr
|
||||||
|
|
||||||
ArmCallWFI
|
ArmReadIdPfr1
|
||||||
wfi
|
mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register
|
||||||
bx lr
|
bx lr
|
||||||
|
|
||||||
//Note: Return 0 in Uniprocessor implementation
|
END
|
||||||
ArmReadCbar
|
|
||||||
mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
ArmInvalidateInstructionAndDataTlb
|
|
||||||
mcr p15, 0, r0, c8, c7, 0 ; Invalidate Inst TLB and Data TLB
|
|
||||||
dsb
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
ArmReadMpidr
|
|
||||||
mrc p15, 0, r0, c0, c0, 5 ; read MPIDR
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
ArmReadTpidrurw
|
|
||||||
mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
ArmWriteTpidrurw
|
|
||||||
mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
END
|
|
||||||
|
|
||||||
|
|||||||
@@ -58,3 +58,15 @@ ArmProcessorMode (
|
|||||||
{
|
{
|
||||||
return (ARM_PROCESSOR_MODE)(CPSRRead() & (UINT32)ARM_PROCESSOR_MODE_MASK);
|
return (ARM_PROCESSOR_MODE)(CPSRRead() & (UINT32)ARM_PROCESSOR_MODE_MASK);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
VOID
|
||||||
|
EFIAPI
|
||||||
|
ArmSetAuxCrBit (
|
||||||
|
IN UINT32 Bits
|
||||||
|
)
|
||||||
|
{
|
||||||
|
UINT32 val = ArmReadAuxCr();
|
||||||
|
val |= Bits;
|
||||||
|
ArmWriteAuxCr(val);
|
||||||
|
}
|
||||||
|
|
||||||
|
|||||||
@@ -1,124 +1,148 @@
|
|||||||
#------------------------------------------------------------------------------
|
#------------------------------------------------------------------------------
|
||||||
#
|
#
|
||||||
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||||
#
|
# Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||||
# This program and the accompanying materials
|
#
|
||||||
# are licensed and made available under the terms and conditions of the BSD License
|
# This program and the accompanying materials
|
||||||
# which accompanies this distribution. The full text of the license may be found at
|
# are licensed and made available under the terms and conditions of the BSD License
|
||||||
# http://opensource.org/licenses/bsd-license.php
|
# which accompanies this distribution. The full text of the license may be found at
|
||||||
#
|
# http://opensource.org/licenses/bsd-license.php
|
||||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
#
|
||||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||||
#
|
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||||
#------------------------------------------------------------------------------
|
#
|
||||||
|
#------------------------------------------------------------------------------
|
||||||
#include <AsmMacroIoLib.h>
|
|
||||||
|
#include <AsmMacroIoLib.h>
|
||||||
.text
|
|
||||||
.align 2
|
#ifdef ARM_CPU_ARMv6
|
||||||
GCC_ASM_EXPORT(Cp15IdCode)
|
// No memory barriers for ARMv6
|
||||||
GCC_ASM_EXPORT(Cp15CacheInfo)
|
#define isb
|
||||||
GCC_ASM_EXPORT(ArmEnableInterrupts)
|
#define dsb
|
||||||
GCC_ASM_EXPORT(ArmDisableInterrupts)
|
#endif
|
||||||
GCC_ASM_EXPORT(ArmGetInterruptState)
|
|
||||||
GCC_ASM_EXPORT(ArmEnableFiq)
|
.text
|
||||||
GCC_ASM_EXPORT(ArmDisableFiq)
|
.align 2
|
||||||
GCC_ASM_EXPORT(ArmGetFiqState)
|
GCC_ASM_EXPORT(Cp15IdCode)
|
||||||
GCC_ASM_EXPORT(ArmInvalidateTlb)
|
GCC_ASM_EXPORT(Cp15CacheInfo)
|
||||||
GCC_ASM_EXPORT(ArmSetTTBR0)
|
GCC_ASM_EXPORT(ArmGetInterruptState)
|
||||||
GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)
|
GCC_ASM_EXPORT(ArmGetFiqState)
|
||||||
GCC_ASM_EXPORT(ArmSetDomainAccessControl)
|
GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)
|
||||||
GCC_ASM_EXPORT(CPSRMaskInsert)
|
GCC_ASM_EXPORT(ArmSetTTBR0)
|
||||||
GCC_ASM_EXPORT(CPSRRead)
|
GCC_ASM_EXPORT(ArmSetDomainAccessControl)
|
||||||
|
GCC_ASM_EXPORT(CPSRMaskInsert)
|
||||||
#------------------------------------------------------------------------------
|
GCC_ASM_EXPORT(CPSRRead)
|
||||||
|
GCC_ASM_EXPORT(ArmWriteCPACR)
|
||||||
ASM_PFX(Cp15IdCode):
|
GCC_ASM_EXPORT(ArmWriteAuxCr)
|
||||||
mrc p15,0,R0,c0,c0,0
|
GCC_ASM_EXPORT(ArmReadAuxCr)
|
||||||
bx LR
|
GCC_ASM_EXPORT(ArmInvalidateTlb)
|
||||||
|
GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
|
||||||
ASM_PFX(Cp15CacheInfo):
|
GCC_ASM_EXPORT(ArmWriteNsacr)
|
||||||
mrc p15,0,R0,c0,c0,1
|
GCC_ASM_EXPORT(ArmWriteScr)
|
||||||
bx LR
|
GCC_ASM_EXPORT(ArmWriteVMBar)
|
||||||
|
|
||||||
ASM_PFX(ArmEnableInterrupts):
|
#------------------------------------------------------------------------------
|
||||||
mrs R0,CPSR
|
|
||||||
bic R0,R0,#0x80 @Enable IRQ interrupts
|
ASM_PFX(Cp15IdCode):
|
||||||
msr CPSR_c,R0
|
mrc p15,0,R0,c0,c0,0
|
||||||
bx LR
|
bx LR
|
||||||
|
|
||||||
ASM_PFX(ArmDisableInterrupts):
|
ASM_PFX(Cp15CacheInfo):
|
||||||
mrs R0,CPSR
|
mrc p15,0,R0,c0,c0,1
|
||||||
orr R1,R0,#0x80 @Disable IRQ interrupts
|
bx LR
|
||||||
msr CPSR_c,R1
|
|
||||||
tst R0,#0x80
|
ASM_PFX(ArmGetInterruptState):
|
||||||
moveq R0,#1
|
mrs R0,CPSR
|
||||||
movne R0,#0
|
tst R0,#0x80 @Check if IRQ is enabled.
|
||||||
bx LR
|
moveq R0,#1
|
||||||
|
movne R0,#0
|
||||||
ASM_PFX(ArmGetInterruptState):
|
bx LR
|
||||||
mrs R0,CPSR
|
|
||||||
tst R0,#0x80 @Check if IRQ is enabled.
|
ASM_PFX(ArmGetFiqState):
|
||||||
moveq R0,#1
|
mrs R0,CPSR
|
||||||
movne R0,#0
|
tst R0,#0x40 @Check if FIQ is enabled.
|
||||||
bx LR
|
moveq R0,#1
|
||||||
|
movne R0,#0
|
||||||
ASM_PFX(ArmEnableFiq):
|
bx LR
|
||||||
mrs R0,CPSR
|
|
||||||
bic R0,R0,#0x40 @Enable FIQ interrupts
|
ASM_PFX(ArmSetDomainAccessControl):
|
||||||
msr CPSR_c,R0
|
mcr p15,0,r0,c3,c0,0
|
||||||
bx LR
|
bx lr
|
||||||
|
|
||||||
ASM_PFX(ArmDisableFiq):
|
ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert
|
||||||
mrs R0,CPSR
|
stmfd sp!, {r4-r12, lr} @ save all the banked registers
|
||||||
orr R1,R0,#0x40 @Disable FIQ interrupts
|
mov r3, sp @ copy the stack pointer into a non-banked register
|
||||||
msr CPSR_c,R1
|
mrs r2, cpsr @ read the cpsr
|
||||||
tst R0,#0x80
|
bic r2, r2, r0 @ clear mask in the cpsr
|
||||||
moveq R0,#1
|
and r1, r1, r0 @ clear bits outside the mask in the input
|
||||||
movne R0,#0
|
orr r2, r2, r1 @ set field
|
||||||
bx LR
|
msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)
|
||||||
|
isb
|
||||||
ASM_PFX(ArmGetFiqState):
|
mov sp, r3 @ restore stack pointer
|
||||||
mrs R0,CPSR
|
ldmfd sp!, {r4-r12, lr} @ restore registers
|
||||||
tst R0,#0x80 @Check if FIQ is enabled.
|
bx lr @ return (hopefully thumb-safe!) @ return (hopefully thumb-safe!)
|
||||||
moveq R0,#1
|
|
||||||
movne R0,#0
|
ASM_PFX(CPSRRead):
|
||||||
bx LR
|
mrs r0, cpsr
|
||||||
|
bx lr
|
||||||
ASM_PFX(ArmInvalidateTlb):
|
|
||||||
mov r0,#0
|
ASM_PFX(ArmWriteCPACR):
|
||||||
mcr p15,0,r0,c8,c7,0
|
mcr p15, 0, r0, c1, c0, 2
|
||||||
bx lr
|
bx lr
|
||||||
|
|
||||||
ASM_PFX(ArmSetTTBR0):
|
ASM_PFX(ArmWriteAuxCr):
|
||||||
mcr p15,0,r0,c2,c0,0
|
mcr p15, 0, r0, c1, c0, 1
|
||||||
bx lr
|
bx lr
|
||||||
|
|
||||||
ASM_PFX(ArmGetTTBR0BaseAddress):
|
ASM_PFX(ArmReadAuxCr):
|
||||||
mrc p15,0,r0,c2,c0,0
|
mrc p15, 0, r0, c1, c0, 1
|
||||||
LoadConstantToReg(0xFFFFC000, r1) @ and r0, r0, #0xFFFFC000
|
bx lr
|
||||||
and r0, r0, r1
|
|
||||||
bx lr
|
ASM_PFX(ArmSetTTBR0):
|
||||||
|
mcr p15,0,r0,c2,c0,0
|
||||||
|
isb
|
||||||
ASM_PFX(ArmSetDomainAccessControl):
|
bx lr
|
||||||
mcr p15,0,r0,c3,c0,0
|
|
||||||
bx lr
|
ASM_PFX(ArmGetTTBR0BaseAddress):
|
||||||
|
mrc p15,0,r0,c2,c0,0
|
||||||
ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert
|
LoadConstantToReg(0xFFFFC000, r1)
|
||||||
stmfd sp!, {r4-r12, lr} @ save all the banked registers
|
and r0, r0, r1
|
||||||
mov r3, sp @ copy the stack pointer into a non-banked register
|
isb
|
||||||
mrs r2, cpsr @ read the cpsr
|
bx lr
|
||||||
bic r2, r2, r0 @ clear mask in the cpsr
|
|
||||||
and r1, r1, r0 @ clear bits outside the mask in the input
|
//
|
||||||
orr r2, r2, r1 @ set field
|
//VOID
|
||||||
msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)
|
//ArmUpdateTranslationTableEntry (
|
||||||
mov sp, r3 @ restore stack pointer
|
// IN VOID *TranslationTableEntry // R0
|
||||||
ldmfd sp!, {r4-r12, lr} @ restore registers
|
// IN VOID *MVA // R1
|
||||||
bx lr @ return (hopefully thumb-safe!)
|
// );
|
||||||
|
ASM_PFX(ArmUpdateTranslationTableEntry):
|
||||||
ASM_PFX(CPSRRead):
|
mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA
|
||||||
mrs r0, cpsr
|
dsb
|
||||||
bx lr
|
mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA
|
||||||
|
mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
|
||||||
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
|
dsb
|
||||||
|
isb
|
||||||
|
bx lr
|
||||||
|
|
||||||
|
ASM_PFX(ArmInvalidateTlb):
|
||||||
|
mov r0,#0
|
||||||
|
mcr p15,0,r0,c8,c7,0
|
||||||
|
mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
|
||||||
|
dsb
|
||||||
|
isb
|
||||||
|
bx lr
|
||||||
|
|
||||||
|
ASM_PFX(ArmWriteNsacr):
|
||||||
|
mcr p15, 0, r0, c1, c1, 2
|
||||||
|
bx lr
|
||||||
|
|
||||||
|
ASM_PFX(ArmWriteScr):
|
||||||
|
mcr p15, 0, r0, c1, c1, 0
|
||||||
|
bx lr
|
||||||
|
|
||||||
|
ASM_PFX(ArmWriteVMBar):
|
||||||
|
mcr p15, 0, r0, c12, c0, 1
|
||||||
|
bx lr
|
||||||
|
|
||||||
|
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
|
||||||
|
|||||||
@@ -1,134 +1,148 @@
|
|||||||
//------------------------------------------------------------------------------
|
//------------------------------------------------------------------------------
|
||||||
//
|
//
|
||||||
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||||
//
|
// Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||||
// This program and the accompanying materials
|
//
|
||||||
// are licensed and made available under the terms and conditions of the BSD License
|
// This program and the accompanying materials
|
||||||
// which accompanies this distribution. The full text of the license may be found at
|
// are licensed and made available under the terms and conditions of the BSD License
|
||||||
// http://opensource.org/licenses/bsd-license.php
|
// which accompanies this distribution. The full text of the license may be found at
|
||||||
//
|
// http://opensource.org/licenses/bsd-license.php
|
||||||
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
//
|
||||||
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||||
//
|
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||||
//------------------------------------------------------------------------------
|
//
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
#include <AsmMacroIoLib.h>
|
|
||||||
|
#include <AsmMacroIoLib.h>
|
||||||
INCLUDE AsmMacroIoLib.inc
|
|
||||||
|
INCLUDE AsmMacroIoLib.inc
|
||||||
EXPORT Cp15IdCode
|
|
||||||
EXPORT Cp15CacheInfo
|
#ifdef ARM_CPU_ARMv6
|
||||||
EXPORT ArmIsMPCore
|
// No memory barriers for ARMv6
|
||||||
EXPORT ArmEnableInterrupts
|
#define isb
|
||||||
EXPORT ArmDisableInterrupts
|
#define dsb
|
||||||
EXPORT ArmGetInterruptState
|
#endif
|
||||||
EXPORT ArmEnableFiq
|
|
||||||
EXPORT ArmDisableFiq
|
EXPORT Cp15IdCode
|
||||||
EXPORT ArmGetFiqState
|
EXPORT Cp15CacheInfo
|
||||||
EXPORT ArmInvalidateTlb
|
EXPORT ArmGetInterruptState
|
||||||
EXPORT ArmSetTTBR0
|
EXPORT ArmGetFiqState
|
||||||
EXPORT ArmGetTTBR0BaseAddress
|
EXPORT ArmGetTTBR0BaseAddress
|
||||||
EXPORT ArmSetDomainAccessControl
|
EXPORT ArmSetTTBR0
|
||||||
EXPORT CPSRMaskInsert
|
EXPORT ArmSetDomainAccessControl
|
||||||
EXPORT CPSRRead
|
EXPORT CPSRMaskInsert
|
||||||
|
EXPORT CPSRRead
|
||||||
AREA ArmLibSupport, CODE, READONLY
|
EXPORT ArmWriteCPACR
|
||||||
|
EXPORT ArmWriteAuxCr
|
||||||
Cp15IdCode
|
EXPORT ArmReadAuxCr
|
||||||
mrc p15,0,R0,c0,c0,0
|
EXPORT ArmInvalidateTlb
|
||||||
bx LR
|
EXPORT ArmUpdateTranslationTableEntry
|
||||||
|
EXPORT ArmWriteNsacr
|
||||||
Cp15CacheInfo
|
EXPORT ArmWriteScr
|
||||||
mrc p15,0,R0,c0,c0,1
|
EXPORT ArmWriteVMBar
|
||||||
bx LR
|
|
||||||
|
AREA ArmLibSupport, CODE, READONLY
|
||||||
ArmIsMPCore
|
|
||||||
mrc p15,0,R0,c0,c0,5
|
Cp15IdCode
|
||||||
// Get Multiprocessing extension (bit31) & U bit (bit30)
|
mrc p15,0,R0,c0,c0,0
|
||||||
and R0, R0, #0xC0000000
|
bx LR
|
||||||
// if bit30 == 0 then the processor is part of a multiprocessor system)
|
|
||||||
and R0, R0, #0x80000000
|
Cp15CacheInfo
|
||||||
bx LR
|
mrc p15,0,R0,c0,c0,1
|
||||||
|
bx LR
|
||||||
ArmEnableInterrupts
|
|
||||||
mrs R0,CPSR
|
ArmGetInterruptState
|
||||||
bic R0,R0,#0x80 ;Enable IRQ interrupts
|
mrs R0,CPSR
|
||||||
msr CPSR_c,R0
|
tst R0,#0x80 // Check if IRQ is enabled.
|
||||||
bx LR
|
moveq R0,#1
|
||||||
|
movne R0,#0
|
||||||
ArmDisableInterrupts
|
bx LR
|
||||||
mrs R0,CPSR
|
|
||||||
orr R1,R0,#0x80 ;Disable IRQ interrupts
|
ArmGetFiqState
|
||||||
msr CPSR_c,R1
|
mrs R0,CPSR
|
||||||
tst R0,#0x80
|
tst R0,#0x40 // Check if FIQ is enabled.
|
||||||
moveq R0,#1
|
moveq R0,#1
|
||||||
movne R0,#0
|
movne R0,#0
|
||||||
bx LR
|
bx LR
|
||||||
|
|
||||||
ArmGetInterruptState
|
ArmSetDomainAccessControl
|
||||||
mrs R0,CPSR
|
mcr p15,0,r0,c3,c0,0
|
||||||
tst R0,#0x80 ;Check if IRQ is enabled.
|
bx lr
|
||||||
moveq R0,#1
|
|
||||||
movne R0,#0
|
CPSRMaskInsert // on entry, r0 is the mask and r1 is the field to insert
|
||||||
bx LR
|
stmfd sp!, {r4-r12, lr} // save all the banked registers
|
||||||
|
mov r3, sp // copy the stack pointer into a non-banked register
|
||||||
ArmEnableFiq
|
mrs r2, cpsr // read the cpsr
|
||||||
mrs R0,CPSR
|
bic r2, r2, r0 // clear mask in the cpsr
|
||||||
bic R0,R0,#0x40 ;Enable IRQ interrupts
|
and r1, r1, r0 // clear bits outside the mask in the input
|
||||||
msr CPSR_c,R0
|
orr r2, r2, r1 // set field
|
||||||
bx LR
|
msr cpsr_cxsf, r2 // write back cpsr (may have caused a mode switch)
|
||||||
|
isb
|
||||||
ArmDisableFiq
|
mov sp, r3 // restore stack pointer
|
||||||
mrs R0,CPSR
|
ldmfd sp!, {r4-r12, lr} // restore registers
|
||||||
orr R1,R0,#0x40 ;Disable IRQ interrupts
|
bx lr // return (hopefully thumb-safe!) // return (hopefully thumb-safe!)
|
||||||
msr CPSR_c,R1
|
|
||||||
tst R0,#0x40
|
CPSRRead
|
||||||
moveq R0,#1
|
mrs r0, cpsr
|
||||||
movne R0,#0
|
bx lr
|
||||||
bx LR
|
|
||||||
|
ArmWriteCPACR
|
||||||
ArmGetFiqState
|
mcr p15, 0, r0, c1, c0, 2
|
||||||
mrs R0,CPSR
|
bx lr
|
||||||
tst R0,#0x40 ;Check if IRQ is enabled.
|
|
||||||
moveq R0,#1
|
ArmWriteAuxCr
|
||||||
movne R0,#0
|
mcr p15, 0, r0, c1, c0, 1
|
||||||
bx LR
|
bx lr
|
||||||
|
|
||||||
ArmInvalidateTlb
|
ArmReadAuxCr
|
||||||
mov r0,#0
|
mrc p15, 0, r0, c1, c0, 1
|
||||||
mcr p15,0,r0,c8,c7,0
|
bx lr
|
||||||
bx lr
|
|
||||||
|
ArmSetTTBR0
|
||||||
ArmSetTTBR0
|
mcr p15,0,r0,c2,c0,0
|
||||||
mcr p15,0,r0,c2,c0,0
|
isb
|
||||||
bx lr
|
bx lr
|
||||||
|
|
||||||
ArmGetTTBR0BaseAddress
|
ArmGetTTBR0BaseAddress
|
||||||
mrc p15,0,r0,c2,c0,0
|
mrc p15,0,r0,c2,c0,0
|
||||||
LoadConstantToReg(0xFFFFC000,r1) // and r0, r0, #0xFFFFC000
|
LoadConstantToReg(0xFFFFC000, r1)
|
||||||
and r0, r0, r1
|
and r0, r0, r1
|
||||||
bx lr
|
isb
|
||||||
|
bx lr
|
||||||
ArmSetDomainAccessControl
|
|
||||||
mcr p15,0,r0,c3,c0,0
|
//
|
||||||
bx lr
|
//VOID
|
||||||
|
//ArmUpdateTranslationTableEntry (
|
||||||
CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert
|
// IN VOID *TranslationTableEntry // R0
|
||||||
stmfd sp!, {r4-r12, lr} ; save all the banked registers
|
// IN VOID *MVA // R1
|
||||||
mov r3, sp ; copy the stack pointer into a non-banked register
|
// );
|
||||||
mrs r2, cpsr ; read the cpsr
|
ArmUpdateTranslationTableEntry
|
||||||
bic r2, r2, r0 ; clear mask in the cpsr
|
mcr p15,0,R0,c7,c14,1 // DCCIMVAC Clean data cache by MVA
|
||||||
and r1, r1, r0 ; clear bits outside the mask in the input
|
dsb
|
||||||
orr r2, r2, r1 ; set field
|
mcr p15,0,R1,c8,c7,1 // TLBIMVA TLB Invalidate MVA
|
||||||
msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch)
|
mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp
|
||||||
mov sp, r3 ; restore stack pointer
|
dsb
|
||||||
ldmfd sp!, {r4-r12, lr} ; restore registers
|
isb
|
||||||
bx lr ; return (hopefully thumb-safe!)
|
bx lr
|
||||||
|
|
||||||
CPSRRead
|
ArmInvalidateTlb
|
||||||
mrs r0, cpsr
|
mov r0,#0
|
||||||
bx lr
|
mcr p15,0,r0,c8,c7,0
|
||||||
|
mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp
|
||||||
END
|
dsb
|
||||||
|
isb
|
||||||
|
bx lr
|
||||||
|
|
||||||
|
ArmWriteNsacr
|
||||||
|
mcr p15, 0, r0, c1, c1, 2
|
||||||
|
bx lr
|
||||||
|
|
||||||
|
ArmWriteScr
|
||||||
|
mcr p15, 0, r0, c1, c1, 0
|
||||||
|
bx lr
|
||||||
|
|
||||||
|
ArmWriteVMBar
|
||||||
|
mcr p15, 0, r0, c12, c0, 1
|
||||||
|
bx lr
|
||||||
|
|
||||||
|
END
|
||||||
|
|||||||
@@ -20,8 +20,6 @@
|
|||||||
#include <Library/MemoryAllocationLib.h>
|
#include <Library/MemoryAllocationLib.h>
|
||||||
#include <Library/PcdLib.h>
|
#include <Library/PcdLib.h>
|
||||||
|
|
||||||
#include <Chipset/ArmV7.h>
|
|
||||||
|
|
||||||
VOID
|
VOID
|
||||||
BuildMemoryTypeInformationHob (
|
BuildMemoryTypeInformationHob (
|
||||||
VOID
|
VOID
|
||||||
|
|||||||
@@ -16,8 +16,6 @@
|
|||||||
|
|
||||||
#include <Ppi/ArmMpCoreInfo.h>
|
#include <Ppi/ArmMpCoreInfo.h>
|
||||||
|
|
||||||
#include <Chipset/ArmV7.h>
|
|
||||||
|
|
||||||
#include "PrePeiCore.h"
|
#include "PrePeiCore.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|||||||
@@ -12,8 +12,6 @@
|
|||||||
*
|
*
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#include <Chipset/ArmV7.h>
|
|
||||||
|
|
||||||
#include "PrePeiCore.h"
|
#include "PrePeiCore.h"
|
||||||
|
|
||||||
VOID
|
VOID
|
||||||
|
|||||||
@@ -20,7 +20,6 @@
|
|||||||
#include <Library/SerialPortLib.h>
|
#include <Library/SerialPortLib.h>
|
||||||
|
|
||||||
#include <Ppi/ArmGlobalVariable.h>
|
#include <Ppi/ArmGlobalVariable.h>
|
||||||
#include <Chipset/ArmV7.h>
|
|
||||||
|
|
||||||
#include "PrePeiCore.h"
|
#include "PrePeiCore.h"
|
||||||
|
|
||||||
|
|||||||
@@ -15,7 +15,6 @@
|
|||||||
#include "PrePi.h"
|
#include "PrePi.h"
|
||||||
|
|
||||||
#include <Library/ArmGicLib.h>
|
#include <Library/ArmGicLib.h>
|
||||||
#include <Chipset/ArmV7.h>
|
|
||||||
|
|
||||||
VOID
|
VOID
|
||||||
PrimaryMain (
|
PrimaryMain (
|
||||||
|
|||||||
@@ -25,8 +25,6 @@
|
|||||||
#include <Library/SerialPortLib.h>
|
#include <Library/SerialPortLib.h>
|
||||||
#include <Library/ArmPlatformLib.h>
|
#include <Library/ArmPlatformLib.h>
|
||||||
|
|
||||||
#include <Chipset/ArmV7.h>
|
|
||||||
|
|
||||||
#define SerialPrint(txt) SerialPortWrite (txt, AsciiStrLen(txt)+1);
|
#define SerialPrint(txt) SerialPortWrite (txt, AsciiStrLen(txt)+1);
|
||||||
|
|
||||||
// Vector Table for PrePi Phase
|
// Vector Table for PrePi Phase
|
||||||
|
|||||||
Reference in New Issue
Block a user