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MdePkg/Library/Dxe: Fix various typos

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Fix various typos in documentation, comments and strings,
and remove the duplicated 'the'.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Antoine Coeur <coeur@gmx.fr>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Signed-off-by: Philippe Mathieu-Daude <philmd@redhat.com>
Message-Id: <20200207010831.9046-25-philmd@redhat.com>
This commit is contained in:
Antoine Coeur
2020-02-07 02:07:37 +01:00
committed by mergify[bot]
parent b219e2cd4c
commit c1d8b697cf
10 changed files with 21 additions and 21 deletions
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6
MdePkg/Library/DxeRuntimePciExpressLib/PciExpressLib.c
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@@ -298,7 +298,7 @@ PciExpressRegisterForRuntimeAccess (
Address = GetPciExpressAddress (Address & 0x0ffff000);
//
// See if Address has already been registerd for runtime access
// See if Address has already been registered for runtime access
//
for (Index = 0; Index < mDxeRuntimePciExpressLibNumberOfRuntimeRanges; Index++) {
if (mDxeRuntimePciExpressLibRegistrationTable[Index].PhysicalAddress == Address) {
@@ -1456,7 +1456,7 @@ PciExpressBitFieldAndThenOr32 (
Size into the buffer specified by Buffer. This function only allows the PCI
configuration registers from a single PCI function to be read. Size is
returned. When possible 32-bit PCI configuration read cycles are used to read
from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit
and 16-bit PCI configuration read cycles may be used at the beginning and the
end of the range.
@@ -1559,7 +1559,7 @@ PciExpressReadBuffer (
Size from the buffer specified by Buffer. This function only allows the PCI
configuration registers from a single PCI function to be written. Size is
returned. When possible 32-bit PCI configuration write cycles are used to
write from StartAdress to StartAddress + Size. Due to alignment restrictions,
write from StartAddress to StartAddress + Size. Due to alignment restrictions,
8-bit and 16-bit PCI configuration write cycles may be used at the beginning
and the end of the range.