Add TPM2 implementation.
signed off by: jiewen.yao@intel.com reviewed by: guo.dong@intel.com git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14687 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
jyao1
jyao1
583
SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Tis.c
Normal file
583
SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Tis.c
Normal file
@@ -0,0 +1,583 @@
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/** @file
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TIS (TPM Interface Specification) functions used by dTPM2.0 library.
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Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <IndustryStandard/Tpm20.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/IoLib.h>
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#include <Library/TimerLib.h>
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#include <Library/DebugLib.h>
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#include <Library/Tpm2DeviceLib.h>
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#include <Library/PcdLib.h>
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//
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// Set structure alignment to 1-byte
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//
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#pragma pack (1)
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//
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// Register set map as specified in TIS specification Chapter 10
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//
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typedef struct {
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///
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/// Used to gain ownership for this particular port.
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///
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UINT8 Access; // 0
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UINT8 Reserved1[7]; // 1
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///
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/// Controls interrupts.
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///
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UINT32 IntEnable; // 8
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///
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/// SIRQ vector to be used by the TPM.
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///
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UINT8 IntVector; // 0ch
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UINT8 Reserved2[3]; // 0dh
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///
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/// What caused interrupt.
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///
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UINT32 IntSts; // 10h
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///
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/// Shows which interrupts are supported by that particular TPM.
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///
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UINT32 IntfCapability; // 14h
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///
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/// Status Register. Provides status of the TPM.
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///
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UINT8 Status; // 18h
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///
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/// Number of consecutive writes that can be done to the TPM.
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///
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UINT16 BurstCount; // 19h
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///
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/// TPM2 support CANCEL at BIT[24] of STATUS register (WO)
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///
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UINT8 StatusEx; // 1Bh
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UINT8 Reserved3[8];
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///
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/// Read or write FIFO, depending on transaction.
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///
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UINT32 DataFifo; // 24h
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UINT8 Reserved4[0xed8]; // 28h
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///
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/// Vendor ID
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///
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UINT16 Vid; // 0f00h
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///
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/// Device ID
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///
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UINT16 Did; // 0f02h
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///
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/// Revision ID
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///
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UINT8 Rid; // 0f04h
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///
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/// TCG defined configuration registers.
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///
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UINT8 TcgDefined[0x7b]; // 0f05h
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///
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/// Alias to I/O legacy space.
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///
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UINT32 LegacyAddress1; // 0f80h
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///
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/// Additional 8 bits for I/O legacy space extension.
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///
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UINT32 LegacyAddress1Ex; // 0f84h
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///
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/// Alias to second I/O legacy space.
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///
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UINT32 LegacyAddress2; // 0f88h
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///
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/// Additional 8 bits for second I/O legacy space extension.
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///
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UINT32 LegacyAddress2Ex; // 0f8ch
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///
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/// Vendor-defined configuration registers.
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///
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UINT8 VendorDefined[0x70];// 0f90h
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} TIS_PC_REGISTERS;
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//
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// Restore original structure alignment
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//
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#pragma pack ()
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//
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// Define pointer types used to access TIS registers on PC
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//
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typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR;
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//
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// Define bits of ACCESS and STATUS registers
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//
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///
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/// This bit is a 1 to indicate that the other bits in this register are valid.
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///
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#define TIS_PC_VALID BIT7
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///
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/// Indicate that this locality is active.
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///
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#define TIS_PC_ACC_ACTIVE BIT5
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///
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/// Set to 1 to indicate that this locality had the TPM taken away while
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/// this locality had the TIS_PC_ACC_ACTIVE bit set.
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///
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#define TIS_PC_ACC_SEIZED BIT4
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///
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/// Set to 1 to indicate that TPM MUST reset the
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/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the
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/// locality that is writing this bit.
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///
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#define TIS_PC_ACC_SEIZE BIT3
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///
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/// When this bit is 1, another locality is requesting usage of the TPM.
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///
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#define TIS_PC_ACC_PENDIND BIT2
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///
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/// Set to 1 to indicate that this locality is requesting to use TPM.
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///
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#define TIS_PC_ACC_RQUUSE BIT1
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///
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/// A value of 1 indicates that a T/OS has not been established on the platform
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///
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#define TIS_PC_ACC_ESTABLISH BIT0
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///
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/// When this bit is 1, TPM is in the Ready state,
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/// indicating it is ready to receive a new command.
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///
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#define TIS_PC_STS_READY BIT6
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///
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/// Write a 1 to this bit to cause the TPM to execute that command.
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///
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#define TIS_PC_STS_GO BIT5
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///
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/// This bit indicates that the TPM has data available as a response.
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///
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#define TIS_PC_STS_DATA BIT4
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///
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/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.
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///
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#define TIS_PC_STS_EXPECT BIT3
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///
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/// Writes a 1 to this bit to force the TPM to re-send the response.
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///
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#define TIS_PC_STS_RETRY BIT1
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//
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// Default TimeOut value
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//
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#define TIS_TIMEOUT_A (1000 * 1000) // 1s
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#define TIS_TIMEOUT_B (2000 * 1000) // 2s
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#define TIS_TIMEOUT_C (1000 * 1000) // 1s
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#define TIS_TIMEOUT_D (1000 * 1000) // 1s
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#define TIS_TIMEOUT_MAX (90000 * 1000) // 90s
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//
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// Max TPM command/reponse length
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//
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#define TPMCMDBUFLENGTH 0x500
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/**
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Check whether TPM chip exist.
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@param[in] TisReg Pointer to TIS register.
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@retval TRUE TPM chip exists.
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@retval FALSE TPM chip is not found.
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**/
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BOOLEAN
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TisPcPresenceCheck (
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IN TIS_PC_REGISTERS_PTR TisReg
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)
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{
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UINT8 RegRead;
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RegRead = MmioRead8 ((UINTN)&TisReg->Access);
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return (BOOLEAN)(RegRead != (UINT8)-1);
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}
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/**
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Check whether the value of a TPM chip register satisfies the input BIT setting.
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@param[in] Register Address port of register to be checked.
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@param[in] BitSet Check these data bits are set.
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@param[in] BitClear Check these data bits are clear.
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@param[in] TimeOut The max wait time (unit MicroSecond) when checking register.
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@retval EFI_SUCCESS The register satisfies the check bit.
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@retval EFI_TIMEOUT The register can't run into the expected status in time.
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**/
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EFI_STATUS
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EFIAPI
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TisPcWaitRegisterBits (
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IN UINT8 *Register,
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IN UINT8 BitSet,
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IN UINT8 BitClear,
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IN UINT32 TimeOut
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)
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{
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UINT8 RegRead;
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UINT32 WaitTime;
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for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){
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RegRead = MmioRead8 ((UINTN)Register);
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if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0)
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return EFI_SUCCESS;
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MicroSecondDelay (30);
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}
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return EFI_TIMEOUT;
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}
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/**
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Get BurstCount by reading the burstCount field of a TIS regiger
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in the time of default TIS_TIMEOUT_D.
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@param[in] TisReg Pointer to TIS register.
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@param[out] BurstCount Pointer to a buffer to store the got BurstConut.
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@retval EFI_SUCCESS Get BurstCount.
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@retval EFI_INVALID_PARAMETER TisReg is NULL or BurstCount is NULL.
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@retval EFI_TIMEOUT BurstCount can't be got in time.
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**/
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EFI_STATUS
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EFIAPI
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TisPcReadBurstCount (
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IN TIS_PC_REGISTERS_PTR TisReg,
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OUT UINT16 *BurstCount
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)
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{
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UINT32 WaitTime;
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UINT8 DataByte0;
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UINT8 DataByte1;
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if (BurstCount == NULL || TisReg == NULL) {
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return EFI_INVALID_PARAMETER;
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}
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WaitTime = 0;
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do {
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//
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// TIS_PC_REGISTERS_PTR->burstCount is UINT16, but it is not 2bytes aligned,
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// so it needs to use MmioRead8 to read two times
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//
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DataByte0 = MmioRead8 ((UINTN)&TisReg->BurstCount);
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DataByte1 = MmioRead8 ((UINTN)&TisReg->BurstCount + 1);
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*BurstCount = (UINT16)((DataByte1 << 8) + DataByte0);
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if (*BurstCount != 0) {
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return EFI_SUCCESS;
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}
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MicroSecondDelay (30);
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WaitTime += 30;
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} while (WaitTime < TIS_TIMEOUT_D);
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return EFI_TIMEOUT;
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}
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/**
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Set TPM chip to ready state by sending ready command TIS_PC_STS_READY
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to Status Register in time.
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@param[in] TisReg Pointer to TIS register.
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@retval EFI_SUCCESS TPM chip enters into ready state.
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@retval EFI_INVALID_PARAMETER TisReg is NULL.
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@retval EFI_TIMEOUT TPM chip can't be set to ready state in time.
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**/
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EFI_STATUS
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EFIAPI
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TisPcPrepareCommand (
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IN TIS_PC_REGISTERS_PTR TisReg
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)
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{
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EFI_STATUS Status;
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if (TisReg == NULL) {
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return EFI_INVALID_PARAMETER;
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}
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MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);
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Status = TisPcWaitRegisterBits (
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&TisReg->Status,
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TIS_PC_STS_READY,
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0,
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TIS_TIMEOUT_B
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);
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return Status;
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}
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/**
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Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE
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to ACCESS Register in the time of default TIS_TIMEOUT_A.
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@param[in] TisReg Pointer to TIS register.
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@retval EFI_SUCCESS Get the control of TPM chip.
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@retval EFI_INVALID_PARAMETER TisReg is NULL.
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@retval EFI_NOT_FOUND TPM chip doesn't exit.
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@retval EFI_TIMEOUT Can't get the TPM control in time.
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**/
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EFI_STATUS
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EFIAPI
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TisPcRequestUseTpm (
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IN TIS_PC_REGISTERS_PTR TisReg
|
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)
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{
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EFI_STATUS Status;
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if (TisReg == NULL) {
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return EFI_INVALID_PARAMETER;
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}
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if (!TisPcPresenceCheck (TisReg)) {
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return EFI_NOT_FOUND;
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}
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MmioWrite8((UINTN)&TisReg->Access, TIS_PC_ACC_RQUUSE);
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Status = TisPcWaitRegisterBits (
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&TisReg->Access,
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||||
(UINT8)(TIS_PC_ACC_ACTIVE |TIS_PC_VALID),
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0,
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||||
TIS_TIMEOUT_A
|
||||
);
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||||
return Status;
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}
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/**
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Send a command to TPM for execution and return response data.
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|
||||
@param[in] TisReg TPM register space base address.
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@param[in] BufferIn Buffer for command data.
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@param[in] SizeIn Size of command data.
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@param[in, out] BufferOut Buffer for response data.
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||||
@param[in, out] SizeOut Size of response data.
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||||
|
||||
@retval EFI_SUCCESS Operation completed successfully.
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@retval EFI_TIMEOUT The register can't run into the expected status in time.
|
||||
@retval EFI_BUFFER_TOO_SMALL Response data buffer is too small.
|
||||
@retval EFI_DEVICE_ERROR Unexpected device behavior.
|
||||
@retval EFI_UNSUPPORTED Unsupported TPM version
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
TisTpmCommand (
|
||||
IN TIS_PC_REGISTERS_PTR TisReg,
|
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IN UINT8 *BufferIn,
|
||||
IN UINT32 SizeIn,
|
||||
IN OUT UINT8 *BufferOut,
|
||||
IN OUT UINT32 *SizeOut
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
UINT16 BurstCount;
|
||||
UINT32 Index;
|
||||
UINT32 TpmOutSize;
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||||
UINT16 Data16;
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||||
UINT32 Data32;
|
||||
|
||||
DEBUG_CODE (
|
||||
UINTN DebugSize;
|
||||
|
||||
DEBUG ((EFI_D_INFO, "TisTpmCommand Send - "));
|
||||
if (SizeIn > 0x100) {
|
||||
DebugSize = 0x40;
|
||||
} else {
|
||||
DebugSize = SizeIn;
|
||||
}
|
||||
for (Index = 0; Index < DebugSize; Index++) {
|
||||
DEBUG ((EFI_D_INFO, "%02x ", BufferIn[Index]));
|
||||
}
|
||||
if (DebugSize != SizeIn) {
|
||||
DEBUG ((EFI_D_INFO, "...... "));
|
||||
for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {
|
||||
DEBUG ((EFI_D_INFO, "%02x ", BufferIn[Index]));
|
||||
}
|
||||
}
|
||||
DEBUG ((EFI_D_INFO, "\n"));
|
||||
);
|
||||
TpmOutSize = 0;
|
||||
|
||||
Status = TisPcPrepareCommand (TisReg);
|
||||
if (EFI_ERROR (Status)){
|
||||
DEBUG ((DEBUG_ERROR, "Tpm is not ready for command!\n"));
|
||||
return Status;
|
||||
}
|
||||
//
|
||||
// Send the command data to Tpm
|
||||
//
|
||||
Index = 0;
|
||||
while (Index < SizeIn) {
|
||||
Status = TisPcReadBurstCount (TisReg, &BurstCount);
|
||||
if (EFI_ERROR (Status)) {
|
||||
Status = EFI_TIMEOUT;
|
||||
goto Exit;
|
||||
}
|
||||
for (; BurstCount > 0 && Index < SizeIn; BurstCount--) {
|
||||
MmioWrite8((UINTN)&TisReg->DataFifo, *(BufferIn + Index));
|
||||
Index++;
|
||||
}
|
||||
}
|
||||
//
|
||||
// Check the Tpm status STS_EXPECT change from 1 to 0
|
||||
//
|
||||
Status = TisPcWaitRegisterBits (
|
||||
&TisReg->Status,
|
||||
(UINT8) TIS_PC_VALID,
|
||||
TIS_PC_STS_EXPECT,
|
||||
TIS_TIMEOUT_C
|
||||
);
|
||||
if (EFI_ERROR (Status)) {
|
||||
DEBUG ((DEBUG_ERROR, "The send buffer too small!\n"));
|
||||
Status = EFI_BUFFER_TOO_SMALL;
|
||||
goto Exit;
|
||||
}
|
||||
//
|
||||
// Executed the TPM command and waiting for the response data ready
|
||||
//
|
||||
MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_GO);
|
||||
|
||||
//
|
||||
// NOTE: That may take many seconds to minutes for certain commands, such as key generation.
|
||||
//
|
||||
Status = TisPcWaitRegisterBits (
|
||||
&TisReg->Status,
|
||||
(UINT8) (TIS_PC_VALID | TIS_PC_STS_DATA),
|
||||
0,
|
||||
TIS_TIMEOUT_MAX
|
||||
);
|
||||
if (EFI_ERROR (Status)) {
|
||||
DEBUG ((DEBUG_ERROR, "Wait for Tpm response data time out!!\n"));
|
||||
Status = EFI_TIMEOUT;
|
||||
goto Exit;
|
||||
}
|
||||
//
|
||||
// Get response data header
|
||||
//
|
||||
Index = 0;
|
||||
BurstCount = 0;
|
||||
while (Index < sizeof (TPM2_RESPONSE_HEADER)) {
|
||||
Status = TisPcReadBurstCount (TisReg, &BurstCount);
|
||||
if (EFI_ERROR (Status)) {
|
||||
Status = EFI_TIMEOUT;
|
||||
goto Exit;
|
||||
}
|
||||
for (; BurstCount > 0; BurstCount--) {
|
||||
*(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);
|
||||
Index++;
|
||||
if (Index == sizeof (TPM2_RESPONSE_HEADER)) break;
|
||||
}
|
||||
}
|
||||
DEBUG_CODE (
|
||||
DEBUG ((EFI_D_INFO, "TisTpmCommand ReceiveHeader - "));
|
||||
for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {
|
||||
DEBUG ((EFI_D_INFO, "%02x ", BufferOut[Index]));
|
||||
}
|
||||
DEBUG ((EFI_D_INFO, "\n"));
|
||||
);
|
||||
//
|
||||
// Check the reponse data header (tag,parasize and returncode )
|
||||
//
|
||||
CopyMem (&Data16, BufferOut, sizeof (UINT16));
|
||||
// TPM2 should not use this RSP_COMMAND
|
||||
if (SwapBytes16 (Data16) == TPM_ST_RSP_COMMAND) {
|
||||
DEBUG ((EFI_D_ERROR, "TPM_ST_RSP error - %x\n", TPM_ST_RSP_COMMAND));
|
||||
Status = EFI_UNSUPPORTED;
|
||||
goto Exit;
|
||||
}
|
||||
|
||||
CopyMem (&Data32, (BufferOut + 2), sizeof (UINT32));
|
||||
TpmOutSize = SwapBytes32 (Data32);
|
||||
if (*SizeOut < TpmOutSize) {
|
||||
Status = EFI_BUFFER_TOO_SMALL;
|
||||
goto Exit;
|
||||
}
|
||||
*SizeOut = TpmOutSize;
|
||||
//
|
||||
// Continue reading the remaining data
|
||||
//
|
||||
while ( Index < TpmOutSize ) {
|
||||
for (; BurstCount > 0; BurstCount--) {
|
||||
*(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);
|
||||
Index++;
|
||||
if (Index == TpmOutSize) {
|
||||
Status = EFI_SUCCESS;
|
||||
goto Exit;
|
||||
}
|
||||
}
|
||||
Status = TisPcReadBurstCount (TisReg, &BurstCount);
|
||||
if (EFI_ERROR (Status)) {
|
||||
Status = EFI_TIMEOUT;
|
||||
goto Exit;
|
||||
}
|
||||
}
|
||||
Exit:
|
||||
DEBUG_CODE (
|
||||
DEBUG ((EFI_D_INFO, "TisTpmCommand Receive - "));
|
||||
for (Index = 0; Index < TpmOutSize; Index++) {
|
||||
DEBUG ((EFI_D_INFO, "%02x ", BufferOut[Index]));
|
||||
}
|
||||
DEBUG ((EFI_D_INFO, "\n"));
|
||||
);
|
||||
MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);
|
||||
return Status;
|
||||
}
|
||||
|
||||
/**
|
||||
This service enables the sending of commands to the TPM2.
|
||||
|
||||
@param[in] InputParameterBlockSize Size of the TPM2 input parameter block.
|
||||
@param[in] InputParameterBlock Pointer to the TPM2 input parameter block.
|
||||
@param[in,out] OutputParameterBlockSize Size of the TPM2 output parameter block.
|
||||
@param[in] OutputParameterBlock Pointer to the TPM2 output parameter block.
|
||||
|
||||
@retval EFI_SUCCESS The command byte stream was successfully sent to the device and a response was successfully received.
|
||||
@retval EFI_DEVICE_ERROR The command was not successfully sent to the device or a response was not successfully received from the device.
|
||||
@retval EFI_BUFFER_TOO_SMALL The output parameter block is too small.
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
DTpm2SubmitCommand (
|
||||
IN UINT32 InputParameterBlockSize,
|
||||
IN UINT8 *InputParameterBlock,
|
||||
IN OUT UINT32 *OutputParameterBlockSize,
|
||||
IN UINT8 *OutputParameterBlock
|
||||
)
|
||||
{
|
||||
return TisTpmCommand (
|
||||
(TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),
|
||||
InputParameterBlock,
|
||||
InputParameterBlockSize,
|
||||
OutputParameterBlock,
|
||||
OutputParameterBlockSize
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
This service requests use TPM2.
|
||||
|
||||
@retval EFI_SUCCESS Get the control of TPM2 chip.
|
||||
@retval EFI_NOT_FOUND TPM2 not found.
|
||||
@retval EFI_DEVICE_ERROR Unexpected device behavior.
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
DTpm2RequestUseTpm (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));
|
||||
}
|
||||
Reference in New Issue
Block a user