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SourceLevelDebugPkg: Apply uncrustify changes

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the SourceLevelDebugPkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
This commit is contained in:
Michael Kubacki
2021-12-05 14:54:15 -08:00
committed by mergify[bot]
parent b878648967
commit c1e126b119
35 changed files with 3547 additions and 3381 deletions
Download Patch File Download Diff File Expand all files Collapse all files

359
SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/DebugCommunicationLibUsb3Common.c
View File

@@ -8,27 +8,27 @@
#include "DebugCommunicationLibUsb3Internal.h"
UINT16 mString0Desc[] = {
UINT16 mString0Desc[] = {
// String Descriptor Type + Length
( USB_DESC_TYPE_STRING << 8 ) + STRING0_DESC_LEN,
(USB_DESC_TYPE_STRING << 8) + STRING0_DESC_LEN,
0x0409
};
UINT16 mManufacturerStrDesc[] = {
UINT16 mManufacturerStrDesc[] = {
// String Descriptor Type + Length
( USB_DESC_TYPE_STRING << 8 ) + MANU_DESC_LEN,
'I', 'n', 't', 'e', 'l'
(USB_DESC_TYPE_STRING << 8) + MANU_DESC_LEN,
'I', 'n','t', 'e', 'l'
};
UINT16 mProductStrDesc[] = {
UINT16 mProductStrDesc[] = {
// String Descriptor Type + Length
( USB_DESC_TYPE_STRING << 8 ) + PRODUCT_DESC_LEN,
'U', 'S', 'B', ' ', '3', '.', '0', ' ', 'D', 'e', 'b', 'u', 'g', ' ', 'C', 'a', 'b', 'l', 'e'
(USB_DESC_TYPE_STRING << 8) + PRODUCT_DESC_LEN,
'U', 'S','B', ' ', '3', '.', '0', ' ', 'D', 'e', 'b', 'u', 'g', ' ', 'C', 'a', 'b', 'l', 'e'
};
UINT16 mSerialNumberStrDesc[] = {
UINT16 mSerialNumberStrDesc[] = {
// String Descriptor Type + Length
( USB_DESC_TYPE_STRING << 8 ) + SERIAL_DESC_LEN,
(USB_DESC_TYPE_STRING << 8) + SERIAL_DESC_LEN,
'1'
};
@@ -39,14 +39,14 @@ UINT16 mSerialNumberStrDesc[] = {
@param[in] BitMask 32-bit mask
**/
VOID
XhcSetR32Bit(
IN OUT UINTN Register,
IN UINT32 BitMask
XhcSetR32Bit (
IN OUT UINTN Register,
IN UINT32 BitMask
)
{
UINT32 RegisterValue;
UINT32 RegisterValue;
RegisterValue = MmioRead32 (Register);
RegisterValue = MmioRead32 (Register);
RegisterValue |= (UINT32)(BitMask);
MmioWrite32 (Register, RegisterValue);
}
@@ -58,14 +58,14 @@ XhcSetR32Bit(
@param[in] BitMask 32-bit mask
**/
VOID
XhcClearR32Bit(
IN OUT UINTN Register,
IN UINT32 BitMask
XhcClearR32Bit (
IN OUT UINTN Register,
IN UINT32 BitMask
)
{
UINT32 RegisterValue;
UINT32 RegisterValue;
RegisterValue = MmioRead32 (Register);
RegisterValue = MmioRead32 (Register);
RegisterValue &= ~BitMask;
MmioWrite32 (Register, RegisterValue);
}
@@ -104,15 +104,15 @@ XhcWriteDebugReg (
**/
UINT32
XhcReadDebugReg (
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN UINT32 Offset
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN UINT32 Offset
)
{
UINT32 Data;
EFI_PHYSICAL_ADDRESS DebugCapabilityBase;
UINT32 Data;
EFI_PHYSICAL_ADDRESS DebugCapabilityBase;
DebugCapabilityBase = Handle->DebugCapabilityBase;
Data = MmioRead32 ((UINTN)(DebugCapabilityBase + Offset));
Data = MmioRead32 ((UINTN)(DebugCapabilityBase + Offset));
return Data;
}
@@ -127,12 +127,12 @@ XhcReadDebugReg (
**/
VOID
XhcSetDebugRegBit (
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN UINT32 Offset,
IN UINT32 Bit
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN UINT32 Offset,
IN UINT32 Bit
)
{
UINT32 Data;
UINT32 Data;
Data = XhcReadDebugReg (Handle, Offset);
Data |= Bit;
@@ -149,15 +149,15 @@ XhcSetDebugRegBit (
**/
VOID
XhcClearDebugRegBit (
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN UINT32 Offset,
IN UINT32 Bit
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN UINT32 Offset,
IN UINT32 Bit
)
{
UINT32 Data;
UINT32 Data;
Data = XhcReadDebugReg (Handle, Offset);
Data &= ~Bit;
Data &= ~Bit;
XhcWriteDebugReg (Handle, Offset, Data);
}
@@ -172,26 +172,26 @@ ProgramXhciBaseAddress (
VOID
)
{
UINT16 PciCmd;
UINT32 Low;
UINT32 High;
EFI_PHYSICAL_ADDRESS XhciMmioBase;
UINT16 PciCmd;
UINT32 Low;
UINT32 High;
EFI_PHYSICAL_ADDRESS XhciMmioBase;
Low = PciRead32 (PcdGet32(PcdUsbXhciPciAddress) + PCI_BASE_ADDRESSREG_OFFSET);
High = PciRead32 (PcdGet32(PcdUsbXhciPciAddress) + PCI_BASE_ADDRESSREG_OFFSET + 4);
XhciMmioBase = (EFI_PHYSICAL_ADDRESS) (LShiftU64 ((UINT64) High, 32) | Low);
Low = PciRead32 (PcdGet32 (PcdUsbXhciPciAddress) + PCI_BASE_ADDRESSREG_OFFSET);
High = PciRead32 (PcdGet32 (PcdUsbXhciPciAddress) + PCI_BASE_ADDRESSREG_OFFSET + 4);
XhciMmioBase = (EFI_PHYSICAL_ADDRESS)(LShiftU64 ((UINT64)High, 32) | Low);
XhciMmioBase &= XHCI_BASE_ADDRESS_64_BIT_MASK;
if ((XhciMmioBase == 0) || (XhciMmioBase == XHCI_BASE_ADDRESS_64_BIT_MASK)) {
XhciMmioBase = PcdGet64(PcdUsbXhciMemorySpaceBase);
PciWrite32(PcdGet32(PcdUsbXhciPciAddress) + PCI_BASE_ADDRESSREG_OFFSET, XhciMmioBase & 0xFFFFFFFF);
PciWrite32(PcdGet32(PcdUsbXhciPciAddress) + PCI_BASE_ADDRESSREG_OFFSET + 4, (RShiftU64 (XhciMmioBase, 32) & 0xFFFFFFFF));
XhciMmioBase = PcdGet64 (PcdUsbXhciMemorySpaceBase);
PciWrite32 (PcdGet32 (PcdUsbXhciPciAddress) + PCI_BASE_ADDRESSREG_OFFSET, XhciMmioBase & 0xFFFFFFFF);
PciWrite32 (PcdGet32 (PcdUsbXhciPciAddress) + PCI_BASE_ADDRESSREG_OFFSET + 4, (RShiftU64 (XhciMmioBase, 32) & 0xFFFFFFFF));
}
PciCmd = PciRead16 (PcdGet32(PcdUsbXhciPciAddress) + PCI_COMMAND_OFFSET);
PciCmd = PciRead16 (PcdGet32 (PcdUsbXhciPciAddress) + PCI_COMMAND_OFFSET);
if (((PciCmd & EFI_PCI_COMMAND_MEMORY_SPACE) == 0) || ((PciCmd & EFI_PCI_COMMAND_BUS_MASTER) == 0)) {
PciCmd |= EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND_BUS_MASTER;
PciWrite16(PcdGet32(PcdUsbXhciPciAddress) + PCI_COMMAND_OFFSET, PciCmd);
PciWrite16 (PcdGet32 (PcdUsbXhciPciAddress) + PCI_COMMAND_OFFSET, PciCmd);
}
return XhciMmioBase;
@@ -206,8 +206,8 @@ ProgramXhciBaseAddress (
**/
VOID
UpdateXhcResource (
IN OUT USB3_DEBUG_PORT_HANDLE *Handle,
IN EFI_PHYSICAL_ADDRESS XhciMmioBase
IN OUT USB3_DEBUG_PORT_HANDLE *Handle,
IN EFI_PHYSICAL_ADDRESS XhciMmioBase
)
{
if (Handle == NULL) {
@@ -234,18 +234,18 @@ UpdateXhcResource (
RETURN_STATUS
EFIAPI
CalculateUsbDebugPortMmioBase (
USB3_DEBUG_PORT_HANDLE *Handle
)
USB3_DEBUG_PORT_HANDLE *Handle
)
{
UINT16 VendorId;
UINT16 DeviceId;
UINT8 ProgInterface;
UINT8 SubClassCode;
UINT8 BaseCode;
BOOLEAN Flag;
UINT32 Capability;
EFI_PHYSICAL_ADDRESS CapabilityPointer;
UINT8 CapLength;
UINT16 VendorId;
UINT16 DeviceId;
UINT8 ProgInterface;
UINT8 SubClassCode;
UINT8 BaseCode;
BOOLEAN Flag;
UINT32 Capability;
EFI_PHYSICAL_ADDRESS CapabilityPointer;
UINT8 CapLength;
if (Handle->Initialized != USB3DBG_UNINITIALIZED) {
if (Handle->Initialized == USB3DBG_NO_DBG_CAB) {
@@ -255,22 +255,22 @@ CalculateUsbDebugPortMmioBase (
}
}
VendorId = PciRead16 (PcdGet32(PcdUsbXhciPciAddress) + PCI_VENDOR_ID_OFFSET);
DeviceId = PciRead16 (PcdGet32(PcdUsbXhciPciAddress) + PCI_DEVICE_ID_OFFSET);
VendorId = PciRead16 (PcdGet32 (PcdUsbXhciPciAddress) + PCI_VENDOR_ID_OFFSET);
DeviceId = PciRead16 (PcdGet32 (PcdUsbXhciPciAddress) + PCI_DEVICE_ID_OFFSET);
if ((VendorId == 0xFFFF) || (DeviceId == 0xFFFF)) {
goto Done;
}
ProgInterface = PciRead8 (PcdGet32(PcdUsbXhciPciAddress) + PCI_CLASSCODE_OFFSET);
SubClassCode = PciRead8 (PcdGet32(PcdUsbXhciPciAddress) + PCI_CLASSCODE_OFFSET + 1);
BaseCode = PciRead8 (PcdGet32(PcdUsbXhciPciAddress) + PCI_CLASSCODE_OFFSET + 2);
ProgInterface = PciRead8 (PcdGet32 (PcdUsbXhciPciAddress) + PCI_CLASSCODE_OFFSET);
SubClassCode = PciRead8 (PcdGet32 (PcdUsbXhciPciAddress) + PCI_CLASSCODE_OFFSET + 1);
BaseCode = PciRead8 (PcdGet32 (PcdUsbXhciPciAddress) + PCI_CLASSCODE_OFFSET + 2);
if ((ProgInterface != PCI_IF_XHCI) || (SubClassCode != PCI_CLASS_SERIAL_USB) || (BaseCode != PCI_CLASS_SERIAL)) {
goto Done;
}
CapLength = MmioRead8 ((UINTN) Handle->XhciMmioBase);
CapLength = MmioRead8 ((UINTN)Handle->XhciMmioBase);
//
// Get capability pointer from HCCPARAMS at offset 0x10
@@ -280,21 +280,23 @@ CalculateUsbDebugPortMmioBase (
//
// Search XHCI debug capability
//
Flag = FALSE;
Flag = FALSE;
Capability = MmioRead32 ((UINTN)CapabilityPointer);
while (TRUE) {
if ((Capability & XHC_CAPABILITY_ID_MASK) == PCI_CAPABILITY_ID_DEBUG_PORT) {
Flag = TRUE;
break;
}
if ((((Capability & XHC_NEXT_CAPABILITY_MASK) >> 8) & XHC_CAPABILITY_ID_MASK) == 0) {
//
// Reach the end of capability list, quit
//
break;
}
CapabilityPointer += ((Capability & XHC_NEXT_CAPABILITY_MASK) >> 8) * 4;
Capability = MmioRead32 ((UINTN)CapabilityPointer);
Capability = MmioRead32 ((UINTN)CapabilityPointer);
}
if (!Flag) {
@@ -307,8 +309,8 @@ CalculateUsbDebugPortMmioBase (
Handle->DebugCapabilityBase = CapabilityPointer;
Handle->DebugCapabilityOffset = CapabilityPointer - Handle->XhciMmioBase;
Handle->XhciOpRegister = Handle->XhciMmioBase + CapLength;
Handle->DebugSupport = TRUE;
Handle->Initialized = USB3DBG_DBG_CAB;
Handle->DebugSupport = TRUE;
Handle->Initialized = USB3DBG_DBG_CAB;
return RETURN_SUCCESS;
Done:
@@ -331,12 +333,12 @@ Done:
**/
BOOLEAN
EFIAPI
NeedReinitializeHardware(
IN USB3_DEBUG_PORT_HANDLE *Handle
NeedReinitializeHardware (
IN USB3_DEBUG_PORT_HANDLE *Handle
)
{
BOOLEAN Result;
volatile UINT32 Dcctrl;
BOOLEAN Result;
volatile UINT32 Dcctrl;
Result = FALSE;
@@ -347,7 +349,7 @@ NeedReinitializeHardware(
if ((Dcctrl & BIT0) == 0) {
Result = TRUE;
} else if (!Handle->Ready) {
Handle->Ready = TRUE;
Handle->Ready = TRUE;
Handle->Initialized = USB3DBG_ENABLED;
}
@@ -363,8 +365,8 @@ NeedReinitializeHardware(
**/
EFI_STATUS
CreateEventRing (
IN USB3_DEBUG_PORT_HANDLE *Handle,
OUT EVENT_RING *EventRing
IN USB3_DEBUG_PORT_HANDLE *Handle,
OUT EVENT_RING *EventRing
)
{
VOID *Buf;
@@ -377,13 +379,13 @@ CreateEventRing (
//
Buf = AllocateAlignBuffer (sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER);
ASSERT (Buf != NULL);
ASSERT (((UINTN) Buf & 0x3F) == 0);
ASSERT (((UINTN)Buf & 0x3F) == 0);
ZeroMem (Buf, sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER);
EventRing->EventRingSeg0 = (EFI_PHYSICAL_ADDRESS)(UINTN) Buf;
EventRing->EventRingSeg0 = (EFI_PHYSICAL_ADDRESS)(UINTN)Buf;
EventRing->TrbNumber = EVENT_RING_TRB_NUMBER;
EventRing->EventRingDequeue = (EFI_PHYSICAL_ADDRESS)(UINTN) EventRing->EventRingSeg0;
EventRing->EventRingEnqueue = (EFI_PHYSICAL_ADDRESS)(UINTN) EventRing->EventRingSeg0;
EventRing->EventRingDequeue = (EFI_PHYSICAL_ADDRESS)(UINTN)EventRing->EventRingSeg0;
EventRing->EventRingEnqueue = (EFI_PHYSICAL_ADDRESS)(UINTN)EventRing->EventRingSeg0;
//
// Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1'
@@ -396,11 +398,11 @@ CreateEventRing (
//
Buf = AllocateAlignBuffer (sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER);
ASSERT (Buf != NULL);
ASSERT (((UINTN) Buf & 0x3F) == 0);
ASSERT (((UINTN)Buf & 0x3F) == 0);
ZeroMem (Buf, sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER);
ERSTBase = (EVENT_RING_SEG_TABLE_ENTRY *) Buf;
EventRing->ERSTBase = (EFI_PHYSICAL_ADDRESS)(UINTN) ERSTBase;
ERSTBase = (EVENT_RING_SEG_TABLE_ENTRY *)Buf;
EventRing->ERSTBase = (EFI_PHYSICAL_ADDRESS)(UINTN)ERSTBase;
//
// Fill Event Segment address
@@ -415,13 +417,13 @@ CreateEventRing (
XhcWriteDebugReg (
Handle,
XHC_DC_DCERDP,
XHC_LOW_32BIT((UINT64)(UINTN)EventRing->EventRingDequeue)
XHC_LOW_32BIT ((UINT64)(UINTN)EventRing->EventRingDequeue)
);
XhcWriteDebugReg (
Handle,
XHC_DC_DCERDP + 4,
XHC_HIGH_32BIT((UINT64)(UINTN)EventRing->EventRingDequeue)
XHC_HIGH_32BIT ((UINT64)(UINTN)EventRing->EventRingDequeue)
);
//
@@ -430,13 +432,13 @@ CreateEventRing (
XhcWriteDebugReg (
Handle,
XHC_DC_DCERSTBA,
XHC_LOW_32BIT((UINT64)(UINTN)ERSTBase)
XHC_LOW_32BIT ((UINT64)(UINTN)ERSTBase)
);
XhcWriteDebugReg (
Handle,
XHC_DC_DCERSTBA + 4,
XHC_HIGH_32BIT((UINT64)(UINTN)ERSTBase)
XHC_HIGH_32BIT ((UINT64)(UINTN)ERSTBase)
);
//
@@ -460,37 +462,37 @@ CreateEventRing (
**/
VOID
CreateTransferRing (
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN UINT32 TrbNum,
OUT TRANSFER_RING *TransferRing
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN UINT32 TrbNum,
OUT TRANSFER_RING *TransferRing
)
{
VOID *Buf;
LINK_TRB *EndTrb;
VOID *Buf;
LINK_TRB *EndTrb;
Buf = AllocateAlignBuffer (sizeof (TRB_TEMPLATE) * TrbNum);
ASSERT (Buf != NULL);
ASSERT (((UINTN) Buf & 0xF) == 0);
ASSERT (((UINTN)Buf & 0xF) == 0);
ZeroMem (Buf, sizeof (TRB_TEMPLATE) * TrbNum);
TransferRing->RingSeg0 = (EFI_PHYSICAL_ADDRESS)(UINTN) Buf;
TransferRing->TrbNumber = TrbNum;
TransferRing->RingEnqueue = TransferRing->RingSeg0;
TransferRing->RingDequeue = TransferRing->RingSeg0;
TransferRing->RingPCS = 1;
TransferRing->RingSeg0 = (EFI_PHYSICAL_ADDRESS)(UINTN)Buf;
TransferRing->TrbNumber = TrbNum;
TransferRing->RingEnqueue = TransferRing->RingSeg0;
TransferRing->RingDequeue = TransferRing->RingSeg0;
TransferRing->RingPCS = 1;
//
// 4.9.2 Transfer Ring Management
// To form a ring (or circular queue) a Link TRB may be inserted at the end of a ring to
// point to the first TRB in the ring.
//
EndTrb = (LINK_TRB *) ((UINTN)Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1));
EndTrb = (LINK_TRB *)((UINTN)Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1));
EndTrb->Type = TRB_TYPE_LINK;
EndTrb->PtrLo = XHC_LOW_32BIT (Buf);
EndTrb->PtrHi = XHC_HIGH_32BIT (Buf);
//
// Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.
//
EndTrb->TC = 1;
EndTrb->TC = 1;
//
// Set Cycle bit as other TRB PCS init value
//
@@ -508,26 +510,26 @@ CreateTransferRing (
**/
EFI_STATUS
CreateDebugCapabilityContext (
IN USB3_DEBUG_PORT_HANDLE *Handle
IN USB3_DEBUG_PORT_HANDLE *Handle
)
{
VOID *Buf;
XHC_DC_CONTEXT *DebugCapabilityContext;
UINT8 *String0Desc;
UINT8 *ManufacturerStrDesc;
UINT8 *ProductStrDesc;
UINT8 *SerialNumberStrDesc;
VOID *Buf;
XHC_DC_CONTEXT *DebugCapabilityContext;
UINT8 *String0Desc;
UINT8 *ManufacturerStrDesc;
UINT8 *ProductStrDesc;
UINT8 *SerialNumberStrDesc;
//
// Allocate debug device context
//
Buf = AllocateAlignBuffer (sizeof (XHC_DC_CONTEXT));
ASSERT (Buf != NULL);
ASSERT (((UINTN) Buf & 0xF) == 0);
ASSERT (((UINTN)Buf & 0xF) == 0);
ZeroMem (Buf, sizeof (XHC_DC_CONTEXT));
DebugCapabilityContext = (XHC_DC_CONTEXT *)(UINTN) Buf;
Handle->DebugCapabilityContext = (EFI_PHYSICAL_ADDRESS)(UINTN) DebugCapabilityContext;
DebugCapabilityContext = (XHC_DC_CONTEXT *)(UINTN)Buf;
Handle->DebugCapabilityContext = (EFI_PHYSICAL_ADDRESS)(UINTN)DebugCapabilityContext;
//
// Initialize DbcInfoContext.
@@ -556,7 +558,7 @@ CreateDebugCapabilityContext (
//
// Update string descriptor address
//
String0Desc = (UINT8 *) AllocateAlignBuffer (STRING0_DESC_LEN + MANU_DESC_LEN + PRODUCT_DESC_LEN + SERIAL_DESC_LEN);
String0Desc = (UINT8 *)AllocateAlignBuffer (STRING0_DESC_LEN + MANU_DESC_LEN + PRODUCT_DESC_LEN + SERIAL_DESC_LEN);
ASSERT (String0Desc != NULL);
ZeroMem (String0Desc, STRING0_DESC_LEN + MANU_DESC_LEN + PRODUCT_DESC_LEN + SERIAL_DESC_LEN);
CopyMem (String0Desc, mString0Desc, STRING0_DESC_LEN);
@@ -596,12 +598,12 @@ CreateDebugCapabilityContext (
XhcWriteDebugReg (
Handle,
XHC_DC_DCCP,
XHC_LOW_32BIT((UINT64)(UINTN)DebugCapabilityContext)
XHC_LOW_32BIT ((UINT64)(UINTN)DebugCapabilityContext)
);
XhcWriteDebugReg (
Handle,
XHC_DC_DCCP + 4,
XHC_HIGH_32BIT((UINT64)(UINTN)DebugCapabilityContext)
XHC_HIGH_32BIT ((UINT64)(UINTN)DebugCapabilityContext)
);
return EFI_SUCCESS;
}
@@ -614,11 +616,11 @@ CreateDebugCapabilityContext (
**/
VOID
XhcDetectDebugCapabilityReady (
IN USB3_DEBUG_PORT_HANDLE *Handle
IN USB3_DEBUG_PORT_HANDLE *Handle
)
{
UINT64 TimeOut;
volatile UINT32 Dcctrl;
UINT64 TimeOut;
volatile UINT32 Dcctrl;
TimeOut = 1;
if (Handle->Initialized == USB3DBG_DBG_CAB) {
@@ -642,6 +644,7 @@ XhcDetectDebugCapabilityReady (
Handle->Ready = TRUE;
break;
}
MicroSecondDelay (XHC_POLL_DELAY);
TimeOut--;
} while (TimeOut != 0);
@@ -659,27 +662,28 @@ XhcDetectDebugCapabilityReady (
RETURN_STATUS
EFIAPI
InitializeUsbDebugHardware (
IN USB3_DEBUG_PORT_HANDLE *Handle
IN USB3_DEBUG_PORT_HANDLE *Handle
)
{
RETURN_STATUS Status;
UINT8 *Buffer;
UINTN Index;
UINT8 TotalUsb3Port;
EFI_PHYSICAL_ADDRESS XhciOpRegister;
UINT32 Dcddi1;
RETURN_STATUS Status;
UINT8 *Buffer;
UINTN Index;
UINT8 TotalUsb3Port;
EFI_PHYSICAL_ADDRESS XhciOpRegister;
UINT32 Dcddi1;
XhciOpRegister = Handle->XhciOpRegister;
TotalUsb3Port = MmioRead32 (((UINTN) Handle->XhciMmioBase + XHC_HCSPARAMS1_OFFSET)) >> 24;
TotalUsb3Port = MmioRead32 (((UINTN)Handle->XhciMmioBase + XHC_HCSPARAMS1_OFFSET)) >> 24;
if (Handle->Initialized == USB3DBG_NOT_ENABLED) {
Dcddi1 = XhcReadDebugReg (Handle,XHC_DC_DCDDI1);
Dcddi1 = XhcReadDebugReg (Handle, XHC_DC_DCDDI1);
if (Dcddi1 != (UINT32)((XHCI_DEBUG_DEVICE_VENDOR_ID << 16) | XHCI_DEBUG_DEVICE_PROTOCOL)) {
//
// The debug capability has been reset by other code, return device error.
//
return EFI_DEVICE_ERROR;
}
//
// If XHCI supports debug capability, hardware resource has been allocated,
// but it has not been enabled, try to enable again.
@@ -718,8 +722,8 @@ InitializeUsbDebugHardware (
//
// Construct the buffer for read, poll and write.
//
Handle->UrbIn.Data = (EFI_PHYSICAL_ADDRESS)(UINTN) Buffer;
Handle->Data = (EFI_PHYSICAL_ADDRESS)(UINTN) Buffer + XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE;
Handle->UrbIn.Data = (EFI_PHYSICAL_ADDRESS)(UINTN)Buffer;
Handle->Data = (EFI_PHYSICAL_ADDRESS)(UINTN)Buffer + XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE;
Handle->UrbOut.Data = Handle->UrbIn.Data + XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE * 2;
//
@@ -739,16 +743,16 @@ InitializeUsbDebugHardware (
// Init DCDDI1 and DCDDI2
//
XhcWriteDebugReg (
Handle,
XHC_DC_DCDDI1,
(UINT32)((XHCI_DEBUG_DEVICE_VENDOR_ID << 16) | XHCI_DEBUG_DEVICE_PROTOCOL)
);
Handle,
XHC_DC_DCDDI1,
(UINT32)((XHCI_DEBUG_DEVICE_VENDOR_ID << 16) | XHCI_DEBUG_DEVICE_PROTOCOL)
);
XhcWriteDebugReg (
Handle,
XHC_DC_DCDDI2,
(UINT32)((XHCI_DEBUG_DEVICE_REVISION << 16) | XHCI_DEBUG_DEVICE_PRODUCT_ID)
);
Handle,
XHC_DC_DCDDI2,
(UINT32)((XHCI_DEBUG_DEVICE_REVISION << 16) | XHCI_DEBUG_DEVICE_PRODUCT_ID)
);
Enable:
if ((Handle->Initialized == USB3DBG_NOT_ENABLED) && (!Handle->ChangePortPower)) {
@@ -775,7 +779,7 @@ Enable:
Status = RETURN_SUCCESS;
if (!Handle->Ready) {
Handle->Initialized = USB3DBG_NOT_ENABLED;
Status = RETURN_NOT_READY;
Status = RETURN_NOT_READY;
} else {
Handle->Initialized = USB3DBG_ENABLED;
}
@@ -791,16 +795,16 @@ Enable:
**/
VOID
DiscoverInitializeUsbDebugPort (
IN USB3_DEBUG_PORT_HANDLE *Handle
IN USB3_DEBUG_PORT_HANDLE *Handle
)
{
EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS XhciMmioBase;
EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS XhciMmioBase;
//
// Read 64-bit MMIO base address
//
XhciMmioBase = ProgramXhciBaseAddress ();
XhciMmioBase = ProgramXhciBaseAddress ();
Handle->XhciMmioBase = XhciMmioBase;
Status = CalculateUsbDebugPortMmioBase (Handle);
@@ -820,14 +824,14 @@ DiscoverInitializeUsbDebugPort (
**/
VOID
SetUsb3DebugPortInstance (
IN USB3_DEBUG_PORT_HANDLE *Instance
IN USB3_DEBUG_PORT_HANDLE *Instance
)
{
EFI_PHYSICAL_ADDRESS *AddrPtr;
EFI_PHYSICAL_ADDRESS *AddrPtr;
AddrPtr = GetUsb3DebugPortInstanceAddrPtr ();
ASSERT (AddrPtr != NULL);
*AddrPtr = (EFI_PHYSICAL_ADDRESS) (UINTN) Instance;
*AddrPtr = (EFI_PHYSICAL_ADDRESS)(UINTN)Instance;
}
/**
@@ -839,13 +843,13 @@ GetUsb3DebugPortInstance (
VOID
)
{
EFI_PHYSICAL_ADDRESS *AddrPtr;
USB3_DEBUG_PORT_HANDLE *Instance;
EFI_PHYSICAL_ADDRESS *AddrPtr;
USB3_DEBUG_PORT_HANDLE *Instance;
AddrPtr = GetUsb3DebugPortInstanceAddrPtr ();
ASSERT (AddrPtr != NULL);
Instance = (USB3_DEBUG_PORT_HANDLE *) (UINTN) *AddrPtr;
Instance = (USB3_DEBUG_PORT_HANDLE *)(UINTN)*AddrPtr;
return Instance;
}
@@ -870,17 +874,17 @@ GetUsb3DebugPortInstance (
UINTN
EFIAPI
DebugPortReadBuffer (
IN DEBUG_PORT_HANDLE Handle,
IN UINT8 *Buffer,
IN UINTN NumberOfBytes,
IN UINTN Timeout
IN DEBUG_PORT_HANDLE Handle,
IN UINT8 *Buffer,
IN UINTN NumberOfBytes,
IN UINTN Timeout
)
{
USB3_DEBUG_PORT_HANDLE *UsbDebugPortHandle;
UINT8 Index;
UINT8 *Data;
USB3_DEBUG_PORT_HANDLE *UsbDebugPortHandle;
UINT8 Index;
UINT8 *Data;
if (NumberOfBytes != 1 || Buffer == NULL || Timeout != 0) {
if ((NumberOfBytes != 1) || (Buffer == NULL) || (Timeout != 0)) {
return 0;
}
@@ -889,11 +893,12 @@ DebugPortReadBuffer (
// If Handle is not NULL, use it and set the instance.
//
if (Handle != NULL) {
UsbDebugPortHandle = (USB3_DEBUG_PORT_HANDLE *) Handle;
UsbDebugPortHandle = (USB3_DEBUG_PORT_HANDLE *)Handle;
SetUsb3DebugPortInstance (UsbDebugPortHandle);
} else {
UsbDebugPortHandle = GetUsb3DebugPortInstance ();
}
if (UsbDebugPortHandle == NULL) {
return 0;
}
@@ -922,8 +927,10 @@ DebugPortReadBuffer (
if ((Index + 1) >= XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE) {
return 0;
}
Data[Index] = Data[Index + 1];
}
UsbDebugPortHandle->DataCount = (UINT8)(UsbDebugPortHandle->DataCount - 1);
return 1;
}
@@ -949,16 +956,16 @@ DebugPortReadBuffer (
UINTN
EFIAPI
DebugPortWriteBuffer (
IN DEBUG_PORT_HANDLE Handle,
IN UINT8 *Buffer,
IN UINTN NumberOfBytes
IN DEBUG_PORT_HANDLE Handle,
IN UINT8 *Buffer,
IN UINTN NumberOfBytes
)
{
USB3_DEBUG_PORT_HANDLE *UsbDebugPortHandle;
UINTN Sent;
UINTN Total;
USB3_DEBUG_PORT_HANDLE *UsbDebugPortHandle;
UINTN Sent;
UINTN Total;
if (NumberOfBytes == 0 || Buffer == NULL) {
if ((NumberOfBytes == 0) || (Buffer == NULL)) {
return 0;
}
@@ -970,11 +977,12 @@ DebugPortWriteBuffer (
// If Handle is not NULL, use it and set the instance.
//
if (Handle != NULL) {
UsbDebugPortHandle = (USB3_DEBUG_PORT_HANDLE *) Handle;
UsbDebugPortHandle = (USB3_DEBUG_PORT_HANDLE *)Handle;
SetUsb3DebugPortInstance (UsbDebugPortHandle);
} else {
UsbDebugPortHandle = GetUsb3DebugPortInstance ();
}
if (UsbDebugPortHandle == NULL) {
return 0;
}
@@ -1001,6 +1009,7 @@ DebugPortWriteBuffer (
} else {
Sent = (UINT8)(NumberOfBytes - Total);
}
XhcDataTransfer (UsbDebugPortHandle, EfiUsbDataOut, Buffer + Total, &Sent, DATA_TRANSFER_WRITE_TIMEOUT);
Total += Sent;
}
@@ -1024,22 +1033,23 @@ DebugPortWriteBuffer (
BOOLEAN
EFIAPI
DebugPortPollBuffer (
IN DEBUG_PORT_HANDLE Handle
IN DEBUG_PORT_HANDLE Handle
)
{
USB3_DEBUG_PORT_HANDLE *UsbDebugPortHandle;
UINTN Length;
USB3_DEBUG_PORT_HANDLE *UsbDebugPortHandle;
UINTN Length;
//
// If Handle is NULL, get own instance.
// If Handle is not NULL, use it and set the instance.
//
if (Handle != NULL) {
UsbDebugPortHandle = (USB3_DEBUG_PORT_HANDLE *) Handle;
UsbDebugPortHandle = (USB3_DEBUG_PORT_HANDLE *)Handle;
SetUsb3DebugPortInstance (UsbDebugPortHandle);
} else {
UsbDebugPortHandle = GetUsb3DebugPortInstance ();
}
if (UsbDebugPortHandle == NULL) {
return FALSE;
}
@@ -1079,7 +1089,7 @@ DebugPortPollBuffer (
//
// Store data into internal buffer for use later
//
UsbDebugPortHandle->DataCount = (UINT8) Length;
UsbDebugPortHandle->DataCount = (UINT8)Length;
return TRUE;
}
@@ -1114,17 +1124,18 @@ DebugPortInitialize (
IN DEBUG_PORT_CONTINUE Function
)
{
USB3_DEBUG_PORT_HANDLE *UsbDebugPortHandle;
USB3_DEBUG_PORT_HANDLE *UsbDebugPortHandle;
//
// Validate the PCD PcdDebugPortHandleBufferSize value
//
ASSERT (PcdGet16 (PcdDebugPortHandleBufferSize) == sizeof (USB3_DEBUG_PORT_HANDLE));
if (Function == NULL && Context != NULL) {
SetUsb3DebugPortInstance ((USB3_DEBUG_PORT_HANDLE *) Context);
return (DEBUG_PORT_HANDLE) Context;
if ((Function == NULL) && (Context != NULL)) {
SetUsb3DebugPortInstance ((USB3_DEBUG_PORT_HANDLE *)Context);
return (DEBUG_PORT_HANDLE)Context;
}
UsbDebugPortHandle = GetUsb3DebugPortInstance ();
if (UsbDebugPortHandle == NULL) {
return NULL;
@@ -1133,8 +1144,8 @@ DebugPortInitialize (
DiscoverInitializeUsbDebugPort (UsbDebugPortHandle);
if (Function != NULL) {
Function (Context, (DEBUG_PORT_HANDLE) UsbDebugPortHandle);
Function (Context, (DEBUG_PORT_HANDLE)UsbDebugPortHandle);
}
return (DEBUG_PORT_HANDLE) UsbDebugPortHandle;
return (DEBUG_PORT_HANDLE)UsbDebugPortHandle;
}

203
SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/DebugCommunicationLibUsb3Dxe.c
View File

@@ -15,12 +15,12 @@
#include <Protocol/DxeSmmReadyToLock.h>
#include "DebugCommunicationLibUsb3Internal.h"
GUID gUsb3DbgGuid = USB3_DBG_GUID;
GUID gUsb3DbgGuid = USB3_DBG_GUID;
USB3_DEBUG_PORT_HANDLE mUsb3Instance = {USB3DBG_UNINITIALIZED};
EFI_PHYSICAL_ADDRESS mUsb3InstanceAddr = 0;
EFI_PHYSICAL_ADDRESS *mUsb3InstanceAddrPtr = NULL;
EFI_PCI_IO_PROTOCOL *mUsb3PciIo = NULL;
USB3_DEBUG_PORT_HANDLE mUsb3Instance = { USB3DBG_UNINITIALIZED };
EFI_PHYSICAL_ADDRESS mUsb3InstanceAddr = 0;
EFI_PHYSICAL_ADDRESS *mUsb3InstanceAddrPtr = NULL;
EFI_PCI_IO_PROTOCOL *mUsb3PciIo = NULL;
/**
Creates a named event that can be signaled.
@@ -71,7 +71,7 @@ Usb3NamedEventListen (
// Register for an installation of protocol interface
//
Status = gBS->RegisterProtocolNotify (
(EFI_GUID *) Name,
(EFI_GUID *)Name,
*Event,
&RegistrationLocal
);
@@ -90,27 +90,27 @@ Usb3NamedEventListen (
**/
VOID
Usb3MapOneDmaBuffer (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_PHYSICAL_ADDRESS Address,
IN UINTN NumberOfBytes
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_PHYSICAL_ADDRESS Address,
IN UINTN NumberOfBytes
)
{
EFI_STATUS Status;
VOID *HostAddress;
EFI_PHYSICAL_ADDRESS DeviceAddress;
VOID *Mapping;
EFI_STATUS Status;
VOID *HostAddress;
EFI_PHYSICAL_ADDRESS DeviceAddress;
VOID *Mapping;
HostAddress = (VOID *) (UINTN) Address;
Status = PciIo->Map (
PciIo,
EfiPciIoOperationBusMasterCommonBuffer,
HostAddress,
&NumberOfBytes,
&DeviceAddress,
&Mapping
);
HostAddress = (VOID *)(UINTN)Address;
Status = PciIo->Map (
PciIo,
EfiPciIoOperationBusMasterCommonBuffer,
HostAddress,
&NumberOfBytes,
&DeviceAddress,
&Mapping
);
ASSERT_EFI_ERROR (Status);
ASSERT (DeviceAddress == ((EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress));
ASSERT (DeviceAddress == ((EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress));
}
/**
@@ -122,8 +122,8 @@ Usb3MapOneDmaBuffer (
**/
VOID
Usb3MapDmaBuffers (
IN USB3_DEBUG_PORT_HANDLE *Instance,
IN EFI_PCI_IO_PROTOCOL *PciIo
IN USB3_DEBUG_PORT_HANDLE *Instance,
IN EFI_PCI_IO_PROTOCOL *PciIo
)
{
Usb3MapOneDmaBuffer (
@@ -164,7 +164,7 @@ Usb3MapDmaBuffers (
Usb3MapOneDmaBuffer (
PciIo,
((XHC_DC_CONTEXT *) (UINTN) Instance->DebugCapabilityContext)->DbcInfoContext.String0DescAddress,
((XHC_DC_CONTEXT *)(UINTN)Instance->DebugCapabilityContext)->DbcInfoContext.String0DescAddress,
STRING0_DESC_LEN + MANU_DESC_LEN + PRODUCT_DESC_LEN + SERIAL_DESC_LEN
);
}
@@ -180,11 +180,11 @@ Usb3MapDmaBuffers (
VOID
EFIAPI
Usb3DxeSmmReadyToLockNotify (
IN EFI_EVENT Event,
IN VOID *Context
IN EFI_EVENT Event,
IN VOID *Context
)
{
USB3_DEBUG_PORT_HANDLE *Instance;
USB3_DEBUG_PORT_HANDLE *Instance;
DEBUG ((DEBUG_INFO, "%a()\n", __FUNCTION__));
@@ -221,15 +221,15 @@ Usb3GetIoMmu (
VOID
)
{
EFI_STATUS Status;
EDKII_IOMMU_PROTOCOL *IoMmu;
EFI_STATUS Status;
EDKII_IOMMU_PROTOCOL *IoMmu;
IoMmu = NULL;
IoMmu = NULL;
Status = gBS->LocateProtocol (
&gEdkiiIoMmuProtocolGuid,
NULL,
(VOID **) &IoMmu
);
&gEdkiiIoMmuProtocolGuid,
NULL,
(VOID **)&IoMmu
);
if (!EFI_ERROR (Status) && (IoMmu != NULL)) {
return IoMmu;
}
@@ -248,22 +248,22 @@ Usb3GetIoMmu (
VOID
EFIAPI
Usb3PciIoNotify (
IN EFI_EVENT Event,
IN VOID *Context
IN EFI_EVENT Event,
IN VOID *Context
)
{
EFI_STATUS Status;
UINTN PciIoHandleCount;
EFI_HANDLE *PciIoHandleBuffer;
UINTN Index;
EFI_PCI_IO_PROTOCOL *PciIo;
UINTN PciSegment;
UINTN PciBusNumber;
UINTN PciDeviceNumber;
UINTN PciFunctionNumber;
UINT32 PciAddress;
USB3_DEBUG_PORT_HANDLE *Instance;
EFI_EVENT SmmReadyToLockEvent;
EFI_STATUS Status;
UINTN PciIoHandleCount;
EFI_HANDLE *PciIoHandleBuffer;
UINTN Index;
EFI_PCI_IO_PROTOCOL *PciIo;
UINTN PciSegment;
UINTN PciBusNumber;
UINTN PciDeviceNumber;
UINTN PciFunctionNumber;
UINT32 PciAddress;
USB3_DEBUG_PORT_HANDLE *Instance;
EFI_EVENT SmmReadyToLockEvent;
Status = gBS->LocateHandleBuffer (
ByProtocol,
@@ -274,18 +274,19 @@ Usb3PciIoNotify (
);
if (!EFI_ERROR (Status) &&
(PciIoHandleBuffer != NULL) &&
(PciIoHandleCount != 0)) {
(PciIoHandleCount != 0))
{
for (Index = 0; Index < PciIoHandleCount; Index++) {
Status = gBS->HandleProtocol (
PciIoHandleBuffer[Index],
&gEfiPciIoProtocolGuid,
(VOID **) &PciIo
(VOID **)&PciIo
);
ASSERT_EFI_ERROR (Status);
Status = PciIo->GetLocation (PciIo, &PciSegment, &PciBusNumber, &PciDeviceNumber, &PciFunctionNumber);
ASSERT_EFI_ERROR (Status);
PciAddress = (UINT32) ((PciBusNumber << 20) | (PciDeviceNumber << 15) | (PciFunctionNumber << 12));
if (PciAddress == PcdGet32(PcdUsbXhciPciAddress)) {
PciAddress = (UINT32)((PciBusNumber << 20) | (PciDeviceNumber << 15) | (PciFunctionNumber << 12));
if (PciAddress == PcdGet32 (PcdUsbXhciPciAddress)) {
//
// Found the PciIo for USB3 debug port.
//
@@ -309,6 +310,7 @@ Usb3PciIoNotify (
}
}
}
gBS->CloseEvent (Event);
break;
}
@@ -331,9 +333,10 @@ GetUsb3DebugPortInstanceAddrPtr (
//
// Use the local variables temporarily.
//
mUsb3InstanceAddr = (EFI_PHYSICAL_ADDRESS) (UINTN) &mUsb3Instance;
mUsb3InstanceAddr = (EFI_PHYSICAL_ADDRESS)(UINTN)&mUsb3Instance;
mUsb3InstanceAddrPtr = &mUsb3InstanceAddr;
}
return mUsb3InstanceAddrPtr;
}
@@ -355,29 +358,30 @@ GetUsb3DebugPortInstanceAddrPtr (
**/
EFI_STATUS
Usb3AllocateDmaBuffer (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINTN Pages,
OUT VOID **Address
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINTN Pages,
OUT VOID **Address
)
{
EFI_STATUS Status;
EFI_STATUS Status;
*Address = NULL;
Status = PciIo->AllocateBuffer (
PciIo,
AllocateAnyPages,
EfiRuntimeServicesData,
Pages,
Address,
0
);
Status = PciIo->AllocateBuffer (
PciIo,
AllocateAnyPages,
EfiRuntimeServicesData,
Pages,
Address,
0
);
if (!EFI_ERROR (Status)) {
Usb3MapOneDmaBuffer (
PciIo,
(EFI_PHYSICAL_ADDRESS) (UINTN) *Address,
(EFI_PHYSICAL_ADDRESS)(UINTN)*Address,
EFI_PAGES_TO_SIZE (Pages)
);
}
return Status;
}
@@ -389,14 +393,14 @@ Usb3AllocateDmaBuffer (
@return A pointer to the allocated buffer or NULL if allocation fails.
**/
VOID*
VOID *
AllocateAlignBuffer (
IN UINTN BufferSize
IN UINTN BufferSize
)
{
EFI_PHYSICAL_ADDRESS TmpAddr;
EFI_STATUS Status;
VOID *Buf;
EFI_PHYSICAL_ADDRESS TmpAddr;
EFI_STATUS Status;
VOID *Buf;
Buf = NULL;
@@ -409,14 +413,14 @@ AllocateAlignBuffer (
);
} else {
TmpAddr = 0xFFFFFFFF;
Status = gBS->AllocatePages (
AllocateMaxAddress,
EfiACPIMemoryNVS,
EFI_SIZE_TO_PAGES (BufferSize),
&TmpAddr
);
Status = gBS->AllocatePages (
AllocateMaxAddress,
EfiACPIMemoryNVS,
EFI_SIZE_TO_PAGES (BufferSize),
&TmpAddr
);
if (!EFI_ERROR (Status)) {
Buf = (VOID *) (UINTN) TmpAddr;
Buf = (VOID *)(UINTN)TmpAddr;
}
}
}
@@ -440,34 +444,34 @@ DebugCommunicationUsb3DxeConstructor (
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_PHYSICAL_ADDRESS *AddrPtr;
USB3_DEBUG_PORT_HANDLE *Instance;
EFI_PHYSICAL_ADDRESS Address;
EFI_STATUS Status;
EFI_EVENT Event;
EFI_PHYSICAL_ADDRESS *AddrPtr;
USB3_DEBUG_PORT_HANDLE *Instance;
EFI_PHYSICAL_ADDRESS Address;
EFI_STATUS Status;
EFI_EVENT Event;
Status = EfiGetSystemConfigurationTable (&gUsb3DbgGuid, (VOID **) &AddrPtr);
Status = EfiGetSystemConfigurationTable (&gUsb3DbgGuid, (VOID **)&AddrPtr);
if (EFI_ERROR (Status) || (AddrPtr == NULL)) {
//
// Instead of using local variables, install system configuration table for
// the local instance and the buffer to save instance address pointer.
//
Address = SIZE_4GB;
Status = gBS->AllocatePages (
AllocateMaxAddress,
EfiACPIMemoryNVS,
EFI_SIZE_TO_PAGES (sizeof (EFI_PHYSICAL_ADDRESS) + sizeof (USB3_DEBUG_PORT_HANDLE)),
&Address
);
Status = gBS->AllocatePages (
AllocateMaxAddress,
EfiACPIMemoryNVS,
EFI_SIZE_TO_PAGES (sizeof (EFI_PHYSICAL_ADDRESS) + sizeof (USB3_DEBUG_PORT_HANDLE)),
&Address
);
if (EFI_ERROR (Status)) {
return Status;
}
AddrPtr = (EFI_PHYSICAL_ADDRESS *) (UINTN) Address;
AddrPtr = (EFI_PHYSICAL_ADDRESS *)(UINTN)Address;
ZeroMem (AddrPtr, sizeof (EFI_PHYSICAL_ADDRESS) + sizeof (USB3_DEBUG_PORT_HANDLE));
Instance = (USB3_DEBUG_PORT_HANDLE *) (AddrPtr + 1);
Instance = (USB3_DEBUG_PORT_HANDLE *)(AddrPtr + 1);
CopyMem (Instance, &mUsb3Instance, sizeof (USB3_DEBUG_PORT_HANDLE));
*AddrPtr = (EFI_PHYSICAL_ADDRESS) (UINTN) Instance;
*AddrPtr = (EFI_PHYSICAL_ADDRESS)(UINTN)Instance;
Status = gBS->InstallConfigurationTable (&gUsb3DbgGuid, AddrPtr);
if (EFI_ERROR (Status)) {
@@ -478,6 +482,7 @@ DebugCommunicationUsb3DxeConstructor (
if (mUsb3InstanceAddrPtr != NULL) {
*AddrPtr = *mUsb3InstanceAddrPtr;
}
mUsb3InstanceAddrPtr = AddrPtr;
Instance = GetUsb3DebugPortInstance ();
@@ -491,7 +496,7 @@ DebugCommunicationUsb3DxeConstructor (
&Event
);
if (!EFI_ERROR (Status)) {
Instance->PciIoEvent = (EFI_PHYSICAL_ADDRESS) (UINTN) Event;
Instance->PciIoEvent = (EFI_PHYSICAL_ADDRESS)(UINTN)Event;
}
}
@@ -514,7 +519,7 @@ DebugCommunicationUsb3DxeDestructor (
IN EFI_SYSTEM_TABLE *SystemTable
)
{
USB3_DEBUG_PORT_HANDLE *Instance;
USB3_DEBUG_PORT_HANDLE *Instance;
Instance = GetUsb3DebugPortInstance ();
ASSERT (Instance != NULL);
@@ -523,9 +528,9 @@ DebugCommunicationUsb3DxeDestructor (
//
// Close the event created.
//
gBS->CloseEvent ((EFI_EVENT) (UINTN) Instance->PciIoEvent);
gBS->CloseEvent ((EFI_EVENT)(UINTN)Instance->PciIoEvent);
Instance->PciIoEvent = 0;
}
return EFI_SUCCESS;
}

510
SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/DebugCommunicationLibUsb3Internal.h
View File

@@ -36,101 +36,101 @@
//
// The state machine of usb debug port
//
#define USB3DBG_NO_DBG_CAB 0 // The XHCI host controller does not support debug capability
#define USB3DBG_DBG_CAB 1 // The XHCI host controller supports debug capability
#define USB3DBG_ENABLED 2 // The XHCI debug device is enabled
#define USB3DBG_NOT_ENABLED 4 // The XHCI debug device is not enabled
#define USB3DBG_UNINITIALIZED 255 // The XHCI debug device is uninitialized
#define USB3DBG_NO_DBG_CAB 0 // The XHCI host controller does not support debug capability
#define USB3DBG_DBG_CAB 1 // The XHCI host controller supports debug capability
#define USB3DBG_ENABLED 2 // The XHCI debug device is enabled
#define USB3DBG_NOT_ENABLED 4 // The XHCI debug device is not enabled
#define USB3DBG_UNINITIALIZED 255 // The XHCI debug device is uninitialized
#define USB3_DEBUG_PORT_WRITE_MAX_PACKET_SIZE 0x08
#define USB3_DEBUG_PORT_WRITE_MAX_PACKET_SIZE 0x08
//
// MaxPacketSize for DbC Endpoint Descriptor IN and OUT
//
#define XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE 0x400
#define XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE 0x400
#define XHCI_DEBUG_DEVICE_VENDOR_ID 0x0525
#define XHCI_DEBUG_DEVICE_PRODUCT_ID 0x127A
#define XHCI_DEBUG_DEVICE_PROTOCOL 0xFF
#define XHCI_DEBUG_DEVICE_REVISION 0x00
#define XHCI_BASE_ADDRESS_64_BIT_MASK 0xFFFFFFFFFFFF0000ULL
#define XHCI_BASE_ADDRESS_32_BIT_MASK 0xFFFF0000
#define XHCI_BASE_ADDRESS_64_BIT_MASK 0xFFFFFFFFFFFF0000ULL
#define XHCI_BASE_ADDRESS_32_BIT_MASK 0xFFFF0000
#define PCI_CAPABILITY_ID_DEBUG_PORT 0x0A
#define XHC_HCCPARAMS_OFFSET 0x10
#define XHC_CAPABILITY_ID_MASK 0xFF
#define XHC_NEXT_CAPABILITY_MASK 0xFF00
#define XHC_HCSPARAMS1_OFFSET 0x4 // Structural Parameters 1
#define XHC_USBCMD_OFFSET 0x0 // USB Command Register Offset
#define XHC_USBSTS_OFFSET 0x4 // USB Status Register Offset
#define XHC_PORTSC_OFFSET 0x400 // Port Status and Control Register Offset
#define XHC_HCSPARAMS1_OFFSET 0x4 // Structural Parameters 1
#define XHC_USBCMD_OFFSET 0x0 // USB Command Register Offset
#define XHC_USBSTS_OFFSET 0x4 // USB Status Register Offset
#define XHC_PORTSC_OFFSET 0x400 // Port Status and Control Register Offset
#define XHC_USBCMD_RUN BIT0 // Run/Stop
#define XHC_USBCMD_RESET BIT1 // Host Controller Reset
#define XHC_USBCMD_RUN BIT0 // Run/Stop
#define XHC_USBCMD_RESET BIT1 // Host Controller Reset
#define XHC_USBSTS_HALT BIT0
#define XHC_USBSTS_HALT BIT0
//
// Indicate the timeout when data is transferred in microsecond. 0 means infinite timeout.
//
#define DATA_TRANSFER_WRITE_TIMEOUT 0
#define DATA_TRANSFER_READ_TIMEOUT 50000
#define DATA_TRANSFER_POLL_TIMEOUT 1000
#define XHC_DEBUG_PORT_1_MILLISECOND 1000
#define DATA_TRANSFER_WRITE_TIMEOUT 0
#define DATA_TRANSFER_READ_TIMEOUT 50000
#define DATA_TRANSFER_POLL_TIMEOUT 1000
#define XHC_DEBUG_PORT_1_MILLISECOND 1000
//
// XHCI port power off/on delay
//
#define XHC_DEBUG_PORT_ON_OFF_DELAY 100000
#define XHC_DEBUG_PORT_ON_OFF_DELAY 100000
//
// USB debug device string descriptor (header size + unicode string length)
//
#define STRING0_DESC_LEN 4
#define MANU_DESC_LEN 12
#define PRODUCT_DESC_LEN 40
#define SERIAL_DESC_LEN 4
#define STRING0_DESC_LEN 4
#define MANU_DESC_LEN 12
#define PRODUCT_DESC_LEN 40
#define SERIAL_DESC_LEN 4
//
// Debug Capability Register Offset
//
#define XHC_DC_DCID 0x0
#define XHC_DC_DCDB 0x4
#define XHC_DC_DCERSTSZ 0x8
#define XHC_DC_DCERSTBA 0x10
#define XHC_DC_DCERDP 0x18
#define XHC_DC_DCCTRL 0x20
#define XHC_DC_DCST 0x24
#define XHC_DC_DCPORTSC 0x28
#define XHC_DC_DCCP 0x30
#define XHC_DC_DCDDI1 0x38
#define XHC_DC_DCDDI2 0x3C
#define XHC_DC_DCID 0x0
#define XHC_DC_DCDB 0x4
#define XHC_DC_DCERSTSZ 0x8
#define XHC_DC_DCERSTBA 0x10
#define XHC_DC_DCERDP 0x18
#define XHC_DC_DCCTRL 0x20
#define XHC_DC_DCST 0x24
#define XHC_DC_DCPORTSC 0x28
#define XHC_DC_DCCP 0x30
#define XHC_DC_DCDDI1 0x38
#define XHC_DC_DCDDI2 0x3C
#define TRB_TYPE_LINK 6
#define TRB_TYPE_LINK 6
#define ERST_NUMBER 0x01
#define TR_RING_TRB_NUMBER 0x100
#define EVENT_RING_TRB_NUMBER 0x200
#define ERST_NUMBER 0x01
#define TR_RING_TRB_NUMBER 0x100
#define EVENT_RING_TRB_NUMBER 0x200
#define ED_BULK_OUT 2
#define ED_BULK_IN 6
#define ED_BULK_OUT 2
#define ED_BULK_IN 6
#define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))
#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))
#define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
#define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))
#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))
#define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
//
// Endpoint Type (EP Type).
//
#define ED_NOT_VALID 0
#define ED_ISOCH_OUT 1
#define ED_BULK_OUT 2
#define ED_INTERRUPT_OUT 3
#define ED_CONTROL_BIDIR 4
#define ED_ISOCH_IN 5
#define ED_BULK_IN 6
#define ED_INTERRUPT_IN 7
#define ED_NOT_VALID 0
#define ED_ISOCH_OUT 1
#define ED_BULK_OUT 2
#define ED_INTERRUPT_OUT 3
#define ED_CONTROL_BIDIR 4
#define ED_ISOCH_IN 5
#define ED_BULK_IN 6
#define ED_INTERRUPT_IN 7
//
// 6.4.5 TRB Completion Codes
@@ -147,67 +147,67 @@
//
// 6.4.6 TRB Types
//
#define TRB_TYPE_NORMAL 1
#define TRB_TYPE_SETUP_STAGE 2
#define TRB_TYPE_DATA_STAGE 3
#define TRB_TYPE_STATUS_STAGE 4
#define TRB_TYPE_ISOCH 5
#define TRB_TYPE_LINK 6
#define TRB_TYPE_EVENT_DATA 7
#define TRB_TYPE_NO_OP 8
#define TRB_TYPE_EN_SLOT 9
#define TRB_TYPE_DIS_SLOT 10
#define TRB_TYPE_ADDRESS_DEV 11
#define TRB_TYPE_CON_ENDPOINT 12
#define TRB_TYPE_EVALU_CONTXT 13
#define TRB_TYPE_RESET_ENDPOINT 14
#define TRB_TYPE_STOP_ENDPOINT 15
#define TRB_TYPE_SET_TR_DEQUE 16
#define TRB_TYPE_RESET_DEV 17
#define TRB_TYPE_GET_PORT_BANW 21
#define TRB_TYPE_FORCE_HEADER 22
#define TRB_TYPE_NO_OP_COMMAND 23
#define TRB_TYPE_TRANS_EVENT 32
#define TRB_TYPE_COMMAND_COMPLT_EVENT 33
#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
#define TRB_TYPE_HOST_CONTROLLER_EVENT 37
#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38
#define TRB_TYPE_MFINDEX_WRAP_EVENT 39
#define TRB_TYPE_NORMAL 1
#define TRB_TYPE_SETUP_STAGE 2
#define TRB_TYPE_DATA_STAGE 3
#define TRB_TYPE_STATUS_STAGE 4
#define TRB_TYPE_ISOCH 5
#define TRB_TYPE_LINK 6
#define TRB_TYPE_EVENT_DATA 7
#define TRB_TYPE_NO_OP 8
#define TRB_TYPE_EN_SLOT 9
#define TRB_TYPE_DIS_SLOT 10
#define TRB_TYPE_ADDRESS_DEV 11
#define TRB_TYPE_CON_ENDPOINT 12
#define TRB_TYPE_EVALU_CONTXT 13
#define TRB_TYPE_RESET_ENDPOINT 14
#define TRB_TYPE_STOP_ENDPOINT 15
#define TRB_TYPE_SET_TR_DEQUE 16
#define TRB_TYPE_RESET_DEV 17
#define TRB_TYPE_GET_PORT_BANW 21
#define TRB_TYPE_FORCE_HEADER 22
#define TRB_TYPE_NO_OP_COMMAND 23
#define TRB_TYPE_TRANS_EVENT 32
#define TRB_TYPE_COMMAND_COMPLT_EVENT 33
#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
#define TRB_TYPE_HOST_CONTROLLER_EVENT 37
#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38
#define TRB_TYPE_MFINDEX_WRAP_EVENT 39
//
// Convert millisecond to microsecond.
//
#define XHC_1_MILLISECOND (1000)
#define XHC_POLL_DELAY (1000)
#define XHC_GENERIC_TIMEOUT (10 * 1000)
#define XHC_1_MILLISECOND (1000)
#define XHC_POLL_DELAY (1000)
#define XHC_GENERIC_TIMEOUT (10 * 1000)
#define EFI_USB_SPEED_FULL 0x0000 ///< 12 Mb/s, USB 1.1 OHCI and UHCI HC.
#define EFI_USB_SPEED_LOW 0x0001 ///< 1 Mb/s, USB 1.1 OHCI and UHCI HC.
#define EFI_USB_SPEED_HIGH 0x0002 ///< 480 Mb/s, USB 2.0 EHCI HC.
#define EFI_USB_SPEED_SUPER 0x0003 ///< 4.8 Gb/s, USB 3.0 XHCI HC.
#define EFI_USB_SPEED_FULL 0x0000 ///< 12 Mb/s, USB 1.1 OHCI and UHCI HC.
#define EFI_USB_SPEED_LOW 0x0001 ///< 1 Mb/s, USB 1.1 OHCI and UHCI HC.
#define EFI_USB_SPEED_HIGH 0x0002 ///< 480 Mb/s, USB 2.0 EHCI HC.
#define EFI_USB_SPEED_SUPER 0x0003 ///< 4.8 Gb/s, USB 3.0 XHCI HC.
//
// Transfer types, used in URB to identify the transfer type
//
#define XHC_CTRL_TRANSFER 0x01
#define XHC_BULK_TRANSFER 0x02
#define XHC_INT_TRANSFER_SYNC 0x04
#define XHC_INT_TRANSFER_ASYNC 0x08
#define XHC_INT_ONLY_TRANSFER_ASYNC 0x10
#define XHC_CTRL_TRANSFER 0x01
#define XHC_BULK_TRANSFER 0x02
#define XHC_INT_TRANSFER_SYNC 0x04
#define XHC_INT_TRANSFER_ASYNC 0x08
#define XHC_INT_ONLY_TRANSFER_ASYNC 0x10
//
// USB Transfer Results
//
#define EFI_USB_NOERROR 0x00
#define EFI_USB_ERR_NOTEXECUTE 0x01
#define EFI_USB_ERR_STALL 0x02
#define EFI_USB_ERR_BUFFER 0x04
#define EFI_USB_ERR_BABBLE 0x08
#define EFI_USB_ERR_NAK 0x10
#define EFI_USB_ERR_CRC 0x20
#define EFI_USB_ERR_TIMEOUT 0x40
#define EFI_USB_ERR_BITSTUFF 0x80
#define EFI_USB_ERR_SYSTEM 0x100
#define EFI_USB_NOERROR 0x00
#define EFI_USB_ERR_NOTEXECUTE 0x01
#define EFI_USB_ERR_STALL 0x02
#define EFI_USB_ERR_BUFFER 0x04
#define EFI_USB_ERR_BABBLE 0x08
#define EFI_USB_ERR_NAK 0x10
#define EFI_USB_ERR_CRC 0x20
#define EFI_USB_ERR_TIMEOUT 0x40
#define EFI_USB_ERR_BITSTUFF 0x80
#define EFI_USB_ERR_SYSTEM 0x100
#pragma pack(1)
@@ -216,42 +216,42 @@
// 7.6.9.2 When used by the DbC it is always a 64 byte data structure
//
typedef struct _ENDPOINT_CONTEXT_64 {
UINT32 EPState:3;
UINT32 RsvdZ1:5;
UINT32 Mult:2; // set to 0
UINT32 MaxPStreams:5; // set to 0
UINT32 LSA:1; // set to 0
UINT32 Interval:8; // set to 0
UINT32 RsvdZ2:8;
UINT32 EPState : 3;
UINT32 RsvdZ1 : 5;
UINT32 Mult : 2; // set to 0
UINT32 MaxPStreams : 5; // set to 0
UINT32 LSA : 1; // set to 0
UINT32 Interval : 8; // set to 0
UINT32 RsvdZ2 : 8;
UINT32 RsvdZ3:1;
UINT32 CErr:2;
UINT32 EPType:3;
UINT32 RsvdZ4:1;
UINT32 HID:1; // set to 0
UINT32 MaxBurstSize:8;
UINT32 MaxPacketSize:16;
UINT32 RsvdZ3 : 1;
UINT32 CErr : 2;
UINT32 EPType : 3;
UINT32 RsvdZ4 : 1;
UINT32 HID : 1; // set to 0
UINT32 MaxBurstSize : 8;
UINT32 MaxPacketSize : 16;
UINT32 PtrLo;
UINT32 PtrLo;
UINT32 PtrHi;
UINT32 PtrHi;
UINT32 AverageTRBLength:16;
UINT32 MaxESITPayload:16; // set to 0
UINT32 AverageTRBLength : 16;
UINT32 MaxESITPayload : 16; // set to 0
UINT32 RsvdZ5; // Reserved
UINT32 RsvdZ6;
UINT32 RsvdZ7;
UINT32 RsvdZ5; // Reserved
UINT32 RsvdZ6;
UINT32 RsvdZ7;
UINT32 RsvdZ8;
UINT32 RsvdZ9;
UINT32 RsvdZ10;
UINT32 RsvdZ11;
UINT32 RsvdZ8;
UINT32 RsvdZ9;
UINT32 RsvdZ10;
UINT32 RsvdZ11;
UINT32 RsvdZ12;
UINT32 RsvdZ13;
UINT32 RsvdZ14;
UINT32 RsvdZ15;
UINT32 RsvdZ12;
UINT32 RsvdZ13;
UINT32 RsvdZ14;
UINT32 RsvdZ15;
} ENDPOINT_CONTEXT_64;
//
@@ -261,25 +261,25 @@ typedef struct _ENDPOINT_CONTEXT_64 {
// Rings, and to define the Data stage information for Control Transfer Rings.
//
typedef struct _TRANSFER_TRB_NORMAL {
UINT32 TRBPtrLo;
UINT32 TRBPtrLo;
UINT32 TRBPtrHi;
UINT32 TRBPtrHi;
UINT32 Length:17;
UINT32 TDSize:5;
UINT32 IntTarget:10;
UINT32 Length : 17;
UINT32 TDSize : 5;
UINT32 IntTarget : 10;
UINT32 CycleBit:1;
UINT32 ENT:1;
UINT32 ISP:1;
UINT32 NS:1;
UINT32 CH:1;
UINT32 IOC:1;
UINT32 IDT:1;
UINT32 RsvdZ1:2;
UINT32 BEI:1;
UINT32 Type:6;
UINT32 RsvdZ2:16;
UINT32 CycleBit : 1;
UINT32 ENT : 1;
UINT32 ISP : 1;
UINT32 NS : 1;
UINT32 CH : 1;
UINT32 IOC : 1;
UINT32 IDT : 1;
UINT32 RsvdZ1 : 2;
UINT32 BEI : 1;
UINT32 Type : 6;
UINT32 RsvdZ2 : 16;
} TRANSFER_TRB_NORMAL;
//
@@ -288,21 +288,21 @@ typedef struct _TRANSFER_TRB_NORMAL {
// for more information on the use and operation of Transfer Events.
//
typedef struct _EVT_TRB_TRANSFER {
UINT32 TRBPtrLo;
UINT32 TRBPtrLo;
UINT32 TRBPtrHi;
UINT32 TRBPtrHi;
UINT32 Length:24;
UINT32 Completecode:8;
UINT32 Length : 24;
UINT32 Completecode : 8;
UINT32 CycleBit:1;
UINT32 RsvdZ1:1;
UINT32 ED:1;
UINT32 RsvdZ2:7;
UINT32 Type:6;
UINT32 EndpointId:5;
UINT32 RsvdZ3:3;
UINT32 SlotId:8;
UINT32 CycleBit : 1;
UINT32 RsvdZ1 : 1;
UINT32 ED : 1;
UINT32 RsvdZ2 : 7;
UINT32 Type : 6;
UINT32 EndpointId : 5;
UINT32 RsvdZ3 : 3;
UINT32 SlotId : 8;
} EVT_TRB_TRANSFER;
//
@@ -310,104 +310,104 @@ typedef struct _EVT_TRB_TRANSFER {
// A Link TRB provides support for non-contiguous TRB Rings.
//
typedef struct _LINK_TRB {
UINT32 PtrLo;
UINT32 PtrLo;
UINT32 PtrHi;
UINT32 PtrHi;
UINT32 RsvdZ1:22;
UINT32 InterTarget:10;
UINT32 RsvdZ1 : 22;
UINT32 InterTarget : 10;
UINT32 CycleBit:1;
UINT32 TC:1;
UINT32 RsvdZ2:2;
UINT32 CH:1;
UINT32 IOC:1;
UINT32 RsvdZ3:4;
UINT32 Type:6;
UINT32 RsvdZ4:16;
UINT32 CycleBit : 1;
UINT32 TC : 1;
UINT32 RsvdZ2 : 2;
UINT32 CH : 1;
UINT32 IOC : 1;
UINT32 RsvdZ3 : 4;
UINT32 Type : 6;
UINT32 RsvdZ4 : 16;
} LINK_TRB;
//
// TRB Template: 16 bytes
//
typedef struct _TRB_TEMPLATE {
UINT32 Parameter1;
UINT32 Parameter1;
UINT32 Parameter2;
UINT32 Parameter2;
UINT32 Status;
UINT32 Status;
UINT32 CycleBit:1;
UINT32 RsvdZ1:9;
UINT32 Type:6;
UINT32 Control:16;
UINT32 CycleBit : 1;
UINT32 RsvdZ1 : 9;
UINT32 Type : 6;
UINT32 Control : 16;
} TRB_TEMPLATE;
//
// Refer to XHCI 6.5 Event Ring Segment Table: 16 bytes
//
typedef struct _EVENT_RING_SEG_TABLE_ENTRY {
UINT32 PtrLo;
UINT32 PtrHi;
UINT32 RingTrbSize:16;
UINT32 RsvdZ1:16;
UINT32 RsvdZ2;
UINT32 PtrLo;
UINT32 PtrHi;
UINT32 RingTrbSize : 16;
UINT32 RsvdZ1 : 16;
UINT32 RsvdZ2;
} EVENT_RING_SEG_TABLE_ENTRY;
//
// Size: 40 bytes
//
typedef struct _EVENT_RING {
EFI_PHYSICAL_ADDRESS ERSTBase;
EFI_PHYSICAL_ADDRESS EventRingSeg0;
UINT32 TrbNumber;
EFI_PHYSICAL_ADDRESS EventRingEnqueue;
EFI_PHYSICAL_ADDRESS EventRingDequeue;
UINT32 EventRingCCS;
EFI_PHYSICAL_ADDRESS ERSTBase;
EFI_PHYSICAL_ADDRESS EventRingSeg0;
UINT32 TrbNumber;
EFI_PHYSICAL_ADDRESS EventRingEnqueue;
EFI_PHYSICAL_ADDRESS EventRingDequeue;
UINT32 EventRingCCS;
} EVENT_RING;
// Size: 32 bytes
typedef struct _TRANSFER_RING {
EFI_PHYSICAL_ADDRESS RingSeg0;
UINT32 TrbNumber;
EFI_PHYSICAL_ADDRESS RingEnqueue;
EFI_PHYSICAL_ADDRESS RingDequeue;
UINT32 RingPCS;
EFI_PHYSICAL_ADDRESS RingSeg0;
UINT32 TrbNumber;
EFI_PHYSICAL_ADDRESS RingEnqueue;
EFI_PHYSICAL_ADDRESS RingDequeue;
UINT32 RingPCS;
} TRANSFER_RING;
//
// Size: 64 bytes
//
typedef struct _DBC_INFO_CONTEXT {
UINT64 String0DescAddress;
UINT64 ManufacturerStrDescAddress;
UINT64 ProductStrDescAddress;
UINT64 SerialNumberStrDescAddress;
UINT64 String0Length:8;
UINT64 ManufacturerStrLength:8;
UINT64 ProductStrLength:8;
UINT64 SerialNumberStrLength:8;
UINT64 RsvdZ1:32;
UINT64 RsvdZ2;
UINT64 RsvdZ3;
UINT64 RsvdZ4;
UINT64 String0DescAddress;
UINT64 ManufacturerStrDescAddress;
UINT64 ProductStrDescAddress;
UINT64 SerialNumberStrDescAddress;
UINT64 String0Length : 8;
UINT64 ManufacturerStrLength : 8;
UINT64 ProductStrLength : 8;
UINT64 SerialNumberStrLength : 8;
UINT64 RsvdZ1 : 32;
UINT64 RsvdZ2;
UINT64 RsvdZ3;
UINT64 RsvdZ4;
} DBC_INFO_CONTEXT;
//
// Debug Capability Context Data Structure: 192 bytes
//
typedef struct _XHC_DC_CONTEXT {
DBC_INFO_CONTEXT DbcInfoContext;
ENDPOINT_CONTEXT_64 EpOutContext;
ENDPOINT_CONTEXT_64 EpInContext;
DBC_INFO_CONTEXT DbcInfoContext;
ENDPOINT_CONTEXT_64 EpOutContext;
ENDPOINT_CONTEXT_64 EpInContext;
} XHC_DC_CONTEXT;
//
// Size: 16 bytes
//
typedef union _TRB {
TRB_TEMPLATE TrbTemplate;
TRANSFER_TRB_NORMAL TrbNormal;
TRB_TEMPLATE TrbTemplate;
TRANSFER_TRB_NORMAL TrbNormal;
} TRB;
///
@@ -427,113 +427,113 @@ typedef struct _URB {
//
// Transfer data buffer
//
EFI_PHYSICAL_ADDRESS Data;
UINT32 DataLen;
EFI_PHYSICAL_ADDRESS Data;
UINT32 DataLen;
//
// Execute result
//
UINT32 Result;
UINT32 Result;
//
// Completed data length
//
UINT32 Completed;
UINT32 Completed;
//
// Tranfer Ring info
//
EFI_PHYSICAL_ADDRESS Ring;
EFI_PHYSICAL_ADDRESS Trb;
BOOLEAN Finished;
EFI_USB_DATA_DIRECTION Direction;
EFI_PHYSICAL_ADDRESS Ring;
EFI_PHYSICAL_ADDRESS Trb;
BOOLEAN Finished;
EFI_USB_DATA_DIRECTION Direction;
} URB;
typedef struct _USB3_DEBUG_PORT_INSTANCE {
UINT8 Initialized;
UINT8 Initialized;
//
// The flag indicates debug capability is supported
//
BOOLEAN DebugSupport;
BOOLEAN DebugSupport;
//
// The flag indicates debug device is ready
//
BOOLEAN Ready;
BOOLEAN Ready;
//
// The flag indicates the instance is from HOB
//
BOOLEAN FromHob;
BOOLEAN FromHob;
//
// Prevent notification being interrupted by debug timer
//
BOOLEAN InNotify;
BOOLEAN InNotify;
//
// PciIo protocol event
//
EFI_PHYSICAL_ADDRESS PciIoEvent;
EFI_PHYSICAL_ADDRESS PciIoEvent;
//
// The flag indicates if USB 3.0 ports has been turn off/on power
//
BOOLEAN ChangePortPower;
BOOLEAN ChangePortPower;
//
// XHCI MMIO Base address
//
EFI_PHYSICAL_ADDRESS XhciMmioBase;
EFI_PHYSICAL_ADDRESS XhciMmioBase;
//
// XHCI OP RegisterBase address
//
EFI_PHYSICAL_ADDRESS XhciOpRegister;
EFI_PHYSICAL_ADDRESS XhciOpRegister;
//
// XHCI Debug Register Base Address
//
EFI_PHYSICAL_ADDRESS DebugCapabilityBase;
EFI_PHYSICAL_ADDRESS DebugCapabilityBase;
//
// XHCI Debug Capability offset
//
UINT64 DebugCapabilityOffset;
UINT64 DebugCapabilityOffset;
//
// XHCI Debug Context Address
//
EFI_PHYSICAL_ADDRESS DebugCapabilityContext;
EFI_PHYSICAL_ADDRESS DebugCapabilityContext;
//
// Transfer Ring
//
TRANSFER_RING TransferRingOut;
TRANSFER_RING TransferRingIn;
TRANSFER_RING TransferRingOut;
TRANSFER_RING TransferRingIn;
//
// EventRing
//
EVENT_RING EventRing;
EVENT_RING EventRing;
//
// URB - Read
//
URB UrbOut;
URB UrbOut;
//
// URB - Write
//
URB UrbIn;
URB UrbIn;
//
// The available data length in the following data buffer.
//
UINT8 DataCount;
UINT8 DataCount;
//
// The data buffer address for data read and poll.
//
EFI_PHYSICAL_ADDRESS Data;
EFI_PHYSICAL_ADDRESS Data;
} USB3_DEBUG_PORT_HANDLE;
#pragma pack()
@@ -549,8 +549,8 @@ typedef struct _USB3_DEBUG_PORT_INSTANCE {
**/
UINT32
XhcReadDebugReg (
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN UINT32 Offset
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN UINT32 Offset
);
/**
@@ -578,9 +578,9 @@ XhcSetDebugRegBit (
**/
VOID
XhcWriteDebugReg (
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN UINT32 Offset,
IN UINT32 Data
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN UINT32 Offset,
IN UINT32 Data
);
/**
@@ -594,7 +594,7 @@ XhcWriteDebugReg (
is not enabled.
**/
BOOLEAN
XhcIsBitSet(
XhcIsBitSet (
UINTN Register,
UINT32 BitMask
);
@@ -606,7 +606,7 @@ XhcIsBitSet(
@param[in] BitMask 32-bit mask
**/
VOID
XhcSetR32Bit(
XhcSetR32Bit (
UINTN Register,
UINT32 BitMask
);
@@ -618,9 +618,9 @@ XhcSetR32Bit(
@param[in] BitMask 32-bit mask
**/
VOID
XhcClearR32Bit(
IN OUT UINTN Register,
IN UINT32 BitMask
XhcClearR32Bit (
IN OUT UINTN Register,
IN UINT32 BitMask
);
/**
@@ -654,9 +654,9 @@ GetXhciPciCommand (
@return A pointer to the allocated buffer or NULL if allocation fails.
**/
VOID*
VOID *
AllocateAlignBuffer (
IN UINTN BufferSize
IN UINTN BufferSize
);
/**
@@ -694,11 +694,11 @@ USB3InitializeReal (
EFI_STATUS
EFIAPI
XhcDataTransfer (
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN EFI_USB_DATA_DIRECTION Direction,
IN OUT VOID *Data,
IN OUT UINTN *DataLength,
IN UINTN Timeout
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN EFI_USB_DATA_DIRECTION Direction,
IN OUT VOID *Data,
IN OUT UINTN *DataLength,
IN UINTN Timeout
);
/**
@@ -713,7 +713,7 @@ XhcDataTransfer (
RETURN_STATUS
EFIAPI
InitializeUsbDebugHardware (
IN USB3_DEBUG_PORT_HANDLE *Handle
IN USB3_DEBUG_PORT_HANDLE *Handle
);
/**

83
SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/DebugCommunicationLibUsb3Pei.c
View File

@@ -13,7 +13,7 @@
#include <Ppi/IoMmu.h>
#include "DebugCommunicationLibUsb3Internal.h"
GUID gUsb3DbgGuid = USB3_DBG_GUID;
GUID gUsb3DbgGuid = USB3_DBG_GUID;
/**
USB3 IOMMU PPI notify.
@@ -33,7 +33,7 @@ Usb3IoMmuPpiNotify (
IN VOID *Ppi
)
{
USB3_DEBUG_PORT_HANDLE *Instance;
USB3_DEBUG_PORT_HANDLE *Instance;
DEBUG ((DEBUG_INFO, "%a()\n", __FUNCTION__));
@@ -60,7 +60,7 @@ Usb3IoMmuPpiNotify (
return EFI_SUCCESS;
}
EFI_PEI_NOTIFY_DESCRIPTOR mUsb3IoMmuPpiNotifyDesc = {
EFI_PEI_NOTIFY_DESCRIPTOR mUsb3IoMmuPpiNotifyDesc = {
(EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEdkiiIoMmuPpiGuid,
Usb3IoMmuPpiNotify
@@ -94,12 +94,12 @@ IoMmuAllocateBuffer (
OUT VOID **Mapping
)
{
EFI_STATUS Status;
UINTN NumberOfBytes;
EFI_STATUS Status;
UINTN NumberOfBytes;
*HostAddress = NULL;
*HostAddress = NULL;
*DeviceAddress = 0;
*Mapping = NULL;
*Mapping = NULL;
Status = IoMmu->AllocateBuffer (
IoMmu,
@@ -113,19 +113,20 @@ IoMmuAllocateBuffer (
}
NumberOfBytes = EFI_PAGES_TO_SIZE (Pages);
Status = IoMmu->Map (
IoMmu,
EdkiiIoMmuOperationBusMasterCommonBuffer,
*HostAddress,
&NumberOfBytes,
DeviceAddress,
Mapping
);
Status = IoMmu->Map (
IoMmu,
EdkiiIoMmuOperationBusMasterCommonBuffer,
*HostAddress,
&NumberOfBytes,
DeviceAddress,
Mapping
);
if (EFI_ERROR (Status)) {
IoMmu->FreeBuffer (IoMmu, Pages, *HostAddress);
*HostAddress = NULL;
return EFI_OUT_OF_RESOURCES;
}
Status = IoMmu->SetAttribute (
IoMmu,
*Mapping,
@@ -134,7 +135,7 @@ IoMmuAllocateBuffer (
if (EFI_ERROR (Status)) {
IoMmu->Unmap (IoMmu, *Mapping);
IoMmu->FreeBuffer (IoMmu, Pages, *HostAddress);
*Mapping = NULL;
*Mapping = NULL;
*HostAddress = NULL;
return Status;
}
@@ -153,15 +154,15 @@ Usb3GetIoMmu (
VOID
)
{
EFI_STATUS Status;
EDKII_IOMMU_PPI *IoMmu;
EFI_STATUS Status;
EDKII_IOMMU_PPI *IoMmu;
IoMmu = NULL;
IoMmu = NULL;
Status = PeiServicesLocatePpi (
&gEdkiiIoMmuPpiGuid,
0,
NULL,
(VOID **) &IoMmu
(VOID **)&IoMmu
);
if (!EFI_ERROR (Status) && (IoMmu != NULL)) {
return IoMmu;
@@ -179,10 +180,10 @@ GetUsb3DebugPortInstanceAddrPtr (
VOID
)
{
USB3_DEBUG_PORT_HANDLE *Instance;
EFI_PHYSICAL_ADDRESS *AddrPtr;
EFI_PEI_HOB_POINTERS Hob;
EFI_STATUS Status;
USB3_DEBUG_PORT_HANDLE *Instance;
EFI_PHYSICAL_ADDRESS *AddrPtr;
EFI_PEI_HOB_POINTERS Hob;
EFI_STATUS Status;
Hob.Raw = GetFirstGuidHob (&gUsb3DbgGuid);
if (Hob.Raw == NULL) {
@@ -196,9 +197,9 @@ GetUsb3DebugPortInstanceAddrPtr (
);
ASSERT (AddrPtr != NULL);
ZeroMem (AddrPtr, sizeof (EFI_PHYSICAL_ADDRESS) + sizeof (USB3_DEBUG_PORT_HANDLE));
Instance = (USB3_DEBUG_PORT_HANDLE *) (AddrPtr + 1);
*AddrPtr = (EFI_PHYSICAL_ADDRESS) (UINTN) Instance;
Instance->FromHob = TRUE;
Instance = (USB3_DEBUG_PORT_HANDLE *)(AddrPtr + 1);
*AddrPtr = (EFI_PHYSICAL_ADDRESS)(UINTN)Instance;
Instance->FromHob = TRUE;
Instance->Initialized = USB3DBG_UNINITIALIZED;
if (Usb3GetIoMmu () == NULL) {
Status = PeiServicesNotifyPpi (&mUsb3IoMmuPpiNotifyDesc);
@@ -219,18 +220,18 @@ GetUsb3DebugPortInstanceAddrPtr (
@return A pointer to the allocated buffer or NULL if allocation fails.
**/
VOID*
VOID *
AllocateAlignBuffer (
IN UINTN BufferSize
IN UINTN BufferSize
)
{
VOID *Buf;
EFI_PHYSICAL_ADDRESS Address;
EFI_STATUS Status;
VOID *MemoryDiscoveredPpi;
EDKII_IOMMU_PPI *IoMmu;
VOID *HostAddress;
VOID *Mapping;
VOID *Buf;
EFI_PHYSICAL_ADDRESS Address;
EFI_STATUS Status;
VOID *MemoryDiscoveredPpi;
EDKII_IOMMU_PPI *IoMmu;
VOID *HostAddress;
VOID *Mapping;
Buf = NULL;
@@ -241,7 +242,7 @@ AllocateAlignBuffer (
&gEfiPeiMemoryDiscoveredPpiGuid,
0,
NULL,
(VOID **) &MemoryDiscoveredPpi
(VOID **)&MemoryDiscoveredPpi
);
if (!EFI_ERROR (Status)) {
IoMmu = Usb3GetIoMmu ();
@@ -254,8 +255,8 @@ AllocateAlignBuffer (
&Mapping
);
if (!EFI_ERROR (Status)) {
ASSERT (Address == ((EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress));
Buf = (VOID *)(UINTN) Address;
ASSERT (Address == ((EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress));
Buf = (VOID *)(UINTN)Address;
}
} else {
Status = PeiServicesAllocatePages (
@@ -264,10 +265,10 @@ AllocateAlignBuffer (
&Address
);
if (!EFI_ERROR (Status)) {
Buf = (VOID *)(UINTN) Address;
Buf = (VOID *)(UINTN)Address;
}
}
}
return Buf;
}

181
SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/DebugCommunicationLibUsb3Transfer.c
View File

@@ -19,20 +19,20 @@
EFI_STATUS
EFIAPI
XhcSyncTrsRing (
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN TRANSFER_RING *TrsRing
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN TRANSFER_RING *TrsRing
)
{
UINTN Index;
TRB_TEMPLATE *TrsTrb;
UINT32 CycleBit;
UINTN Index;
TRB_TEMPLATE *TrsTrb;
UINT32 CycleBit;
ASSERT (TrsRing != NULL);
//
// Calculate the latest RingEnqueue and RingPCS
//
TrsTrb = (TRB_TEMPLATE *)(UINTN) TrsRing->RingEnqueue;
TrsTrb = (TRB_TEMPLATE *)(UINTN)TrsRing->RingEnqueue;
ASSERT (TrsTrb != NULL);
@@ -40,13 +40,14 @@ XhcSyncTrsRing (
if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) {
break;
}
TrsTrb++;
if ((UINT8) TrsTrb->Type == TRB_TYPE_LINK) {
ASSERT (((LINK_TRB*)TrsTrb)->TC != 0);
if ((UINT8)TrsTrb->Type == TRB_TYPE_LINK) {
ASSERT (((LINK_TRB *)TrsTrb)->TC != 0);
//
// set cycle bit in Link TRB as normal
//
((LINK_TRB*)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;
((LINK_TRB *)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;
//
// Toggle PCS maintained by software
//
@@ -54,10 +55,11 @@ XhcSyncTrsRing (
TrsTrb = (TRB_TEMPLATE *)(UINTN)((TrsTrb->Parameter1 | LShiftU64 ((UINT64)TrsTrb->Parameter2, 32)) & ~0x0F);
}
}
ASSERT (Index != TrsRing->TrbNumber);
if ((EFI_PHYSICAL_ADDRESS)(UINTN) TrsTrb != TrsRing->RingEnqueue) {
TrsRing->RingEnqueue = (EFI_PHYSICAL_ADDRESS)(UINTN) TrsTrb;
if ((EFI_PHYSICAL_ADDRESS)(UINTN)TrsTrb != TrsRing->RingEnqueue) {
TrsRing->RingEnqueue = (EFI_PHYSICAL_ADDRESS)(UINTN)TrsTrb;
}
//
@@ -83,11 +85,11 @@ EFI_STATUS
EFIAPI
XhcSyncEventRing (
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN EVENT_RING *EvtRing
IN EVENT_RING *EvtRing
)
{
UINTN Index;
TRB_TEMPLATE *EvtTrb1;
UINTN Index;
TRB_TEMPLATE *EvtTrb1;
ASSERT (EvtRing != NULL);
@@ -95,7 +97,7 @@ XhcSyncEventRing (
// Calculate the EventRingEnqueue and EventRingCCS.
// Note: only support single Segment
//
EvtTrb1 = (TRB_TEMPLATE *)(UINTN) EvtRing->EventRingDequeue;
EvtTrb1 = (TRB_TEMPLATE *)(UINTN)EvtRing->EventRingDequeue;
for (Index = 0; Index < EvtRing->TrbNumber; Index++) {
if (EvtTrb1->CycleBit != EvtRing->EventRingCCS) {
@@ -104,8 +106,8 @@ XhcSyncEventRing (
EvtTrb1++;
if ((UINTN)EvtTrb1 >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
EvtTrb1 = (TRB_TEMPLATE *)(UINTN) EvtRing->EventRingSeg0;
if ((UINTN)EvtTrb1 >= ((UINTN)EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
EvtTrb1 = (TRB_TEMPLATE *)(UINTN)EvtRing->EventRingSeg0;
EvtRing->EventRingCCS = (EvtRing->EventRingCCS) ? 0 : 1;
}
}
@@ -133,16 +135,16 @@ XhcSyncEventRing (
EFI_STATUS
EFIAPI
XhcCheckNewEvent (
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN EVENT_RING *EvtRing,
OUT TRB_TEMPLATE **NewEvtTrb
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN EVENT_RING *EvtRing,
OUT TRB_TEMPLATE **NewEvtTrb
)
{
EFI_STATUS Status;
EFI_STATUS Status;
ASSERT (EvtRing != NULL);
*NewEvtTrb = (TRB_TEMPLATE *)(UINTN) EvtRing->EventRingDequeue;
*NewEvtTrb = (TRB_TEMPLATE *)(UINTN)EvtRing->EventRingDequeue;
if (EvtRing->EventRingDequeue == EvtRing->EventRingEnqueue) {
return EFI_NOT_READY;
@@ -154,7 +156,7 @@ XhcCheckNewEvent (
//
// If the dequeue pointer is beyond the ring, then roll-back it to the beginning of the ring.
//
if ((UINTN)EvtRing->EventRingDequeue >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
if ((UINTN)EvtRing->EventRingDequeue >= ((UINTN)EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
EvtRing->EventRingDequeue = EvtRing->EventRingSeg0;
}
@@ -173,14 +175,14 @@ XhcCheckNewEvent (
**/
BOOLEAN
IsTrbInTrsRing (
IN TRANSFER_RING *Ring,
IN TRB_TEMPLATE *Trb
IN TRANSFER_RING *Ring,
IN TRB_TEMPLATE *Trb
)
{
TRB_TEMPLATE *CheckedTrb;
UINTN Index;
CheckedTrb = (TRB_TEMPLATE *)(UINTN) Ring->RingSeg0;
CheckedTrb = (TRB_TEMPLATE *)(UINTN)Ring->RingSeg0;
ASSERT (Ring->TrbNumber == TR_RING_TRB_NUMBER);
@@ -188,6 +190,7 @@ IsTrbInTrsRing (
if (Trb == CheckedTrb) {
return TRUE;
}
CheckedTrb++;
}
@@ -204,18 +207,18 @@ IsTrbInTrsRing (
**/
VOID
XhcCheckUrbResult (
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN URB *Urb
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN URB *Urb
)
{
EVT_TRB_TRANSFER *EvtTrb;
TRB_TEMPLATE *TRBPtr;
UINTN Index;
EFI_STATUS Status;
URB *CheckedUrb;
UINT64 XhcDequeue;
UINT32 High;
UINT32 Low;
EVT_TRB_TRANSFER *EvtTrb;
TRB_TEMPLATE *TRBPtr;
UINTN Index;
EFI_STATUS Status;
URB *CheckedUrb;
UINT64 XhcDequeue;
UINT32 High;
UINT32 Low;
ASSERT ((Handle != NULL) && (Urb != NULL));
@@ -231,7 +234,6 @@ XhcCheckUrbResult (
XhcSyncEventRing (Handle, &Handle->EventRing);
for (Index = 0; Index < Handle->EventRing.TrbNumber; Index++) {
Status = XhcCheckNewEvent (Handle, &Handle->EventRing, ((TRB_TEMPLATE **)&EvtTrb));
if (Status == EFI_NOT_READY) {
//
@@ -244,7 +246,7 @@ XhcCheckUrbResult (
continue;
}
TRBPtr = (TRB_TEMPLATE *)(UINTN)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64) EvtTrb->TRBPtrHi, 32));
TRBPtr = (TRB_TEMPLATE *)(UINTN)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64)EvtTrb->TRBPtrHi, 32));
if (IsTrbInTrsRing ((TRANSFER_RING *)(UINTN)(Urb->Ring), TRBPtr)) {
CheckedUrb = Urb;
@@ -253,7 +255,7 @@ XhcCheckUrbResult (
// If it is read event and it should be generated by poll, and current operation is write, we need save data into internal buffer.
// Internal buffer is used by next read.
//
Handle->DataCount = (UINT8) (Handle->UrbIn.DataLen - EvtTrb->Length);
Handle->DataCount = (UINT8)(Handle->UrbIn.DataLen - EvtTrb->Length);
CopyMem ((VOID *)(UINTN)Handle->Data, (VOID *)(UINTN)Handle->UrbIn.Data, Handle->DataCount);
//
// Fill this TRB complete with CycleBit, otherwise next read will fail with old TRB.
@@ -265,14 +267,16 @@ XhcCheckUrbResult (
}
if ((EvtTrb->Completecode == TRB_COMPLETION_SHORT_PACKET) ||
(EvtTrb->Completecode == TRB_COMPLETION_SUCCESS)) {
(EvtTrb->Completecode == TRB_COMPLETION_SUCCESS))
{
//
// The length of data which were transferred.
//
CheckedUrb->Completed += (((TRANSFER_TRB_NORMAL*)TRBPtr)->Length - EvtTrb->Length);
CheckedUrb->Completed += (((TRANSFER_TRB_NORMAL *)TRBPtr)->Length - EvtTrb->Length);
} else {
CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;
CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;
}
//
// This Urb has been processed
//
@@ -286,9 +290,9 @@ EXIT:
// Some 3rd party XHCI external cards don't support single 64-bytes width register access,
// So divide it to two 32-bytes width register access.
//
Low = XhcReadDebugReg (Handle, XHC_DC_DCERDP);
High = XhcReadDebugReg (Handle, XHC_DC_DCERDP + 4);
XhcDequeue = (UINT64)(LShiftU64((UINT64)High, 32) | Low);
Low = XhcReadDebugReg (Handle, XHC_DC_DCERDP);
High = XhcReadDebugReg (Handle, XHC_DC_DCERDP + 4);
XhcDequeue = (UINT64)(LShiftU64 ((UINT64)High, 32) | Low);
if ((XhcDequeue & (~0x0F)) != ((UINT64)(UINTN)Handle->EventRing.EventRingDequeue & (~0x0F))) {
//
@@ -312,11 +316,11 @@ EXIT:
EFI_STATUS
EFIAPI
XhcRingDoorBell (
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN URB *Urb
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN URB *Urb
)
{
UINT32 Dcdb;
UINT32 Dcdb;
//
// 7.6.8.2 DCDB Register
@@ -342,20 +346,21 @@ XhcRingDoorBell (
**/
VOID
XhcExecTransfer (
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN URB *Urb,
IN UINTN Timeout
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN URB *Urb,
IN UINTN Timeout
)
{
TRANSFER_RING *Ring;
TRB_TEMPLATE *Trb;
UINTN Loop;
UINTN Index;
TRANSFER_RING *Ring;
TRB_TEMPLATE *Trb;
UINTN Loop;
UINTN Index;
Loop = Timeout / XHC_DEBUG_PORT_1_MILLISECOND;
if (Timeout == 0) {
Loop = 0xFFFFFFFF;
}
XhcRingDoorBell (Handle, Urb);
//
// Event Ring Not Empty bit can only be set to 1 by XHC after ringing door bell with some delay.
@@ -365,19 +370,22 @@ XhcExecTransfer (
if (Urb->Finished) {
break;
}
MicroSecondDelay (XHC_DEBUG_PORT_1_MILLISECOND);
}
if (Index == Loop) {
//
// If time out occurs.
//
Urb->Result |= EFI_USB_ERR_TIMEOUT;
}
//
// If URB transfer is error, restore transfer ring to original value before URB transfer
// This will make the current transfer TRB is always at the latest unused one in transfer ring.
//
Ring = (TRANSFER_RING *)(UINTN) Urb->Ring;
Ring = (TRANSFER_RING *)(UINTN)Urb->Ring;
if ((Urb->Result != EFI_USB_NOERROR) && (Urb->Direction == EfiUsbDataIn)) {
//
// Adjust Enqueue pointer
@@ -386,7 +394,7 @@ XhcExecTransfer (
//
// Clear CCS flag for next use
//
Trb = (TRB_TEMPLATE *)(UINTN) Urb->Trb;
Trb = (TRB_TEMPLATE *)(UINTN)Urb->Trb;
Trb->CycleBit = ((~Ring->RingPCS) & BIT0);
} else {
//
@@ -407,12 +415,12 @@ XhcExecTransfer (
**/
EFI_STATUS
XhcCreateTransferTrb (
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN URB *Urb
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN URB *Urb
)
{
TRANSFER_RING *EPRing;
TRB *Trb;
TRANSFER_RING *EPRing;
TRB *Trb;
if (Urb->Direction == EfiUsbDataIn) {
EPRing = &Handle->TransferRingIn;
@@ -420,11 +428,11 @@ XhcCreateTransferTrb (
EPRing = &Handle->TransferRingOut;
}
Urb->Ring = (EFI_PHYSICAL_ADDRESS)(UINTN) EPRing;
Urb->Ring = (EFI_PHYSICAL_ADDRESS)(UINTN)EPRing;
XhcSyncTrsRing (Handle, EPRing);
Urb->Trb = EPRing->RingEnqueue;
Trb = (TRB *)(UINTN)EPRing->RingEnqueue;
Urb->Trb = EPRing->RingEnqueue;
Trb = (TRB *)(UINTN)EPRing->RingEnqueue;
Trb->TrbNormal.TRBPtrLo = XHC_LOW_32BIT (Urb->Data);
Trb->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT (Urb->Data);
Trb->TrbNormal.Length = Urb->DataLen;
@@ -453,17 +461,17 @@ XhcCreateTransferTrb (
@return Created URB or NULL
**/
URB*
URB *
XhcCreateUrb (
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN EFI_USB_DATA_DIRECTION Direction,
IN VOID *Data,
IN UINTN DataLen
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN EFI_USB_DATA_DIRECTION Direction,
IN VOID *Data,
IN UINTN DataLen
)
{
EFI_STATUS Status;
URB *Urb;
EFI_PHYSICAL_ADDRESS UrbData;
EFI_STATUS Status;
URB *Urb;
EFI_PHYSICAL_ADDRESS UrbData;
if (Direction == EfiUsbDataIn) {
Urb = &Handle->UrbIn;
@@ -471,7 +479,7 @@ XhcCreateUrb (
Urb = &Handle->UrbOut;
}
UrbData = Urb->Data;
UrbData = Urb->Data;
ZeroMem (Urb, sizeof (URB));
Urb->Direction = Direction;
@@ -481,20 +489,20 @@ XhcCreateUrb (
// to make XHCI DMA successfully
// re-use the pre-allocate buffer in PEI to avoid DXE memory service or gBS are not ready
//
Urb->Data = UrbData;
Urb->Data = UrbData;
if (Direction == EfiUsbDataIn) {
//
// Do not break URB data in buffer as it may contain the data which were just put in via DMA by XHC
//
Urb->DataLen = (UINT32) DataLen;
Urb->DataLen = (UINT32)DataLen;
} else {
//
// Put data into URB data out buffer which will create TRBs
//
ZeroMem ((VOID*)(UINTN) Urb->Data, DataLen);
CopyMem ((VOID*)(UINTN) Urb->Data, Data, DataLen);
Urb->DataLen = (UINT32) DataLen;
ZeroMem ((VOID *)(UINTN)Urb->Data, DataLen);
CopyMem ((VOID *)(UINTN)Urb->Data, Data, DataLen);
Urb->DataLen = (UINT32)DataLen;
}
Status = XhcCreateTransferTrb (Handle, Urb);
@@ -524,15 +532,15 @@ XhcCreateUrb (
EFI_STATUS
EFIAPI
XhcDataTransfer (
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN EFI_USB_DATA_DIRECTION Direction,
IN OUT VOID *Data,
IN OUT UINTN *DataLength,
IN UINTN Timeout
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN EFI_USB_DATA_DIRECTION Direction,
IN OUT VOID *Data,
IN OUT UINTN *DataLength,
IN UINTN Timeout
)
{
URB *Urb;
EFI_STATUS Status;
URB *Urb;
EFI_STATUS Status;
//
// Validate the parameters
@@ -557,7 +565,7 @@ XhcDataTransfer (
return EFI_DEVICE_ERROR;
}
*DataLength = Urb->Completed;
*DataLength = Urb->Completed;
Status = EFI_TIMEOUT;
if (Urb->Result == EFI_USB_NOERROR) {
@@ -574,4 +582,3 @@ XhcDataTransfer (
return Status;
}