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SourceLevelDebugPkg: Apply uncrustify changes

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the SourceLevelDebugPkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
This commit is contained in:
Michael Kubacki
2021-12-05 14:54:15 -08:00
committed by mergify[bot]
parent b878648967
commit c1e126b119
35 changed files with 3547 additions and 3381 deletions
Download Patch File Download Diff File Expand all files Collapse all files

181
SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/DebugCommunicationLibUsb3Transfer.c
View File

@ -19,20 +19,20 @@
EFI_STATUS
EFIAPI
XhcSyncTrsRing (
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN TRANSFER_RING *TrsRing
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN TRANSFER_RING *TrsRing
)
{
UINTN Index;
TRB_TEMPLATE *TrsTrb;
UINT32 CycleBit;
UINTN Index;
TRB_TEMPLATE *TrsTrb;
UINT32 CycleBit;
ASSERT (TrsRing != NULL);
//
// Calculate the latest RingEnqueue and RingPCS
//
TrsTrb = (TRB_TEMPLATE *)(UINTN) TrsRing->RingEnqueue;
TrsTrb = (TRB_TEMPLATE *)(UINTN)TrsRing->RingEnqueue;
ASSERT (TrsTrb != NULL);
@ -40,13 +40,14 @@ XhcSyncTrsRing (
if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) {
break;
}
TrsTrb++;
if ((UINT8) TrsTrb->Type == TRB_TYPE_LINK) {
ASSERT (((LINK_TRB*)TrsTrb)->TC != 0);
if ((UINT8)TrsTrb->Type == TRB_TYPE_LINK) {
ASSERT (((LINK_TRB *)TrsTrb)->TC != 0);
//
// set cycle bit in Link TRB as normal
//
((LINK_TRB*)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;
((LINK_TRB *)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;
//
// Toggle PCS maintained by software
//
@ -54,10 +55,11 @@ XhcSyncTrsRing (
TrsTrb = (TRB_TEMPLATE *)(UINTN)((TrsTrb->Parameter1 | LShiftU64 ((UINT64)TrsTrb->Parameter2, 32)) & ~0x0F);
}
}
ASSERT (Index != TrsRing->TrbNumber);
if ((EFI_PHYSICAL_ADDRESS)(UINTN) TrsTrb != TrsRing->RingEnqueue) {
TrsRing->RingEnqueue = (EFI_PHYSICAL_ADDRESS)(UINTN) TrsTrb;
if ((EFI_PHYSICAL_ADDRESS)(UINTN)TrsTrb != TrsRing->RingEnqueue) {
TrsRing->RingEnqueue = (EFI_PHYSICAL_ADDRESS)(UINTN)TrsTrb;
}
//
@ -83,11 +85,11 @@ EFI_STATUS
EFIAPI
XhcSyncEventRing (
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN EVENT_RING *EvtRing
IN EVENT_RING *EvtRing
)
{
UINTN Index;
TRB_TEMPLATE *EvtTrb1;
UINTN Index;
TRB_TEMPLATE *EvtTrb1;
ASSERT (EvtRing != NULL);
@ -95,7 +97,7 @@ XhcSyncEventRing (
// Calculate the EventRingEnqueue and EventRingCCS.
// Note: only support single Segment
//
EvtTrb1 = (TRB_TEMPLATE *)(UINTN) EvtRing->EventRingDequeue;
EvtTrb1 = (TRB_TEMPLATE *)(UINTN)EvtRing->EventRingDequeue;
for (Index = 0; Index < EvtRing->TrbNumber; Index++) {
if (EvtTrb1->CycleBit != EvtRing->EventRingCCS) {
@ -104,8 +106,8 @@ XhcSyncEventRing (
EvtTrb1++;
if ((UINTN)EvtTrb1 >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
EvtTrb1 = (TRB_TEMPLATE *)(UINTN) EvtRing->EventRingSeg0;
if ((UINTN)EvtTrb1 >= ((UINTN)EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
EvtTrb1 = (TRB_TEMPLATE *)(UINTN)EvtRing->EventRingSeg0;
EvtRing->EventRingCCS = (EvtRing->EventRingCCS) ? 0 : 1;
}
}
@ -133,16 +135,16 @@ XhcSyncEventRing (
EFI_STATUS
EFIAPI
XhcCheckNewEvent (
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN EVENT_RING *EvtRing,
OUT TRB_TEMPLATE **NewEvtTrb
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN EVENT_RING *EvtRing,
OUT TRB_TEMPLATE **NewEvtTrb
)
{
EFI_STATUS Status;
EFI_STATUS Status;
ASSERT (EvtRing != NULL);
*NewEvtTrb = (TRB_TEMPLATE *)(UINTN) EvtRing->EventRingDequeue;
*NewEvtTrb = (TRB_TEMPLATE *)(UINTN)EvtRing->EventRingDequeue;
if (EvtRing->EventRingDequeue == EvtRing->EventRingEnqueue) {
return EFI_NOT_READY;
@ -154,7 +156,7 @@ XhcCheckNewEvent (
//
// If the dequeue pointer is beyond the ring, then roll-back it to the beginning of the ring.
//
if ((UINTN)EvtRing->EventRingDequeue >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
if ((UINTN)EvtRing->EventRingDequeue >= ((UINTN)EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
EvtRing->EventRingDequeue = EvtRing->EventRingSeg0;
}
@ -173,14 +175,14 @@ XhcCheckNewEvent (
**/
BOOLEAN
IsTrbInTrsRing (
IN TRANSFER_RING *Ring,
IN TRB_TEMPLATE *Trb
IN TRANSFER_RING *Ring,
IN TRB_TEMPLATE *Trb
)
{
TRB_TEMPLATE *CheckedTrb;
UINTN Index;
CheckedTrb = (TRB_TEMPLATE *)(UINTN) Ring->RingSeg0;
CheckedTrb = (TRB_TEMPLATE *)(UINTN)Ring->RingSeg0;
ASSERT (Ring->TrbNumber == TR_RING_TRB_NUMBER);
@ -188,6 +190,7 @@ IsTrbInTrsRing (
if (Trb == CheckedTrb) {
return TRUE;
}
CheckedTrb++;
}
@ -204,18 +207,18 @@ IsTrbInTrsRing (
**/
VOID
XhcCheckUrbResult (
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN URB *Urb
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN URB *Urb
)
{
EVT_TRB_TRANSFER *EvtTrb;
TRB_TEMPLATE *TRBPtr;
UINTN Index;
EFI_STATUS Status;
URB *CheckedUrb;
UINT64 XhcDequeue;
UINT32 High;
UINT32 Low;
EVT_TRB_TRANSFER *EvtTrb;
TRB_TEMPLATE *TRBPtr;
UINTN Index;
EFI_STATUS Status;
URB *CheckedUrb;
UINT64 XhcDequeue;
UINT32 High;
UINT32 Low;
ASSERT ((Handle != NULL) && (Urb != NULL));
@ -231,7 +234,6 @@ XhcCheckUrbResult (
XhcSyncEventRing (Handle, &Handle->EventRing);
for (Index = 0; Index < Handle->EventRing.TrbNumber; Index++) {
Status = XhcCheckNewEvent (Handle, &Handle->EventRing, ((TRB_TEMPLATE **)&EvtTrb));
if (Status == EFI_NOT_READY) {
//
@ -244,7 +246,7 @@ XhcCheckUrbResult (
continue;
}
TRBPtr = (TRB_TEMPLATE *)(UINTN)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64) EvtTrb->TRBPtrHi, 32));
TRBPtr = (TRB_TEMPLATE *)(UINTN)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64)EvtTrb->TRBPtrHi, 32));
if (IsTrbInTrsRing ((TRANSFER_RING *)(UINTN)(Urb->Ring), TRBPtr)) {
CheckedUrb = Urb;
@ -253,7 +255,7 @@ XhcCheckUrbResult (
// If it is read event and it should be generated by poll, and current operation is write, we need save data into internal buffer.
// Internal buffer is used by next read.
//
Handle->DataCount = (UINT8) (Handle->UrbIn.DataLen - EvtTrb->Length);
Handle->DataCount = (UINT8)(Handle->UrbIn.DataLen - EvtTrb->Length);
CopyMem ((VOID *)(UINTN)Handle->Data, (VOID *)(UINTN)Handle->UrbIn.Data, Handle->DataCount);
//
// Fill this TRB complete with CycleBit, otherwise next read will fail with old TRB.
@ -265,14 +267,16 @@ XhcCheckUrbResult (
}
if ((EvtTrb->Completecode == TRB_COMPLETION_SHORT_PACKET) ||
(EvtTrb->Completecode == TRB_COMPLETION_SUCCESS)) {
(EvtTrb->Completecode == TRB_COMPLETION_SUCCESS))
{
//
// The length of data which were transferred.
//
CheckedUrb->Completed += (((TRANSFER_TRB_NORMAL*)TRBPtr)->Length - EvtTrb->Length);
CheckedUrb->Completed += (((TRANSFER_TRB_NORMAL *)TRBPtr)->Length - EvtTrb->Length);
} else {
CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;
CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;
}
//
// This Urb has been processed
//
@ -286,9 +290,9 @@ EXIT:
// Some 3rd party XHCI external cards don't support single 64-bytes width register access,
// So divide it to two 32-bytes width register access.
//
Low = XhcReadDebugReg (Handle, XHC_DC_DCERDP);
High = XhcReadDebugReg (Handle, XHC_DC_DCERDP + 4);
XhcDequeue = (UINT64)(LShiftU64((UINT64)High, 32) | Low);
Low = XhcReadDebugReg (Handle, XHC_DC_DCERDP);
High = XhcReadDebugReg (Handle, XHC_DC_DCERDP + 4);
XhcDequeue = (UINT64)(LShiftU64 ((UINT64)High, 32) | Low);
if ((XhcDequeue & (~0x0F)) != ((UINT64)(UINTN)Handle->EventRing.EventRingDequeue & (~0x0F))) {
//
@ -312,11 +316,11 @@ EXIT:
EFI_STATUS
EFIAPI
XhcRingDoorBell (
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN URB *Urb
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN URB *Urb
)
{
UINT32 Dcdb;
UINT32 Dcdb;
//
// 7.6.8.2 DCDB Register
@ -342,20 +346,21 @@ XhcRingDoorBell (
**/
VOID
XhcExecTransfer (
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN URB *Urb,
IN UINTN Timeout
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN URB *Urb,
IN UINTN Timeout
)
{
TRANSFER_RING *Ring;
TRB_TEMPLATE *Trb;
UINTN Loop;
UINTN Index;
TRANSFER_RING *Ring;
TRB_TEMPLATE *Trb;
UINTN Loop;
UINTN Index;
Loop = Timeout / XHC_DEBUG_PORT_1_MILLISECOND;
if (Timeout == 0) {
Loop = 0xFFFFFFFF;
}
XhcRingDoorBell (Handle, Urb);
//
// Event Ring Not Empty bit can only be set to 1 by XHC after ringing door bell with some delay.
@ -365,19 +370,22 @@ XhcExecTransfer (
if (Urb->Finished) {
break;
}
MicroSecondDelay (XHC_DEBUG_PORT_1_MILLISECOND);
}
if (Index == Loop) {
//
// If time out occurs.
//
Urb->Result |= EFI_USB_ERR_TIMEOUT;
}
//
// If URB transfer is error, restore transfer ring to original value before URB transfer
// This will make the current transfer TRB is always at the latest unused one in transfer ring.
//
Ring = (TRANSFER_RING *)(UINTN) Urb->Ring;
Ring = (TRANSFER_RING *)(UINTN)Urb->Ring;
if ((Urb->Result != EFI_USB_NOERROR) && (Urb->Direction == EfiUsbDataIn)) {
//
// Adjust Enqueue pointer
@ -386,7 +394,7 @@ XhcExecTransfer (
//
// Clear CCS flag for next use
//
Trb = (TRB_TEMPLATE *)(UINTN) Urb->Trb;
Trb = (TRB_TEMPLATE *)(UINTN)Urb->Trb;
Trb->CycleBit = ((~Ring->RingPCS) & BIT0);
} else {
//
@ -407,12 +415,12 @@ XhcExecTransfer (
**/
EFI_STATUS
XhcCreateTransferTrb (
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN URB *Urb
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN URB *Urb
)
{
TRANSFER_RING *EPRing;
TRB *Trb;
TRANSFER_RING *EPRing;
TRB *Trb;
if (Urb->Direction == EfiUsbDataIn) {
EPRing = &Handle->TransferRingIn;
@ -420,11 +428,11 @@ XhcCreateTransferTrb (
EPRing = &Handle->TransferRingOut;
}
Urb->Ring = (EFI_PHYSICAL_ADDRESS)(UINTN) EPRing;
Urb->Ring = (EFI_PHYSICAL_ADDRESS)(UINTN)EPRing;
XhcSyncTrsRing (Handle, EPRing);
Urb->Trb = EPRing->RingEnqueue;
Trb = (TRB *)(UINTN)EPRing->RingEnqueue;
Urb->Trb = EPRing->RingEnqueue;
Trb = (TRB *)(UINTN)EPRing->RingEnqueue;
Trb->TrbNormal.TRBPtrLo = XHC_LOW_32BIT (Urb->Data);
Trb->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT (Urb->Data);
Trb->TrbNormal.Length = Urb->DataLen;
@ -453,17 +461,17 @@ XhcCreateTransferTrb (
@return Created URB or NULL
**/
URB*
URB *
XhcCreateUrb (
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN EFI_USB_DATA_DIRECTION Direction,
IN VOID *Data,
IN UINTN DataLen
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN EFI_USB_DATA_DIRECTION Direction,
IN VOID *Data,
IN UINTN DataLen
)
{
EFI_STATUS Status;
URB *Urb;
EFI_PHYSICAL_ADDRESS UrbData;
EFI_STATUS Status;
URB *Urb;
EFI_PHYSICAL_ADDRESS UrbData;
if (Direction == EfiUsbDataIn) {
Urb = &Handle->UrbIn;
@ -471,7 +479,7 @@ XhcCreateUrb (
Urb = &Handle->UrbOut;
}
UrbData = Urb->Data;
UrbData = Urb->Data;
ZeroMem (Urb, sizeof (URB));
Urb->Direction = Direction;
@ -481,20 +489,20 @@ XhcCreateUrb (
// to make XHCI DMA successfully
// re-use the pre-allocate buffer in PEI to avoid DXE memory service or gBS are not ready
//
Urb->Data = UrbData;
Urb->Data = UrbData;
if (Direction == EfiUsbDataIn) {
//
// Do not break URB data in buffer as it may contain the data which were just put in via DMA by XHC
//
Urb->DataLen = (UINT32) DataLen;
Urb->DataLen = (UINT32)DataLen;
} else {
//
// Put data into URB data out buffer which will create TRBs
//
ZeroMem ((VOID*)(UINTN) Urb->Data, DataLen);
CopyMem ((VOID*)(UINTN) Urb->Data, Data, DataLen);
Urb->DataLen = (UINT32) DataLen;
ZeroMem ((VOID *)(UINTN)Urb->Data, DataLen);
CopyMem ((VOID *)(UINTN)Urb->Data, Data, DataLen);
Urb->DataLen = (UINT32)DataLen;
}
Status = XhcCreateTransferTrb (Handle, Urb);
@ -524,15 +532,15 @@ XhcCreateUrb (
EFI_STATUS
EFIAPI
XhcDataTransfer (
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN EFI_USB_DATA_DIRECTION Direction,
IN OUT VOID *Data,
IN OUT UINTN *DataLength,
IN UINTN Timeout
IN USB3_DEBUG_PORT_HANDLE *Handle,
IN EFI_USB_DATA_DIRECTION Direction,
IN OUT VOID *Data,
IN OUT UINTN *DataLength,
IN UINTN Timeout
)
{
URB *Urb;
EFI_STATUS Status;
URB *Urb;
EFI_STATUS Status;
//
// Validate the parameters
@ -557,7 +565,7 @@ XhcDataTransfer (
return EFI_DEVICE_ERROR;
}
*DataLength = Urb->Completed;
*DataLength = Urb->Completed;
Status = EFI_TIMEOUT;
if (Urb->Result == EFI_USB_NOERROR) {
@ -574,4 +582,3 @@ XhcDataTransfer (
return Status;
}